timing.cc revision 7720
12623SN/A/* 22623SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 32623SN/A * All rights reserved. 42623SN/A * 52623SN/A * Redistribution and use in source and binary forms, with or without 62623SN/A * modification, are permitted provided that the following conditions are 72623SN/A * met: redistributions of source code must retain the above copyright 82623SN/A * notice, this list of conditions and the following disclaimer; 92623SN/A * redistributions in binary form must reproduce the above copyright 102623SN/A * notice, this list of conditions and the following disclaimer in the 112623SN/A * documentation and/or other materials provided with the distribution; 122623SN/A * neither the name of the copyright holders nor the names of its 132623SN/A * contributors may be used to endorse or promote products derived from 142623SN/A * this software without specific prior written permission. 152623SN/A * 162623SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172623SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182623SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192623SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202623SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212623SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222623SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232623SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242623SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252623SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262623SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 292623SN/A */ 302623SN/A 313170Sstever@eecs.umich.edu#include "arch/locked_mem.hh" 325103Ssaidi@eecs.umich.edu#include "arch/mmaped_ipr.hh" 332623SN/A#include "arch/utility.hh" 344040Ssaidi@eecs.umich.edu#include "base/bigint.hh" 356658Snate@binkert.org#include "config/the_isa.hh" 362623SN/A#include "cpu/exetrace.hh" 372623SN/A#include "cpu/simple/timing.hh" 383348Sbinkertn@umich.edu#include "mem/packet.hh" 393348Sbinkertn@umich.edu#include "mem/packet_access.hh" 404762Snate@binkert.org#include "params/TimingSimpleCPU.hh" 417678Sgblack@eecs.umich.edu#include "sim/faults.hh" 422901Ssaidi@eecs.umich.edu#include "sim/system.hh" 432623SN/A 442623SN/Ausing namespace std; 452623SN/Ausing namespace TheISA; 462623SN/A 472856Srdreslin@umich.eduPort * 482856Srdreslin@umich.eduTimingSimpleCPU::getPort(const std::string &if_name, int idx) 492856Srdreslin@umich.edu{ 502856Srdreslin@umich.edu if (if_name == "dcache_port") 512856Srdreslin@umich.edu return &dcachePort; 522856Srdreslin@umich.edu else if (if_name == "icache_port") 532856Srdreslin@umich.edu return &icachePort; 542856Srdreslin@umich.edu else 552856Srdreslin@umich.edu panic("No Such Port\n"); 562856Srdreslin@umich.edu} 572623SN/A 582623SN/Avoid 592623SN/ATimingSimpleCPU::init() 602623SN/A{ 612623SN/A BaseCPU::init(); 622623SN/A#if FULL_SYSTEM 632680Sktlim@umich.edu for (int i = 0; i < threadContexts.size(); ++i) { 642680Sktlim@umich.edu ThreadContext *tc = threadContexts[i]; 652623SN/A 662623SN/A // initialize CPU, including PC 675712Shsul@eecs.umich.edu TheISA::initCPU(tc, _cpuId); 682623SN/A } 692623SN/A#endif 702623SN/A} 712623SN/A 722623SN/ATick 733349Sbinkertn@umich.eduTimingSimpleCPU::CpuPort::recvAtomic(PacketPtr pkt) 742623SN/A{ 752623SN/A panic("TimingSimpleCPU doesn't expect recvAtomic callback!"); 762623SN/A return curTick; 772623SN/A} 782623SN/A 792623SN/Avoid 803349Sbinkertn@umich.eduTimingSimpleCPU::CpuPort::recvFunctional(PacketPtr pkt) 812623SN/A{ 823184Srdreslin@umich.edu //No internal storage to update, jusst return 833184Srdreslin@umich.edu return; 842623SN/A} 852623SN/A 862623SN/Avoid 872623SN/ATimingSimpleCPU::CpuPort::recvStatusChange(Status status) 882623SN/A{ 893647Srdreslin@umich.edu if (status == RangeChange) { 903647Srdreslin@umich.edu if (!snoopRangeSent) { 913647Srdreslin@umich.edu snoopRangeSent = true; 923647Srdreslin@umich.edu sendStatusChange(Port::RangeChange); 933647Srdreslin@umich.edu } 942631SN/A return; 953647Srdreslin@umich.edu } 962631SN/A 972623SN/A panic("TimingSimpleCPU doesn't expect recvStatusChange callback!"); 982623SN/A} 992623SN/A 1002948Ssaidi@eecs.umich.edu 1012948Ssaidi@eecs.umich.eduvoid 1023349Sbinkertn@umich.eduTimingSimpleCPU::CpuPort::TickEvent::schedule(PacketPtr _pkt, Tick t) 1032948Ssaidi@eecs.umich.edu{ 1042948Ssaidi@eecs.umich.edu pkt = _pkt; 1055606Snate@binkert.org cpu->schedule(this, t); 1062948Ssaidi@eecs.umich.edu} 1072948Ssaidi@eecs.umich.edu 1085529Snate@binkert.orgTimingSimpleCPU::TimingSimpleCPU(TimingSimpleCPUParams *p) 1095894Sgblack@eecs.umich.edu : BaseSimpleCPU(p), fetchTranslation(this), icachePort(this, p->clock), 1105894Sgblack@eecs.umich.edu dcachePort(this, p->clock), fetchEvent(this) 1112623SN/A{ 1122623SN/A _status = Idle; 1133647Srdreslin@umich.edu 1143647Srdreslin@umich.edu icachePort.snoopRangeSent = false; 1153647Srdreslin@umich.edu dcachePort.snoopRangeSent = false; 1163647Srdreslin@umich.edu 1172623SN/A ifetch_pkt = dcache_pkt = NULL; 1182839Sktlim@umich.edu drainEvent = NULL; 1193222Sktlim@umich.edu previousTick = 0; 1202901Ssaidi@eecs.umich.edu changeState(SimObject::Running); 1212623SN/A} 1222623SN/A 1232623SN/A 1242623SN/ATimingSimpleCPU::~TimingSimpleCPU() 1252623SN/A{ 1262623SN/A} 1272623SN/A 1282623SN/Avoid 1292623SN/ATimingSimpleCPU::serialize(ostream &os) 1302623SN/A{ 1312915Sktlim@umich.edu SimObject::State so_state = SimObject::getState(); 1322915Sktlim@umich.edu SERIALIZE_ENUM(so_state); 1332623SN/A BaseSimpleCPU::serialize(os); 1342623SN/A} 1352623SN/A 1362623SN/Avoid 1372623SN/ATimingSimpleCPU::unserialize(Checkpoint *cp, const string §ion) 1382623SN/A{ 1392915Sktlim@umich.edu SimObject::State so_state; 1402915Sktlim@umich.edu UNSERIALIZE_ENUM(so_state); 1412623SN/A BaseSimpleCPU::unserialize(cp, section); 1422798Sktlim@umich.edu} 1432798Sktlim@umich.edu 1442901Ssaidi@eecs.umich.eduunsigned int 1452839Sktlim@umich.eduTimingSimpleCPU::drain(Event *drain_event) 1462798Sktlim@umich.edu{ 1472839Sktlim@umich.edu // TimingSimpleCPU is ready to drain if it's not waiting for 1482798Sktlim@umich.edu // an access to complete. 1495496Ssaidi@eecs.umich.edu if (_status == Idle || _status == Running || _status == SwitchedOut) { 1502901Ssaidi@eecs.umich.edu changeState(SimObject::Drained); 1512901Ssaidi@eecs.umich.edu return 0; 1522798Sktlim@umich.edu } else { 1532839Sktlim@umich.edu changeState(SimObject::Draining); 1542839Sktlim@umich.edu drainEvent = drain_event; 1552901Ssaidi@eecs.umich.edu return 1; 1562798Sktlim@umich.edu } 1572623SN/A} 1582623SN/A 1592623SN/Avoid 1602798Sktlim@umich.eduTimingSimpleCPU::resume() 1612623SN/A{ 1625221Ssaidi@eecs.umich.edu DPRINTF(SimpleCPU, "Resume\n"); 1632798Sktlim@umich.edu if (_status != SwitchedOut && _status != Idle) { 1644762Snate@binkert.org assert(system->getMemoryMode() == Enums::timing); 1653201Shsul@eecs.umich.edu 1665710Scws3k@cs.virginia.edu if (fetchEvent.scheduled()) 1675710Scws3k@cs.virginia.edu deschedule(fetchEvent); 1682915Sktlim@umich.edu 1695710Scws3k@cs.virginia.edu schedule(fetchEvent, nextCycle()); 1702623SN/A } 1712798Sktlim@umich.edu 1722901Ssaidi@eecs.umich.edu changeState(SimObject::Running); 1732798Sktlim@umich.edu} 1742798Sktlim@umich.edu 1752798Sktlim@umich.eduvoid 1762798Sktlim@umich.eduTimingSimpleCPU::switchOut() 1772798Sktlim@umich.edu{ 1785496Ssaidi@eecs.umich.edu assert(_status == Running || _status == Idle); 1792798Sktlim@umich.edu _status = SwitchedOut; 1805099Ssaidi@eecs.umich.edu numCycles += tickToCycles(curTick - previousTick); 1812867Sktlim@umich.edu 1822867Sktlim@umich.edu // If we've been scheduled to resume but are then told to switch out, 1832867Sktlim@umich.edu // we'll need to cancel it. 1845710Scws3k@cs.virginia.edu if (fetchEvent.scheduled()) 1855606Snate@binkert.org deschedule(fetchEvent); 1862623SN/A} 1872623SN/A 1882623SN/A 1892623SN/Avoid 1902623SN/ATimingSimpleCPU::takeOverFrom(BaseCPU *oldCPU) 1912623SN/A{ 1924192Sktlim@umich.edu BaseCPU::takeOverFrom(oldCPU, &icachePort, &dcachePort); 1932623SN/A 1942680Sktlim@umich.edu // if any of this CPU's ThreadContexts are active, mark the CPU as 1952623SN/A // running and schedule its tick event. 1962680Sktlim@umich.edu for (int i = 0; i < threadContexts.size(); ++i) { 1972680Sktlim@umich.edu ThreadContext *tc = threadContexts[i]; 1982680Sktlim@umich.edu if (tc->status() == ThreadContext::Active && _status != Running) { 1992623SN/A _status = Running; 2002623SN/A break; 2012623SN/A } 2022623SN/A } 2033201Shsul@eecs.umich.edu 2043201Shsul@eecs.umich.edu if (_status != Running) { 2053201Shsul@eecs.umich.edu _status = Idle; 2063201Shsul@eecs.umich.edu } 2075169Ssaidi@eecs.umich.edu assert(threadContexts.size() == 1); 2085101Ssaidi@eecs.umich.edu previousTick = curTick; 2092623SN/A} 2102623SN/A 2112623SN/A 2122623SN/Avoid 2132623SN/ATimingSimpleCPU::activateContext(int thread_num, int delay) 2142623SN/A{ 2155221Ssaidi@eecs.umich.edu DPRINTF(SimpleCPU, "ActivateContext %d (%d cycles)\n", thread_num, delay); 2165221Ssaidi@eecs.umich.edu 2172623SN/A assert(thread_num == 0); 2182683Sktlim@umich.edu assert(thread); 2192623SN/A 2202623SN/A assert(_status == Idle); 2212623SN/A 2222623SN/A notIdleFraction++; 2232623SN/A _status = Running; 2243686Sktlim@umich.edu 2252623SN/A // kick things off by initiating the fetch of the next instruction 2265606Snate@binkert.org schedule(fetchEvent, nextCycle(curTick + ticks(delay))); 2272623SN/A} 2282623SN/A 2292623SN/A 2302623SN/Avoid 2312623SN/ATimingSimpleCPU::suspendContext(int thread_num) 2322623SN/A{ 2335221Ssaidi@eecs.umich.edu DPRINTF(SimpleCPU, "SuspendContext %d\n", thread_num); 2345221Ssaidi@eecs.umich.edu 2352623SN/A assert(thread_num == 0); 2362683Sktlim@umich.edu assert(thread); 2372623SN/A 2386043Sgblack@eecs.umich.edu if (_status == Idle) 2396043Sgblack@eecs.umich.edu return; 2406043Sgblack@eecs.umich.edu 2412644Sstever@eecs.umich.edu assert(_status == Running); 2422623SN/A 2432644Sstever@eecs.umich.edu // just change status to Idle... if status != Running, 2442644Sstever@eecs.umich.edu // completeInst() will not initiate fetch of next instruction. 2452623SN/A 2462623SN/A notIdleFraction--; 2472623SN/A _status = Idle; 2482623SN/A} 2492623SN/A 2505728Sgblack@eecs.umich.edubool 2515728Sgblack@eecs.umich.eduTimingSimpleCPU::handleReadPacket(PacketPtr pkt) 2525728Sgblack@eecs.umich.edu{ 2535728Sgblack@eecs.umich.edu RequestPtr req = pkt->req; 2545728Sgblack@eecs.umich.edu if (req->isMmapedIpr()) { 2555728Sgblack@eecs.umich.edu Tick delay; 2565728Sgblack@eecs.umich.edu delay = TheISA::handleIprRead(thread->getTC(), pkt); 2575728Sgblack@eecs.umich.edu new IprEvent(pkt, this, nextCycle(curTick + delay)); 2585728Sgblack@eecs.umich.edu _status = DcacheWaitResponse; 2595728Sgblack@eecs.umich.edu dcache_pkt = NULL; 2605728Sgblack@eecs.umich.edu } else if (!dcachePort.sendTiming(pkt)) { 2615728Sgblack@eecs.umich.edu _status = DcacheRetry; 2625728Sgblack@eecs.umich.edu dcache_pkt = pkt; 2635728Sgblack@eecs.umich.edu } else { 2645728Sgblack@eecs.umich.edu _status = DcacheWaitResponse; 2655728Sgblack@eecs.umich.edu // memory system takes ownership of packet 2665728Sgblack@eecs.umich.edu dcache_pkt = NULL; 2675728Sgblack@eecs.umich.edu } 2685728Sgblack@eecs.umich.edu return dcache_pkt == NULL; 2695728Sgblack@eecs.umich.edu} 2702623SN/A 2715894Sgblack@eecs.umich.eduvoid 2726973Stjones1@inf.ed.ac.ukTimingSimpleCPU::sendData(RequestPtr req, uint8_t *data, uint64_t *res, 2736973Stjones1@inf.ed.ac.uk bool read) 2745744Sgblack@eecs.umich.edu{ 2755894Sgblack@eecs.umich.edu PacketPtr pkt; 2765894Sgblack@eecs.umich.edu buildPacket(pkt, req, read); 2777691SAli.Saidi@ARM.com pkt->dataDynamicArray<uint8_t>(data); 2785894Sgblack@eecs.umich.edu if (req->getFlags().isSet(Request::NO_ACCESS)) { 2795894Sgblack@eecs.umich.edu assert(!dcache_pkt); 2805894Sgblack@eecs.umich.edu pkt->makeResponse(); 2815894Sgblack@eecs.umich.edu completeDataAccess(pkt); 2825894Sgblack@eecs.umich.edu } else if (read) { 2835894Sgblack@eecs.umich.edu handleReadPacket(pkt); 2845894Sgblack@eecs.umich.edu } else { 2855894Sgblack@eecs.umich.edu bool do_access = true; // flag to suppress cache access 2865894Sgblack@eecs.umich.edu 2876102Sgblack@eecs.umich.edu if (req->isLLSC()) { 2885894Sgblack@eecs.umich.edu do_access = TheISA::handleLockedWrite(thread, req); 2895894Sgblack@eecs.umich.edu } else if (req->isCondSwap()) { 2905894Sgblack@eecs.umich.edu assert(res); 2915894Sgblack@eecs.umich.edu req->setExtraData(*res); 2925894Sgblack@eecs.umich.edu } 2935894Sgblack@eecs.umich.edu 2945894Sgblack@eecs.umich.edu if (do_access) { 2955894Sgblack@eecs.umich.edu dcache_pkt = pkt; 2965894Sgblack@eecs.umich.edu handleWritePacket(); 2975894Sgblack@eecs.umich.edu } else { 2985894Sgblack@eecs.umich.edu _status = DcacheWaitResponse; 2995894Sgblack@eecs.umich.edu completeDataAccess(pkt); 3005894Sgblack@eecs.umich.edu } 3015894Sgblack@eecs.umich.edu } 3025894Sgblack@eecs.umich.edu} 3035894Sgblack@eecs.umich.edu 3045894Sgblack@eecs.umich.eduvoid 3056973Stjones1@inf.ed.ac.ukTimingSimpleCPU::sendSplitData(RequestPtr req1, RequestPtr req2, 3066973Stjones1@inf.ed.ac.uk RequestPtr req, uint8_t *data, bool read) 3075894Sgblack@eecs.umich.edu{ 3085894Sgblack@eecs.umich.edu PacketPtr pkt1, pkt2; 3095894Sgblack@eecs.umich.edu buildSplitPacket(pkt1, pkt2, req1, req2, req, data, read); 3105894Sgblack@eecs.umich.edu if (req->getFlags().isSet(Request::NO_ACCESS)) { 3115894Sgblack@eecs.umich.edu assert(!dcache_pkt); 3125894Sgblack@eecs.umich.edu pkt1->makeResponse(); 3135894Sgblack@eecs.umich.edu completeDataAccess(pkt1); 3145894Sgblack@eecs.umich.edu } else if (read) { 3155894Sgblack@eecs.umich.edu if (handleReadPacket(pkt1)) { 3165894Sgblack@eecs.umich.edu SplitFragmentSenderState * send_state = 3175894Sgblack@eecs.umich.edu dynamic_cast<SplitFragmentSenderState *>(pkt1->senderState); 3185894Sgblack@eecs.umich.edu send_state->clearFromParent(); 3195894Sgblack@eecs.umich.edu if (handleReadPacket(pkt2)) { 3205894Sgblack@eecs.umich.edu send_state = dynamic_cast<SplitFragmentSenderState *>( 3215894Sgblack@eecs.umich.edu pkt1->senderState); 3225894Sgblack@eecs.umich.edu send_state->clearFromParent(); 3235894Sgblack@eecs.umich.edu } 3245894Sgblack@eecs.umich.edu } 3255894Sgblack@eecs.umich.edu } else { 3265894Sgblack@eecs.umich.edu dcache_pkt = pkt1; 3275894Sgblack@eecs.umich.edu if (handleWritePacket()) { 3285894Sgblack@eecs.umich.edu SplitFragmentSenderState * send_state = 3295894Sgblack@eecs.umich.edu dynamic_cast<SplitFragmentSenderState *>(pkt1->senderState); 3305894Sgblack@eecs.umich.edu send_state->clearFromParent(); 3315894Sgblack@eecs.umich.edu dcache_pkt = pkt2; 3325894Sgblack@eecs.umich.edu if (handleWritePacket()) { 3335894Sgblack@eecs.umich.edu send_state = dynamic_cast<SplitFragmentSenderState *>( 3345894Sgblack@eecs.umich.edu pkt1->senderState); 3355894Sgblack@eecs.umich.edu send_state->clearFromParent(); 3365894Sgblack@eecs.umich.edu } 3375894Sgblack@eecs.umich.edu } 3385894Sgblack@eecs.umich.edu } 3395894Sgblack@eecs.umich.edu} 3405894Sgblack@eecs.umich.edu 3415894Sgblack@eecs.umich.eduvoid 3425894Sgblack@eecs.umich.eduTimingSimpleCPU::translationFault(Fault fault) 3435894Sgblack@eecs.umich.edu{ 3446739Sgblack@eecs.umich.edu // fault may be NoFault in cases where a fault is suppressed, 3456739Sgblack@eecs.umich.edu // for instance prefetches. 3465894Sgblack@eecs.umich.edu numCycles += tickToCycles(curTick - previousTick); 3475894Sgblack@eecs.umich.edu previousTick = curTick; 3485894Sgblack@eecs.umich.edu 3495894Sgblack@eecs.umich.edu if (traceData) { 3505894Sgblack@eecs.umich.edu // Since there was a fault, we shouldn't trace this instruction. 3515894Sgblack@eecs.umich.edu delete traceData; 3525894Sgblack@eecs.umich.edu traceData = NULL; 3535744Sgblack@eecs.umich.edu } 3545744Sgblack@eecs.umich.edu 3555894Sgblack@eecs.umich.edu postExecute(); 3565894Sgblack@eecs.umich.edu 3575894Sgblack@eecs.umich.edu if (getState() == SimObject::Draining) { 3585894Sgblack@eecs.umich.edu advancePC(fault); 3595894Sgblack@eecs.umich.edu completeDrain(); 3605894Sgblack@eecs.umich.edu } else { 3615894Sgblack@eecs.umich.edu advanceInst(fault); 3625894Sgblack@eecs.umich.edu } 3635894Sgblack@eecs.umich.edu} 3645894Sgblack@eecs.umich.edu 3655894Sgblack@eecs.umich.eduvoid 3665894Sgblack@eecs.umich.eduTimingSimpleCPU::buildPacket(PacketPtr &pkt, RequestPtr req, bool read) 3675894Sgblack@eecs.umich.edu{ 3685894Sgblack@eecs.umich.edu MemCmd cmd; 3695894Sgblack@eecs.umich.edu if (read) { 3705894Sgblack@eecs.umich.edu cmd = MemCmd::ReadReq; 3716102Sgblack@eecs.umich.edu if (req->isLLSC()) 3725894Sgblack@eecs.umich.edu cmd = MemCmd::LoadLockedReq; 3735894Sgblack@eecs.umich.edu } else { 3745894Sgblack@eecs.umich.edu cmd = MemCmd::WriteReq; 3756102Sgblack@eecs.umich.edu if (req->isLLSC()) { 3765894Sgblack@eecs.umich.edu cmd = MemCmd::StoreCondReq; 3775894Sgblack@eecs.umich.edu } else if (req->isSwap()) { 3785894Sgblack@eecs.umich.edu cmd = MemCmd::SwapReq; 3795894Sgblack@eecs.umich.edu } 3805894Sgblack@eecs.umich.edu } 3815894Sgblack@eecs.umich.edu pkt = new Packet(req, cmd, Packet::Broadcast); 3825894Sgblack@eecs.umich.edu} 3835894Sgblack@eecs.umich.edu 3845894Sgblack@eecs.umich.eduvoid 3855894Sgblack@eecs.umich.eduTimingSimpleCPU::buildSplitPacket(PacketPtr &pkt1, PacketPtr &pkt2, 3865894Sgblack@eecs.umich.edu RequestPtr req1, RequestPtr req2, RequestPtr req, 3875894Sgblack@eecs.umich.edu uint8_t *data, bool read) 3885894Sgblack@eecs.umich.edu{ 3895894Sgblack@eecs.umich.edu pkt1 = pkt2 = NULL; 3905894Sgblack@eecs.umich.edu 3915744Sgblack@eecs.umich.edu assert(!req1->isMmapedIpr() && !req2->isMmapedIpr()); 3925744Sgblack@eecs.umich.edu 3935894Sgblack@eecs.umich.edu if (req->getFlags().isSet(Request::NO_ACCESS)) { 3945894Sgblack@eecs.umich.edu buildPacket(pkt1, req, read); 3955894Sgblack@eecs.umich.edu return; 3965894Sgblack@eecs.umich.edu } 3975894Sgblack@eecs.umich.edu 3985894Sgblack@eecs.umich.edu buildPacket(pkt1, req1, read); 3995894Sgblack@eecs.umich.edu buildPacket(pkt2, req2, read); 4005894Sgblack@eecs.umich.edu 4015744Sgblack@eecs.umich.edu req->setPhys(req1->getPaddr(), req->getSize(), req1->getFlags()); 4025744Sgblack@eecs.umich.edu PacketPtr pkt = new Packet(req, pkt1->cmd.responseCommand(), 4035744Sgblack@eecs.umich.edu Packet::Broadcast); 4045744Sgblack@eecs.umich.edu 4057691SAli.Saidi@ARM.com pkt->dataDynamicArray<uint8_t>(data); 4065744Sgblack@eecs.umich.edu pkt1->dataStatic<uint8_t>(data); 4075744Sgblack@eecs.umich.edu pkt2->dataStatic<uint8_t>(data + req1->getSize()); 4085744Sgblack@eecs.umich.edu 4095744Sgblack@eecs.umich.edu SplitMainSenderState * main_send_state = new SplitMainSenderState; 4105744Sgblack@eecs.umich.edu pkt->senderState = main_send_state; 4115744Sgblack@eecs.umich.edu main_send_state->fragments[0] = pkt1; 4125744Sgblack@eecs.umich.edu main_send_state->fragments[1] = pkt2; 4135744Sgblack@eecs.umich.edu main_send_state->outstanding = 2; 4145744Sgblack@eecs.umich.edu pkt1->senderState = new SplitFragmentSenderState(pkt, 0); 4155744Sgblack@eecs.umich.edu pkt2->senderState = new SplitFragmentSenderState(pkt, 1); 4165744Sgblack@eecs.umich.edu} 4175744Sgblack@eecs.umich.edu 4182623SN/AFault 4197520Sgblack@eecs.umich.eduTimingSimpleCPU::readBytes(Addr addr, uint8_t *data, 4207520Sgblack@eecs.umich.edu unsigned size, unsigned flags) 4212623SN/A{ 4225728Sgblack@eecs.umich.edu Fault fault; 4235728Sgblack@eecs.umich.edu const int asid = 0; 4246221Snate@binkert.org const ThreadID tid = 0; 4257720Sgblack@eecs.umich.edu const Addr pc = thread->instAddr(); 4266227Snate@binkert.org unsigned block_size = dcachePort.peerBlockSize(); 4276973Stjones1@inf.ed.ac.uk BaseTLB::Mode mode = BaseTLB::Read; 4282623SN/A 4297045Ssteve.reinhardt@amd.com if (traceData) { 4307045Ssteve.reinhardt@amd.com traceData->setAddr(addr); 4317045Ssteve.reinhardt@amd.com } 4327045Ssteve.reinhardt@amd.com 4337520Sgblack@eecs.umich.edu RequestPtr req = new Request(asid, addr, size, 4346221Snate@binkert.org flags, pc, _cpuId, tid); 4355728Sgblack@eecs.umich.edu 4367520Sgblack@eecs.umich.edu Addr split_addr = roundDown(addr + size - 1, block_size); 4375744Sgblack@eecs.umich.edu assert(split_addr <= addr || split_addr - addr < block_size); 4385728Sgblack@eecs.umich.edu 4395894Sgblack@eecs.umich.edu _status = DTBWaitResponse; 4405744Sgblack@eecs.umich.edu if (split_addr > addr) { 4415894Sgblack@eecs.umich.edu RequestPtr req1, req2; 4426102Sgblack@eecs.umich.edu assert(!req->isLLSC() && !req->isSwap()); 4435894Sgblack@eecs.umich.edu req->splitOnVaddr(split_addr, req1, req2); 4445894Sgblack@eecs.umich.edu 4456973Stjones1@inf.ed.ac.uk WholeTranslationState *state = 4467520Sgblack@eecs.umich.edu new WholeTranslationState(req, req1, req2, new uint8_t[size], 4476973Stjones1@inf.ed.ac.uk NULL, mode); 4486973Stjones1@inf.ed.ac.uk DataTranslation<TimingSimpleCPU> *trans1 = 4496973Stjones1@inf.ed.ac.uk new DataTranslation<TimingSimpleCPU>(this, state, 0); 4506973Stjones1@inf.ed.ac.uk DataTranslation<TimingSimpleCPU> *trans2 = 4516973Stjones1@inf.ed.ac.uk new DataTranslation<TimingSimpleCPU>(this, state, 1); 4526973Stjones1@inf.ed.ac.uk 4536973Stjones1@inf.ed.ac.uk thread->dtb->translateTiming(req1, tc, trans1, mode); 4546973Stjones1@inf.ed.ac.uk thread->dtb->translateTiming(req2, tc, trans2, mode); 4555744Sgblack@eecs.umich.edu } else { 4566973Stjones1@inf.ed.ac.uk WholeTranslationState *state = 4577520Sgblack@eecs.umich.edu new WholeTranslationState(req, new uint8_t[size], NULL, mode); 4586973Stjones1@inf.ed.ac.uk DataTranslation<TimingSimpleCPU> *translation 4596973Stjones1@inf.ed.ac.uk = new DataTranslation<TimingSimpleCPU>(this, state); 4606973Stjones1@inf.ed.ac.uk thread->dtb->translateTiming(req, tc, translation, mode); 4612623SN/A } 4622623SN/A 4635728Sgblack@eecs.umich.edu return NoFault; 4642623SN/A} 4652623SN/A 4667520Sgblack@eecs.umich.edutemplate <class T> 4677520Sgblack@eecs.umich.eduFault 4687520Sgblack@eecs.umich.eduTimingSimpleCPU::read(Addr addr, T &data, unsigned flags) 4697520Sgblack@eecs.umich.edu{ 4707520Sgblack@eecs.umich.edu return readBytes(addr, (uint8_t *)&data, sizeof(T), flags); 4717520Sgblack@eecs.umich.edu} 4727520Sgblack@eecs.umich.edu 4732623SN/A#ifndef DOXYGEN_SHOULD_SKIP_THIS 4742623SN/A 4752623SN/Atemplate 4762623SN/AFault 4774040Ssaidi@eecs.umich.eduTimingSimpleCPU::read(Addr addr, Twin64_t &data, unsigned flags); 4784040Ssaidi@eecs.umich.edu 4794040Ssaidi@eecs.umich.edutemplate 4804040Ssaidi@eecs.umich.eduFault 4814115Ssaidi@eecs.umich.eduTimingSimpleCPU::read(Addr addr, Twin32_t &data, unsigned flags); 4824115Ssaidi@eecs.umich.edu 4834115Ssaidi@eecs.umich.edutemplate 4844115Ssaidi@eecs.umich.eduFault 4852623SN/ATimingSimpleCPU::read(Addr addr, uint64_t &data, unsigned flags); 4862623SN/A 4872623SN/Atemplate 4882623SN/AFault 4892623SN/ATimingSimpleCPU::read(Addr addr, uint32_t &data, unsigned flags); 4902623SN/A 4912623SN/Atemplate 4922623SN/AFault 4932623SN/ATimingSimpleCPU::read(Addr addr, uint16_t &data, unsigned flags); 4942623SN/A 4952623SN/Atemplate 4962623SN/AFault 4972623SN/ATimingSimpleCPU::read(Addr addr, uint8_t &data, unsigned flags); 4982623SN/A 4992623SN/A#endif //DOXYGEN_SHOULD_SKIP_THIS 5002623SN/A 5012623SN/Atemplate<> 5022623SN/AFault 5032623SN/ATimingSimpleCPU::read(Addr addr, double &data, unsigned flags) 5042623SN/A{ 5052623SN/A return read(addr, *(uint64_t*)&data, flags); 5062623SN/A} 5072623SN/A 5082623SN/Atemplate<> 5092623SN/AFault 5102623SN/ATimingSimpleCPU::read(Addr addr, float &data, unsigned flags) 5112623SN/A{ 5122623SN/A return read(addr, *(uint32_t*)&data, flags); 5132623SN/A} 5142623SN/A 5152623SN/Atemplate<> 5162623SN/AFault 5172623SN/ATimingSimpleCPU::read(Addr addr, int32_t &data, unsigned flags) 5182623SN/A{ 5192623SN/A return read(addr, (uint32_t&)data, flags); 5202623SN/A} 5212623SN/A 5225728Sgblack@eecs.umich.edubool 5235728Sgblack@eecs.umich.eduTimingSimpleCPU::handleWritePacket() 5245728Sgblack@eecs.umich.edu{ 5255728Sgblack@eecs.umich.edu RequestPtr req = dcache_pkt->req; 5265728Sgblack@eecs.umich.edu if (req->isMmapedIpr()) { 5275728Sgblack@eecs.umich.edu Tick delay; 5285728Sgblack@eecs.umich.edu delay = TheISA::handleIprWrite(thread->getTC(), dcache_pkt); 5295728Sgblack@eecs.umich.edu new IprEvent(dcache_pkt, this, nextCycle(curTick + delay)); 5305728Sgblack@eecs.umich.edu _status = DcacheWaitResponse; 5315728Sgblack@eecs.umich.edu dcache_pkt = NULL; 5325728Sgblack@eecs.umich.edu } else if (!dcachePort.sendTiming(dcache_pkt)) { 5335728Sgblack@eecs.umich.edu _status = DcacheRetry; 5345728Sgblack@eecs.umich.edu } else { 5355728Sgblack@eecs.umich.edu _status = DcacheWaitResponse; 5365728Sgblack@eecs.umich.edu // memory system takes ownership of packet 5375728Sgblack@eecs.umich.edu dcache_pkt = NULL; 5385728Sgblack@eecs.umich.edu } 5395728Sgblack@eecs.umich.edu return dcache_pkt == NULL; 5405728Sgblack@eecs.umich.edu} 5412623SN/A 5422623SN/AFault 5437520Sgblack@eecs.umich.eduTimingSimpleCPU::writeTheseBytes(uint8_t *data, unsigned size, 5447520Sgblack@eecs.umich.edu Addr addr, unsigned flags, uint64_t *res) 5452623SN/A{ 5465728Sgblack@eecs.umich.edu const int asid = 0; 5476221Snate@binkert.org const ThreadID tid = 0; 5487720Sgblack@eecs.umich.edu const Addr pc = thread->instAddr(); 5496227Snate@binkert.org unsigned block_size = dcachePort.peerBlockSize(); 5506973Stjones1@inf.ed.ac.uk BaseTLB::Mode mode = BaseTLB::Write; 5513169Sstever@eecs.umich.edu 5527045Ssteve.reinhardt@amd.com if (traceData) { 5537045Ssteve.reinhardt@amd.com traceData->setAddr(addr); 5547045Ssteve.reinhardt@amd.com } 5557045Ssteve.reinhardt@amd.com 5567520Sgblack@eecs.umich.edu RequestPtr req = new Request(asid, addr, size, 5576221Snate@binkert.org flags, pc, _cpuId, tid); 5585728Sgblack@eecs.umich.edu 5597520Sgblack@eecs.umich.edu Addr split_addr = roundDown(addr + size - 1, block_size); 5605744Sgblack@eecs.umich.edu assert(split_addr <= addr || split_addr - addr < block_size); 5615728Sgblack@eecs.umich.edu 5625894Sgblack@eecs.umich.edu _status = DTBWaitResponse; 5635744Sgblack@eecs.umich.edu if (split_addr > addr) { 5645894Sgblack@eecs.umich.edu RequestPtr req1, req2; 5656102Sgblack@eecs.umich.edu assert(!req->isLLSC() && !req->isSwap()); 5665894Sgblack@eecs.umich.edu req->splitOnVaddr(split_addr, req1, req2); 5675894Sgblack@eecs.umich.edu 5686973Stjones1@inf.ed.ac.uk WholeTranslationState *state = 5697520Sgblack@eecs.umich.edu new WholeTranslationState(req, req1, req2, data, res, mode); 5706973Stjones1@inf.ed.ac.uk DataTranslation<TimingSimpleCPU> *trans1 = 5716973Stjones1@inf.ed.ac.uk new DataTranslation<TimingSimpleCPU>(this, state, 0); 5726973Stjones1@inf.ed.ac.uk DataTranslation<TimingSimpleCPU> *trans2 = 5736973Stjones1@inf.ed.ac.uk new DataTranslation<TimingSimpleCPU>(this, state, 1); 5746973Stjones1@inf.ed.ac.uk 5756973Stjones1@inf.ed.ac.uk thread->dtb->translateTiming(req1, tc, trans1, mode); 5766973Stjones1@inf.ed.ac.uk thread->dtb->translateTiming(req2, tc, trans2, mode); 5775744Sgblack@eecs.umich.edu } else { 5786973Stjones1@inf.ed.ac.uk WholeTranslationState *state = 5797520Sgblack@eecs.umich.edu new WholeTranslationState(req, data, res, mode); 5806973Stjones1@inf.ed.ac.uk DataTranslation<TimingSimpleCPU> *translation = 5816973Stjones1@inf.ed.ac.uk new DataTranslation<TimingSimpleCPU>(this, state); 5826973Stjones1@inf.ed.ac.uk thread->dtb->translateTiming(req, tc, translation, mode); 5832623SN/A } 5842623SN/A 5857045Ssteve.reinhardt@amd.com // Translation faults will be returned via finishTranslation() 5865728Sgblack@eecs.umich.edu return NoFault; 5872623SN/A} 5882623SN/A 5897520Sgblack@eecs.umich.eduFault 5907520Sgblack@eecs.umich.eduTimingSimpleCPU::writeBytes(uint8_t *data, unsigned size, 5917520Sgblack@eecs.umich.edu Addr addr, unsigned flags, uint64_t *res) 5927520Sgblack@eecs.umich.edu{ 5937520Sgblack@eecs.umich.edu uint8_t *newData = new uint8_t[size]; 5947520Sgblack@eecs.umich.edu memcpy(newData, data, size); 5957520Sgblack@eecs.umich.edu return writeTheseBytes(newData, size, addr, flags, res); 5967520Sgblack@eecs.umich.edu} 5977520Sgblack@eecs.umich.edu 5987520Sgblack@eecs.umich.edutemplate <class T> 5997520Sgblack@eecs.umich.eduFault 6007520Sgblack@eecs.umich.eduTimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res) 6017520Sgblack@eecs.umich.edu{ 6027520Sgblack@eecs.umich.edu if (traceData) { 6037520Sgblack@eecs.umich.edu traceData->setData(data); 6047520Sgblack@eecs.umich.edu } 6057691SAli.Saidi@ARM.com T *dataP = (T*) new uint8_t[sizeof(T)]; 6067520Sgblack@eecs.umich.edu *dataP = TheISA::htog(data); 6077520Sgblack@eecs.umich.edu 6087520Sgblack@eecs.umich.edu return writeTheseBytes((uint8_t *)dataP, sizeof(T), addr, flags, res); 6097520Sgblack@eecs.umich.edu} 6107520Sgblack@eecs.umich.edu 6112623SN/A 6122623SN/A#ifndef DOXYGEN_SHOULD_SKIP_THIS 6132623SN/Atemplate 6142623SN/AFault 6154224Sgblack@eecs.umich.eduTimingSimpleCPU::write(Twin32_t data, Addr addr, 6164224Sgblack@eecs.umich.edu unsigned flags, uint64_t *res); 6174224Sgblack@eecs.umich.edu 6184224Sgblack@eecs.umich.edutemplate 6194224Sgblack@eecs.umich.eduFault 6204224Sgblack@eecs.umich.eduTimingSimpleCPU::write(Twin64_t data, Addr addr, 6214224Sgblack@eecs.umich.edu unsigned flags, uint64_t *res); 6224224Sgblack@eecs.umich.edu 6234224Sgblack@eecs.umich.edutemplate 6244224Sgblack@eecs.umich.eduFault 6252623SN/ATimingSimpleCPU::write(uint64_t data, Addr addr, 6262623SN/A unsigned flags, uint64_t *res); 6272623SN/A 6282623SN/Atemplate 6292623SN/AFault 6302623SN/ATimingSimpleCPU::write(uint32_t data, Addr addr, 6312623SN/A unsigned flags, uint64_t *res); 6322623SN/A 6332623SN/Atemplate 6342623SN/AFault 6352623SN/ATimingSimpleCPU::write(uint16_t data, Addr addr, 6362623SN/A unsigned flags, uint64_t *res); 6372623SN/A 6382623SN/Atemplate 6392623SN/AFault 6402623SN/ATimingSimpleCPU::write(uint8_t data, Addr addr, 6412623SN/A unsigned flags, uint64_t *res); 6422623SN/A 6432623SN/A#endif //DOXYGEN_SHOULD_SKIP_THIS 6442623SN/A 6452623SN/Atemplate<> 6462623SN/AFault 6472623SN/ATimingSimpleCPU::write(double data, Addr addr, unsigned flags, uint64_t *res) 6482623SN/A{ 6492623SN/A return write(*(uint64_t*)&data, addr, flags, res); 6502623SN/A} 6512623SN/A 6522623SN/Atemplate<> 6532623SN/AFault 6542623SN/ATimingSimpleCPU::write(float data, Addr addr, unsigned flags, uint64_t *res) 6552623SN/A{ 6562623SN/A return write(*(uint32_t*)&data, addr, flags, res); 6572623SN/A} 6582623SN/A 6592623SN/A 6602623SN/Atemplate<> 6612623SN/AFault 6622623SN/ATimingSimpleCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res) 6632623SN/A{ 6642623SN/A return write((uint32_t)data, addr, flags, res); 6652623SN/A} 6662623SN/A 6672623SN/A 6682623SN/Avoid 6696973Stjones1@inf.ed.ac.ukTimingSimpleCPU::finishTranslation(WholeTranslationState *state) 6706973Stjones1@inf.ed.ac.uk{ 6716973Stjones1@inf.ed.ac.uk _status = Running; 6726973Stjones1@inf.ed.ac.uk 6736973Stjones1@inf.ed.ac.uk if (state->getFault() != NoFault) { 6746973Stjones1@inf.ed.ac.uk if (state->isPrefetch()) { 6756973Stjones1@inf.ed.ac.uk state->setNoFault(); 6766973Stjones1@inf.ed.ac.uk } 6777691SAli.Saidi@ARM.com delete [] state->data; 6786973Stjones1@inf.ed.ac.uk state->deleteReqs(); 6796973Stjones1@inf.ed.ac.uk translationFault(state->getFault()); 6806973Stjones1@inf.ed.ac.uk } else { 6816973Stjones1@inf.ed.ac.uk if (!state->isSplit) { 6826973Stjones1@inf.ed.ac.uk sendData(state->mainReq, state->data, state->res, 6836973Stjones1@inf.ed.ac.uk state->mode == BaseTLB::Read); 6846973Stjones1@inf.ed.ac.uk } else { 6856973Stjones1@inf.ed.ac.uk sendSplitData(state->sreqLow, state->sreqHigh, state->mainReq, 6866973Stjones1@inf.ed.ac.uk state->data, state->mode == BaseTLB::Read); 6876973Stjones1@inf.ed.ac.uk } 6886973Stjones1@inf.ed.ac.uk } 6896973Stjones1@inf.ed.ac.uk 6906973Stjones1@inf.ed.ac.uk delete state; 6916973Stjones1@inf.ed.ac.uk} 6926973Stjones1@inf.ed.ac.uk 6936973Stjones1@inf.ed.ac.uk 6946973Stjones1@inf.ed.ac.ukvoid 6952623SN/ATimingSimpleCPU::fetch() 6962623SN/A{ 6975221Ssaidi@eecs.umich.edu DPRINTF(SimpleCPU, "Fetch\n"); 6985221Ssaidi@eecs.umich.edu 6993387Sgblack@eecs.umich.edu if (!curStaticInst || !curStaticInst->isDelayedCommit()) 7003387Sgblack@eecs.umich.edu checkForInterrupts(); 7012631SN/A 7025348Ssaidi@eecs.umich.edu checkPcEventQueue(); 7035348Ssaidi@eecs.umich.edu 7047720Sgblack@eecs.umich.edu TheISA::PCState pcState = thread->pcState(); 7057720Sgblack@eecs.umich.edu bool needToFetch = !isRomMicroPC(pcState.microPC()) && !curMacroStaticInst; 7062623SN/A 7077720Sgblack@eecs.umich.edu if (needToFetch) { 7085669Sgblack@eecs.umich.edu Request *ifetch_req = new Request(); 7095712Shsul@eecs.umich.edu ifetch_req->setThreadContext(_cpuId, /* thread ID */ 0); 7105894Sgblack@eecs.umich.edu setupFetchRequest(ifetch_req); 7116023Snate@binkert.org thread->itb->translateTiming(ifetch_req, tc, &fetchTranslation, 7126023Snate@binkert.org BaseTLB::Execute); 7132623SN/A } else { 7145669Sgblack@eecs.umich.edu _status = IcacheWaitResponse; 7155669Sgblack@eecs.umich.edu completeIfetch(NULL); 7165894Sgblack@eecs.umich.edu 7175894Sgblack@eecs.umich.edu numCycles += tickToCycles(curTick - previousTick); 7185894Sgblack@eecs.umich.edu previousTick = curTick; 7195894Sgblack@eecs.umich.edu } 7205894Sgblack@eecs.umich.edu} 7215894Sgblack@eecs.umich.edu 7225894Sgblack@eecs.umich.edu 7235894Sgblack@eecs.umich.eduvoid 7245894Sgblack@eecs.umich.eduTimingSimpleCPU::sendFetch(Fault fault, RequestPtr req, ThreadContext *tc) 7255894Sgblack@eecs.umich.edu{ 7265894Sgblack@eecs.umich.edu if (fault == NoFault) { 7275894Sgblack@eecs.umich.edu ifetch_pkt = new Packet(req, MemCmd::ReadReq, Packet::Broadcast); 7285894Sgblack@eecs.umich.edu ifetch_pkt->dataStatic(&inst); 7295894Sgblack@eecs.umich.edu 7305894Sgblack@eecs.umich.edu if (!icachePort.sendTiming(ifetch_pkt)) { 7315894Sgblack@eecs.umich.edu // Need to wait for retry 7325894Sgblack@eecs.umich.edu _status = IcacheRetry; 7335894Sgblack@eecs.umich.edu } else { 7345894Sgblack@eecs.umich.edu // Need to wait for cache to respond 7355894Sgblack@eecs.umich.edu _status = IcacheWaitResponse; 7365894Sgblack@eecs.umich.edu // ownership of packet transferred to memory system 7375894Sgblack@eecs.umich.edu ifetch_pkt = NULL; 7385894Sgblack@eecs.umich.edu } 7395894Sgblack@eecs.umich.edu } else { 7405894Sgblack@eecs.umich.edu delete req; 7415894Sgblack@eecs.umich.edu // fetch fault: advance directly to next instruction (fault handler) 7425894Sgblack@eecs.umich.edu advanceInst(fault); 7432623SN/A } 7443222Sktlim@umich.edu 7455099Ssaidi@eecs.umich.edu numCycles += tickToCycles(curTick - previousTick); 7463222Sktlim@umich.edu previousTick = curTick; 7472623SN/A} 7482623SN/A 7492623SN/A 7502623SN/Avoid 7512644Sstever@eecs.umich.eduTimingSimpleCPU::advanceInst(Fault fault) 7522623SN/A{ 7535726Sgblack@eecs.umich.edu if (fault != NoFault || !stayAtPC) 7545726Sgblack@eecs.umich.edu advancePC(fault); 7552623SN/A 7562631SN/A if (_status == Running) { 7572631SN/A // kick off fetch of next instruction... callback from icache 7582631SN/A // response will cause that instruction to be executed, 7592631SN/A // keeping the CPU running. 7602631SN/A fetch(); 7612631SN/A } 7622623SN/A} 7632623SN/A 7642623SN/A 7652623SN/Avoid 7663349Sbinkertn@umich.eduTimingSimpleCPU::completeIfetch(PacketPtr pkt) 7672623SN/A{ 7685221Ssaidi@eecs.umich.edu DPRINTF(SimpleCPU, "Complete ICache Fetch\n"); 7695221Ssaidi@eecs.umich.edu 7702623SN/A // received a response from the icache: execute the received 7712623SN/A // instruction 7725669Sgblack@eecs.umich.edu 7735669Sgblack@eecs.umich.edu assert(!pkt || !pkt->isError()); 7742623SN/A assert(_status == IcacheWaitResponse); 7752798Sktlim@umich.edu 7762623SN/A _status = Running; 7772644Sstever@eecs.umich.edu 7785099Ssaidi@eecs.umich.edu numCycles += tickToCycles(curTick - previousTick); 7793222Sktlim@umich.edu previousTick = curTick; 7803222Sktlim@umich.edu 7812839Sktlim@umich.edu if (getState() == SimObject::Draining) { 7825669Sgblack@eecs.umich.edu if (pkt) { 7835669Sgblack@eecs.umich.edu delete pkt->req; 7845669Sgblack@eecs.umich.edu delete pkt; 7855669Sgblack@eecs.umich.edu } 7863658Sktlim@umich.edu 7872839Sktlim@umich.edu completeDrain(); 7882798Sktlim@umich.edu return; 7892798Sktlim@umich.edu } 7902798Sktlim@umich.edu 7912623SN/A preExecute(); 7925726Sgblack@eecs.umich.edu if (curStaticInst && 7935726Sgblack@eecs.umich.edu curStaticInst->isMemRef() && !curStaticInst->isDataPrefetch()) { 7942623SN/A // load or store: just send to dcache 7952623SN/A Fault fault = curStaticInst->initiateAcc(this, traceData); 7963170Sstever@eecs.umich.edu if (_status != Running) { 7973170Sstever@eecs.umich.edu // instruction will complete in dcache response callback 7985894Sgblack@eecs.umich.edu assert(_status == DcacheWaitResponse || 7995894Sgblack@eecs.umich.edu _status == DcacheRetry || DTBWaitResponse); 8003170Sstever@eecs.umich.edu assert(fault == NoFault); 8012644Sstever@eecs.umich.edu } else { 8025894Sgblack@eecs.umich.edu if (fault != NoFault && traceData) { 8035001Sgblack@eecs.umich.edu // If there was a fault, we shouldn't trace this instruction. 8045001Sgblack@eecs.umich.edu delete traceData; 8055001Sgblack@eecs.umich.edu traceData = NULL; 8063170Sstever@eecs.umich.edu } 8074998Sgblack@eecs.umich.edu 8082644Sstever@eecs.umich.edu postExecute(); 8095103Ssaidi@eecs.umich.edu // @todo remove me after debugging with legion done 8105103Ssaidi@eecs.umich.edu if (curStaticInst && (!curStaticInst->isMicroop() || 8115103Ssaidi@eecs.umich.edu curStaticInst->isFirstMicroop())) 8125103Ssaidi@eecs.umich.edu instCnt++; 8132644Sstever@eecs.umich.edu advanceInst(fault); 8142644Sstever@eecs.umich.edu } 8155726Sgblack@eecs.umich.edu } else if (curStaticInst) { 8162623SN/A // non-memory instruction: execute completely now 8172623SN/A Fault fault = curStaticInst->execute(this, traceData); 8184998Sgblack@eecs.umich.edu 8194998Sgblack@eecs.umich.edu // keep an instruction count 8204998Sgblack@eecs.umich.edu if (fault == NoFault) 8214998Sgblack@eecs.umich.edu countInst(); 8227655Sali.saidi@arm.com else if (traceData && !DTRACE(ExecFaulting)) { 8235001Sgblack@eecs.umich.edu delete traceData; 8245001Sgblack@eecs.umich.edu traceData = NULL; 8255001Sgblack@eecs.umich.edu } 8264998Sgblack@eecs.umich.edu 8272644Sstever@eecs.umich.edu postExecute(); 8285103Ssaidi@eecs.umich.edu // @todo remove me after debugging with legion done 8295103Ssaidi@eecs.umich.edu if (curStaticInst && (!curStaticInst->isMicroop() || 8305103Ssaidi@eecs.umich.edu curStaticInst->isFirstMicroop())) 8315103Ssaidi@eecs.umich.edu instCnt++; 8322644Sstever@eecs.umich.edu advanceInst(fault); 8335726Sgblack@eecs.umich.edu } else { 8345726Sgblack@eecs.umich.edu advanceInst(NoFault); 8352623SN/A } 8363658Sktlim@umich.edu 8375669Sgblack@eecs.umich.edu if (pkt) { 8385669Sgblack@eecs.umich.edu delete pkt->req; 8395669Sgblack@eecs.umich.edu delete pkt; 8405669Sgblack@eecs.umich.edu } 8412623SN/A} 8422623SN/A 8432948Ssaidi@eecs.umich.eduvoid 8442948Ssaidi@eecs.umich.eduTimingSimpleCPU::IcachePort::ITickEvent::process() 8452948Ssaidi@eecs.umich.edu{ 8462948Ssaidi@eecs.umich.edu cpu->completeIfetch(pkt); 8472948Ssaidi@eecs.umich.edu} 8482623SN/A 8492623SN/Abool 8503349Sbinkertn@umich.eduTimingSimpleCPU::IcachePort::recvTiming(PacketPtr pkt) 8512623SN/A{ 8524986Ssaidi@eecs.umich.edu if (pkt->isResponse() && !pkt->wasNacked()) { 8533310Srdreslin@umich.edu // delay processing of returned data until next CPU clock edge 8544584Ssaidi@eecs.umich.edu Tick next_tick = cpu->nextCycle(curTick); 8552948Ssaidi@eecs.umich.edu 8563495Sktlim@umich.edu if (next_tick == curTick) 8573310Srdreslin@umich.edu cpu->completeIfetch(pkt); 8583310Srdreslin@umich.edu else 8593495Sktlim@umich.edu tickEvent.schedule(pkt, next_tick); 8602948Ssaidi@eecs.umich.edu 8613310Srdreslin@umich.edu return true; 8623310Srdreslin@umich.edu } 8634870Sstever@eecs.umich.edu else if (pkt->wasNacked()) { 8644433Ssaidi@eecs.umich.edu assert(cpu->_status == IcacheWaitResponse); 8654433Ssaidi@eecs.umich.edu pkt->reinitNacked(); 8664433Ssaidi@eecs.umich.edu if (!sendTiming(pkt)) { 8674433Ssaidi@eecs.umich.edu cpu->_status = IcacheRetry; 8684433Ssaidi@eecs.umich.edu cpu->ifetch_pkt = pkt; 8694433Ssaidi@eecs.umich.edu } 8703310Srdreslin@umich.edu } 8714433Ssaidi@eecs.umich.edu //Snooping a Coherence Request, do nothing 8724433Ssaidi@eecs.umich.edu return true; 8732623SN/A} 8742623SN/A 8752657Ssaidi@eecs.umich.eduvoid 8762623SN/ATimingSimpleCPU::IcachePort::recvRetry() 8772623SN/A{ 8782623SN/A // we shouldn't get a retry unless we have a packet that we're 8792623SN/A // waiting to transmit 8802623SN/A assert(cpu->ifetch_pkt != NULL); 8812623SN/A assert(cpu->_status == IcacheRetry); 8823349Sbinkertn@umich.edu PacketPtr tmp = cpu->ifetch_pkt; 8832657Ssaidi@eecs.umich.edu if (sendTiming(tmp)) { 8842657Ssaidi@eecs.umich.edu cpu->_status = IcacheWaitResponse; 8852657Ssaidi@eecs.umich.edu cpu->ifetch_pkt = NULL; 8862657Ssaidi@eecs.umich.edu } 8872623SN/A} 8882623SN/A 8892623SN/Avoid 8903349Sbinkertn@umich.eduTimingSimpleCPU::completeDataAccess(PacketPtr pkt) 8912623SN/A{ 8922623SN/A // received a response from the dcache: complete the load or store 8932623SN/A // instruction 8944870Sstever@eecs.umich.edu assert(!pkt->isError()); 8957516Shestness@cs.utexas.edu assert(_status == DcacheWaitResponse || _status == DTBWaitResponse || 8967516Shestness@cs.utexas.edu pkt->req->getFlags().isSet(Request::NO_ACCESS)); 8972623SN/A 8985099Ssaidi@eecs.umich.edu numCycles += tickToCycles(curTick - previousTick); 8993222Sktlim@umich.edu previousTick = curTick; 9003184Srdreslin@umich.edu 9015728Sgblack@eecs.umich.edu if (pkt->senderState) { 9025728Sgblack@eecs.umich.edu SplitFragmentSenderState * send_state = 9035728Sgblack@eecs.umich.edu dynamic_cast<SplitFragmentSenderState *>(pkt->senderState); 9045728Sgblack@eecs.umich.edu assert(send_state); 9055728Sgblack@eecs.umich.edu delete pkt->req; 9065728Sgblack@eecs.umich.edu delete pkt; 9075728Sgblack@eecs.umich.edu PacketPtr big_pkt = send_state->bigPkt; 9085728Sgblack@eecs.umich.edu delete send_state; 9095728Sgblack@eecs.umich.edu 9105728Sgblack@eecs.umich.edu SplitMainSenderState * main_send_state = 9115728Sgblack@eecs.umich.edu dynamic_cast<SplitMainSenderState *>(big_pkt->senderState); 9125728Sgblack@eecs.umich.edu assert(main_send_state); 9135728Sgblack@eecs.umich.edu // Record the fact that this packet is no longer outstanding. 9145728Sgblack@eecs.umich.edu assert(main_send_state->outstanding != 0); 9155728Sgblack@eecs.umich.edu main_send_state->outstanding--; 9165728Sgblack@eecs.umich.edu 9175728Sgblack@eecs.umich.edu if (main_send_state->outstanding) { 9185728Sgblack@eecs.umich.edu return; 9195728Sgblack@eecs.umich.edu } else { 9205728Sgblack@eecs.umich.edu delete main_send_state; 9215728Sgblack@eecs.umich.edu big_pkt->senderState = NULL; 9225728Sgblack@eecs.umich.edu pkt = big_pkt; 9235728Sgblack@eecs.umich.edu } 9245728Sgblack@eecs.umich.edu } 9255728Sgblack@eecs.umich.edu 9265728Sgblack@eecs.umich.edu _status = Running; 9275728Sgblack@eecs.umich.edu 9282623SN/A Fault fault = curStaticInst->completeAcc(pkt, this, traceData); 9292623SN/A 9304998Sgblack@eecs.umich.edu // keep an instruction count 9314998Sgblack@eecs.umich.edu if (fault == NoFault) 9324998Sgblack@eecs.umich.edu countInst(); 9335001Sgblack@eecs.umich.edu else if (traceData) { 9345001Sgblack@eecs.umich.edu // If there was a fault, we shouldn't trace this instruction. 9355001Sgblack@eecs.umich.edu delete traceData; 9365001Sgblack@eecs.umich.edu traceData = NULL; 9375001Sgblack@eecs.umich.edu } 9384998Sgblack@eecs.umich.edu 9395507Sstever@gmail.com // the locked flag may be cleared on the response packet, so check 9405507Sstever@gmail.com // pkt->req and not pkt to see if it was a load-locked 9416102Sgblack@eecs.umich.edu if (pkt->isRead() && pkt->req->isLLSC()) { 9423170Sstever@eecs.umich.edu TheISA::handleLockedRead(thread, pkt->req); 9433170Sstever@eecs.umich.edu } 9443170Sstever@eecs.umich.edu 9452644Sstever@eecs.umich.edu delete pkt->req; 9462644Sstever@eecs.umich.edu delete pkt; 9472644Sstever@eecs.umich.edu 9483184Srdreslin@umich.edu postExecute(); 9493227Sktlim@umich.edu 9503201Shsul@eecs.umich.edu if (getState() == SimObject::Draining) { 9513201Shsul@eecs.umich.edu advancePC(fault); 9523201Shsul@eecs.umich.edu completeDrain(); 9533201Shsul@eecs.umich.edu 9543201Shsul@eecs.umich.edu return; 9553201Shsul@eecs.umich.edu } 9563201Shsul@eecs.umich.edu 9572644Sstever@eecs.umich.edu advanceInst(fault); 9582623SN/A} 9592623SN/A 9602623SN/A 9612798Sktlim@umich.eduvoid 9622839Sktlim@umich.eduTimingSimpleCPU::completeDrain() 9632798Sktlim@umich.edu{ 9642839Sktlim@umich.edu DPRINTF(Config, "Done draining\n"); 9652901Ssaidi@eecs.umich.edu changeState(SimObject::Drained); 9662839Sktlim@umich.edu drainEvent->process(); 9672798Sktlim@umich.edu} 9682623SN/A 9694192Sktlim@umich.eduvoid 9704192Sktlim@umich.eduTimingSimpleCPU::DcachePort::setPeer(Port *port) 9714192Sktlim@umich.edu{ 9724192Sktlim@umich.edu Port::setPeer(port); 9734192Sktlim@umich.edu 9744192Sktlim@umich.edu#if FULL_SYSTEM 9754192Sktlim@umich.edu // Update the ThreadContext's memory ports (Functional/Virtual 9764192Sktlim@umich.edu // Ports) 9775497Ssaidi@eecs.umich.edu cpu->tcBase()->connectMemPorts(cpu->tcBase()); 9784192Sktlim@umich.edu#endif 9794192Sktlim@umich.edu} 9804192Sktlim@umich.edu 9812623SN/Abool 9823349Sbinkertn@umich.eduTimingSimpleCPU::DcachePort::recvTiming(PacketPtr pkt) 9832623SN/A{ 9844986Ssaidi@eecs.umich.edu if (pkt->isResponse() && !pkt->wasNacked()) { 9853310Srdreslin@umich.edu // delay processing of returned data until next CPU clock edge 9864584Ssaidi@eecs.umich.edu Tick next_tick = cpu->nextCycle(curTick); 9872948Ssaidi@eecs.umich.edu 9885728Sgblack@eecs.umich.edu if (next_tick == curTick) { 9893310Srdreslin@umich.edu cpu->completeDataAccess(pkt); 9905728Sgblack@eecs.umich.edu } else { 9913495Sktlim@umich.edu tickEvent.schedule(pkt, next_tick); 9925728Sgblack@eecs.umich.edu } 9932948Ssaidi@eecs.umich.edu 9943310Srdreslin@umich.edu return true; 9953310Srdreslin@umich.edu } 9964870Sstever@eecs.umich.edu else if (pkt->wasNacked()) { 9974433Ssaidi@eecs.umich.edu assert(cpu->_status == DcacheWaitResponse); 9984433Ssaidi@eecs.umich.edu pkt->reinitNacked(); 9994433Ssaidi@eecs.umich.edu if (!sendTiming(pkt)) { 10004433Ssaidi@eecs.umich.edu cpu->_status = DcacheRetry; 10014433Ssaidi@eecs.umich.edu cpu->dcache_pkt = pkt; 10024433Ssaidi@eecs.umich.edu } 10033310Srdreslin@umich.edu } 10044433Ssaidi@eecs.umich.edu //Snooping a Coherence Request, do nothing 10054433Ssaidi@eecs.umich.edu return true; 10062948Ssaidi@eecs.umich.edu} 10072948Ssaidi@eecs.umich.edu 10082948Ssaidi@eecs.umich.eduvoid 10092948Ssaidi@eecs.umich.eduTimingSimpleCPU::DcachePort::DTickEvent::process() 10102948Ssaidi@eecs.umich.edu{ 10112630SN/A cpu->completeDataAccess(pkt); 10122623SN/A} 10132623SN/A 10142657Ssaidi@eecs.umich.eduvoid 10152623SN/ATimingSimpleCPU::DcachePort::recvRetry() 10162623SN/A{ 10172623SN/A // we shouldn't get a retry unless we have a packet that we're 10182623SN/A // waiting to transmit 10192623SN/A assert(cpu->dcache_pkt != NULL); 10202623SN/A assert(cpu->_status == DcacheRetry); 10213349Sbinkertn@umich.edu PacketPtr tmp = cpu->dcache_pkt; 10225728Sgblack@eecs.umich.edu if (tmp->senderState) { 10235728Sgblack@eecs.umich.edu // This is a packet from a split access. 10245728Sgblack@eecs.umich.edu SplitFragmentSenderState * send_state = 10255728Sgblack@eecs.umich.edu dynamic_cast<SplitFragmentSenderState *>(tmp->senderState); 10265728Sgblack@eecs.umich.edu assert(send_state); 10275728Sgblack@eecs.umich.edu PacketPtr big_pkt = send_state->bigPkt; 10285728Sgblack@eecs.umich.edu 10295728Sgblack@eecs.umich.edu SplitMainSenderState * main_send_state = 10305728Sgblack@eecs.umich.edu dynamic_cast<SplitMainSenderState *>(big_pkt->senderState); 10315728Sgblack@eecs.umich.edu assert(main_send_state); 10325728Sgblack@eecs.umich.edu 10335728Sgblack@eecs.umich.edu if (sendTiming(tmp)) { 10345728Sgblack@eecs.umich.edu // If we were able to send without retrying, record that fact 10355728Sgblack@eecs.umich.edu // and try sending the other fragment. 10365728Sgblack@eecs.umich.edu send_state->clearFromParent(); 10375728Sgblack@eecs.umich.edu int other_index = main_send_state->getPendingFragment(); 10385728Sgblack@eecs.umich.edu if (other_index > 0) { 10395728Sgblack@eecs.umich.edu tmp = main_send_state->fragments[other_index]; 10405728Sgblack@eecs.umich.edu cpu->dcache_pkt = tmp; 10415728Sgblack@eecs.umich.edu if ((big_pkt->isRead() && cpu->handleReadPacket(tmp)) || 10425728Sgblack@eecs.umich.edu (big_pkt->isWrite() && cpu->handleWritePacket())) { 10435728Sgblack@eecs.umich.edu main_send_state->fragments[other_index] = NULL; 10445728Sgblack@eecs.umich.edu } 10455728Sgblack@eecs.umich.edu } else { 10465728Sgblack@eecs.umich.edu cpu->_status = DcacheWaitResponse; 10475728Sgblack@eecs.umich.edu // memory system takes ownership of packet 10485728Sgblack@eecs.umich.edu cpu->dcache_pkt = NULL; 10495728Sgblack@eecs.umich.edu } 10505728Sgblack@eecs.umich.edu } 10515728Sgblack@eecs.umich.edu } else if (sendTiming(tmp)) { 10522657Ssaidi@eecs.umich.edu cpu->_status = DcacheWaitResponse; 10533170Sstever@eecs.umich.edu // memory system takes ownership of packet 10542657Ssaidi@eecs.umich.edu cpu->dcache_pkt = NULL; 10552657Ssaidi@eecs.umich.edu } 10562623SN/A} 10572623SN/A 10585606Snate@binkert.orgTimingSimpleCPU::IprEvent::IprEvent(Packet *_pkt, TimingSimpleCPU *_cpu, 10595606Snate@binkert.org Tick t) 10605606Snate@binkert.org : pkt(_pkt), cpu(_cpu) 10615103Ssaidi@eecs.umich.edu{ 10625606Snate@binkert.org cpu->schedule(this, t); 10635103Ssaidi@eecs.umich.edu} 10645103Ssaidi@eecs.umich.edu 10655103Ssaidi@eecs.umich.eduvoid 10665103Ssaidi@eecs.umich.eduTimingSimpleCPU::IprEvent::process() 10675103Ssaidi@eecs.umich.edu{ 10685103Ssaidi@eecs.umich.edu cpu->completeDataAccess(pkt); 10695103Ssaidi@eecs.umich.edu} 10705103Ssaidi@eecs.umich.edu 10715103Ssaidi@eecs.umich.educonst char * 10725336Shines@cs.fsu.eduTimingSimpleCPU::IprEvent::description() const 10735103Ssaidi@eecs.umich.edu{ 10745103Ssaidi@eecs.umich.edu return "Timing Simple CPU Delay IPR event"; 10755103Ssaidi@eecs.umich.edu} 10765103Ssaidi@eecs.umich.edu 10772623SN/A 10785315Sstever@gmail.comvoid 10795315Sstever@gmail.comTimingSimpleCPU::printAddr(Addr a) 10805315Sstever@gmail.com{ 10815315Sstever@gmail.com dcachePort.printAddr(a); 10825315Sstever@gmail.com} 10835315Sstever@gmail.com 10845315Sstever@gmail.com 10852623SN/A//////////////////////////////////////////////////////////////////////// 10862623SN/A// 10872623SN/A// TimingSimpleCPU Simulation Object 10882623SN/A// 10894762Snate@binkert.orgTimingSimpleCPU * 10904762Snate@binkert.orgTimingSimpleCPUParams::create() 10912623SN/A{ 10925529Snate@binkert.org numThreads = 1; 10935529Snate@binkert.org#if !FULL_SYSTEM 10944762Snate@binkert.org if (workload.size() != 1) 10954762Snate@binkert.org panic("only one workload allowed"); 10962623SN/A#endif 10975529Snate@binkert.org return new TimingSimpleCPU(this); 10982623SN/A} 1099