timing.cc revision 7045
12623SN/A/* 22623SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 32623SN/A * All rights reserved. 42623SN/A * 52623SN/A * Redistribution and use in source and binary forms, with or without 62623SN/A * modification, are permitted provided that the following conditions are 72623SN/A * met: redistributions of source code must retain the above copyright 82623SN/A * notice, this list of conditions and the following disclaimer; 92623SN/A * redistributions in binary form must reproduce the above copyright 102623SN/A * notice, this list of conditions and the following disclaimer in the 112623SN/A * documentation and/or other materials provided with the distribution; 122623SN/A * neither the name of the copyright holders nor the names of its 132623SN/A * contributors may be used to endorse or promote products derived from 142623SN/A * this software without specific prior written permission. 152623SN/A * 162623SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172623SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182623SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192623SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202623SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212623SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222623SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232623SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242623SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252623SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262623SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 292623SN/A */ 302623SN/A 313170Sstever@eecs.umich.edu#include "arch/locked_mem.hh" 325103Ssaidi@eecs.umich.edu#include "arch/mmaped_ipr.hh" 332623SN/A#include "arch/utility.hh" 344040Ssaidi@eecs.umich.edu#include "base/bigint.hh" 356658Snate@binkert.org#include "config/the_isa.hh" 362623SN/A#include "cpu/exetrace.hh" 372623SN/A#include "cpu/simple/timing.hh" 383348Sbinkertn@umich.edu#include "mem/packet.hh" 393348Sbinkertn@umich.edu#include "mem/packet_access.hh" 404762Snate@binkert.org#include "params/TimingSimpleCPU.hh" 412901Ssaidi@eecs.umich.edu#include "sim/system.hh" 422623SN/A 432623SN/Ausing namespace std; 442623SN/Ausing namespace TheISA; 452623SN/A 462856Srdreslin@umich.eduPort * 472856Srdreslin@umich.eduTimingSimpleCPU::getPort(const std::string &if_name, int idx) 482856Srdreslin@umich.edu{ 492856Srdreslin@umich.edu if (if_name == "dcache_port") 502856Srdreslin@umich.edu return &dcachePort; 512856Srdreslin@umich.edu else if (if_name == "icache_port") 522856Srdreslin@umich.edu return &icachePort; 532856Srdreslin@umich.edu else 542856Srdreslin@umich.edu panic("No Such Port\n"); 552856Srdreslin@umich.edu} 562623SN/A 572623SN/Avoid 582623SN/ATimingSimpleCPU::init() 592623SN/A{ 602623SN/A BaseCPU::init(); 612623SN/A#if FULL_SYSTEM 622680Sktlim@umich.edu for (int i = 0; i < threadContexts.size(); ++i) { 632680Sktlim@umich.edu ThreadContext *tc = threadContexts[i]; 642623SN/A 652623SN/A // initialize CPU, including PC 665712Shsul@eecs.umich.edu TheISA::initCPU(tc, _cpuId); 672623SN/A } 682623SN/A#endif 692623SN/A} 702623SN/A 712623SN/ATick 723349Sbinkertn@umich.eduTimingSimpleCPU::CpuPort::recvAtomic(PacketPtr pkt) 732623SN/A{ 742623SN/A panic("TimingSimpleCPU doesn't expect recvAtomic callback!"); 752623SN/A return curTick; 762623SN/A} 772623SN/A 782623SN/Avoid 793349Sbinkertn@umich.eduTimingSimpleCPU::CpuPort::recvFunctional(PacketPtr pkt) 802623SN/A{ 813184Srdreslin@umich.edu //No internal storage to update, jusst return 823184Srdreslin@umich.edu return; 832623SN/A} 842623SN/A 852623SN/Avoid 862623SN/ATimingSimpleCPU::CpuPort::recvStatusChange(Status status) 872623SN/A{ 883647Srdreslin@umich.edu if (status == RangeChange) { 893647Srdreslin@umich.edu if (!snoopRangeSent) { 903647Srdreslin@umich.edu snoopRangeSent = true; 913647Srdreslin@umich.edu sendStatusChange(Port::RangeChange); 923647Srdreslin@umich.edu } 932631SN/A return; 943647Srdreslin@umich.edu } 952631SN/A 962623SN/A panic("TimingSimpleCPU doesn't expect recvStatusChange callback!"); 972623SN/A} 982623SN/A 992948Ssaidi@eecs.umich.edu 1002948Ssaidi@eecs.umich.eduvoid 1013349Sbinkertn@umich.eduTimingSimpleCPU::CpuPort::TickEvent::schedule(PacketPtr _pkt, Tick t) 1022948Ssaidi@eecs.umich.edu{ 1032948Ssaidi@eecs.umich.edu pkt = _pkt; 1045606Snate@binkert.org cpu->schedule(this, t); 1052948Ssaidi@eecs.umich.edu} 1062948Ssaidi@eecs.umich.edu 1075529Snate@binkert.orgTimingSimpleCPU::TimingSimpleCPU(TimingSimpleCPUParams *p) 1085894Sgblack@eecs.umich.edu : BaseSimpleCPU(p), fetchTranslation(this), icachePort(this, p->clock), 1095894Sgblack@eecs.umich.edu dcachePort(this, p->clock), fetchEvent(this) 1102623SN/A{ 1112623SN/A _status = Idle; 1123647Srdreslin@umich.edu 1133647Srdreslin@umich.edu icachePort.snoopRangeSent = false; 1143647Srdreslin@umich.edu dcachePort.snoopRangeSent = false; 1153647Srdreslin@umich.edu 1162623SN/A ifetch_pkt = dcache_pkt = NULL; 1172839Sktlim@umich.edu drainEvent = NULL; 1183222Sktlim@umich.edu previousTick = 0; 1192901Ssaidi@eecs.umich.edu changeState(SimObject::Running); 1202623SN/A} 1212623SN/A 1222623SN/A 1232623SN/ATimingSimpleCPU::~TimingSimpleCPU() 1242623SN/A{ 1252623SN/A} 1262623SN/A 1272623SN/Avoid 1282623SN/ATimingSimpleCPU::serialize(ostream &os) 1292623SN/A{ 1302915Sktlim@umich.edu SimObject::State so_state = SimObject::getState(); 1312915Sktlim@umich.edu SERIALIZE_ENUM(so_state); 1322623SN/A BaseSimpleCPU::serialize(os); 1332623SN/A} 1342623SN/A 1352623SN/Avoid 1362623SN/ATimingSimpleCPU::unserialize(Checkpoint *cp, const string §ion) 1372623SN/A{ 1382915Sktlim@umich.edu SimObject::State so_state; 1392915Sktlim@umich.edu UNSERIALIZE_ENUM(so_state); 1402623SN/A BaseSimpleCPU::unserialize(cp, section); 1412798Sktlim@umich.edu} 1422798Sktlim@umich.edu 1432901Ssaidi@eecs.umich.eduunsigned int 1442839Sktlim@umich.eduTimingSimpleCPU::drain(Event *drain_event) 1452798Sktlim@umich.edu{ 1462839Sktlim@umich.edu // TimingSimpleCPU is ready to drain if it's not waiting for 1472798Sktlim@umich.edu // an access to complete. 1485496Ssaidi@eecs.umich.edu if (_status == Idle || _status == Running || _status == SwitchedOut) { 1492901Ssaidi@eecs.umich.edu changeState(SimObject::Drained); 1502901Ssaidi@eecs.umich.edu return 0; 1512798Sktlim@umich.edu } else { 1522839Sktlim@umich.edu changeState(SimObject::Draining); 1532839Sktlim@umich.edu drainEvent = drain_event; 1542901Ssaidi@eecs.umich.edu return 1; 1552798Sktlim@umich.edu } 1562623SN/A} 1572623SN/A 1582623SN/Avoid 1592798Sktlim@umich.eduTimingSimpleCPU::resume() 1602623SN/A{ 1615221Ssaidi@eecs.umich.edu DPRINTF(SimpleCPU, "Resume\n"); 1622798Sktlim@umich.edu if (_status != SwitchedOut && _status != Idle) { 1634762Snate@binkert.org assert(system->getMemoryMode() == Enums::timing); 1643201Shsul@eecs.umich.edu 1655710Scws3k@cs.virginia.edu if (fetchEvent.scheduled()) 1665710Scws3k@cs.virginia.edu deschedule(fetchEvent); 1672915Sktlim@umich.edu 1685710Scws3k@cs.virginia.edu schedule(fetchEvent, nextCycle()); 1692623SN/A } 1702798Sktlim@umich.edu 1712901Ssaidi@eecs.umich.edu changeState(SimObject::Running); 1722798Sktlim@umich.edu} 1732798Sktlim@umich.edu 1742798Sktlim@umich.eduvoid 1752798Sktlim@umich.eduTimingSimpleCPU::switchOut() 1762798Sktlim@umich.edu{ 1775496Ssaidi@eecs.umich.edu assert(_status == Running || _status == Idle); 1782798Sktlim@umich.edu _status = SwitchedOut; 1795099Ssaidi@eecs.umich.edu numCycles += tickToCycles(curTick - previousTick); 1802867Sktlim@umich.edu 1812867Sktlim@umich.edu // If we've been scheduled to resume but are then told to switch out, 1822867Sktlim@umich.edu // we'll need to cancel it. 1835710Scws3k@cs.virginia.edu if (fetchEvent.scheduled()) 1845606Snate@binkert.org deschedule(fetchEvent); 1852623SN/A} 1862623SN/A 1872623SN/A 1882623SN/Avoid 1892623SN/ATimingSimpleCPU::takeOverFrom(BaseCPU *oldCPU) 1902623SN/A{ 1914192Sktlim@umich.edu BaseCPU::takeOverFrom(oldCPU, &icachePort, &dcachePort); 1922623SN/A 1932680Sktlim@umich.edu // if any of this CPU's ThreadContexts are active, mark the CPU as 1942623SN/A // running and schedule its tick event. 1952680Sktlim@umich.edu for (int i = 0; i < threadContexts.size(); ++i) { 1962680Sktlim@umich.edu ThreadContext *tc = threadContexts[i]; 1972680Sktlim@umich.edu if (tc->status() == ThreadContext::Active && _status != Running) { 1982623SN/A _status = Running; 1992623SN/A break; 2002623SN/A } 2012623SN/A } 2023201Shsul@eecs.umich.edu 2033201Shsul@eecs.umich.edu if (_status != Running) { 2043201Shsul@eecs.umich.edu _status = Idle; 2053201Shsul@eecs.umich.edu } 2065169Ssaidi@eecs.umich.edu assert(threadContexts.size() == 1); 2075101Ssaidi@eecs.umich.edu previousTick = curTick; 2082623SN/A} 2092623SN/A 2102623SN/A 2112623SN/Avoid 2122623SN/ATimingSimpleCPU::activateContext(int thread_num, int delay) 2132623SN/A{ 2145221Ssaidi@eecs.umich.edu DPRINTF(SimpleCPU, "ActivateContext %d (%d cycles)\n", thread_num, delay); 2155221Ssaidi@eecs.umich.edu 2162623SN/A assert(thread_num == 0); 2172683Sktlim@umich.edu assert(thread); 2182623SN/A 2192623SN/A assert(_status == Idle); 2202623SN/A 2212623SN/A notIdleFraction++; 2222623SN/A _status = Running; 2233686Sktlim@umich.edu 2242623SN/A // kick things off by initiating the fetch of the next instruction 2255606Snate@binkert.org schedule(fetchEvent, nextCycle(curTick + ticks(delay))); 2262623SN/A} 2272623SN/A 2282623SN/A 2292623SN/Avoid 2302623SN/ATimingSimpleCPU::suspendContext(int thread_num) 2312623SN/A{ 2325221Ssaidi@eecs.umich.edu DPRINTF(SimpleCPU, "SuspendContext %d\n", thread_num); 2335221Ssaidi@eecs.umich.edu 2342623SN/A assert(thread_num == 0); 2352683Sktlim@umich.edu assert(thread); 2362623SN/A 2376043Sgblack@eecs.umich.edu if (_status == Idle) 2386043Sgblack@eecs.umich.edu return; 2396043Sgblack@eecs.umich.edu 2402644Sstever@eecs.umich.edu assert(_status == Running); 2412623SN/A 2422644Sstever@eecs.umich.edu // just change status to Idle... if status != Running, 2432644Sstever@eecs.umich.edu // completeInst() will not initiate fetch of next instruction. 2442623SN/A 2452623SN/A notIdleFraction--; 2462623SN/A _status = Idle; 2472623SN/A} 2482623SN/A 2495728Sgblack@eecs.umich.edubool 2505728Sgblack@eecs.umich.eduTimingSimpleCPU::handleReadPacket(PacketPtr pkt) 2515728Sgblack@eecs.umich.edu{ 2525728Sgblack@eecs.umich.edu RequestPtr req = pkt->req; 2535728Sgblack@eecs.umich.edu if (req->isMmapedIpr()) { 2545728Sgblack@eecs.umich.edu Tick delay; 2555728Sgblack@eecs.umich.edu delay = TheISA::handleIprRead(thread->getTC(), pkt); 2565728Sgblack@eecs.umich.edu new IprEvent(pkt, this, nextCycle(curTick + delay)); 2575728Sgblack@eecs.umich.edu _status = DcacheWaitResponse; 2585728Sgblack@eecs.umich.edu dcache_pkt = NULL; 2595728Sgblack@eecs.umich.edu } else if (!dcachePort.sendTiming(pkt)) { 2605728Sgblack@eecs.umich.edu _status = DcacheRetry; 2615728Sgblack@eecs.umich.edu dcache_pkt = pkt; 2625728Sgblack@eecs.umich.edu } else { 2635728Sgblack@eecs.umich.edu _status = DcacheWaitResponse; 2645728Sgblack@eecs.umich.edu // memory system takes ownership of packet 2655728Sgblack@eecs.umich.edu dcache_pkt = NULL; 2665728Sgblack@eecs.umich.edu } 2675728Sgblack@eecs.umich.edu return dcache_pkt == NULL; 2685728Sgblack@eecs.umich.edu} 2692623SN/A 2705894Sgblack@eecs.umich.eduvoid 2716973Stjones1@inf.ed.ac.ukTimingSimpleCPU::sendData(RequestPtr req, uint8_t *data, uint64_t *res, 2726973Stjones1@inf.ed.ac.uk bool read) 2735744Sgblack@eecs.umich.edu{ 2745894Sgblack@eecs.umich.edu PacketPtr pkt; 2755894Sgblack@eecs.umich.edu buildPacket(pkt, req, read); 2765894Sgblack@eecs.umich.edu pkt->dataDynamic<uint8_t>(data); 2775894Sgblack@eecs.umich.edu if (req->getFlags().isSet(Request::NO_ACCESS)) { 2785894Sgblack@eecs.umich.edu assert(!dcache_pkt); 2795894Sgblack@eecs.umich.edu pkt->makeResponse(); 2805894Sgblack@eecs.umich.edu completeDataAccess(pkt); 2815894Sgblack@eecs.umich.edu } else if (read) { 2825894Sgblack@eecs.umich.edu handleReadPacket(pkt); 2835894Sgblack@eecs.umich.edu } else { 2845894Sgblack@eecs.umich.edu bool do_access = true; // flag to suppress cache access 2855894Sgblack@eecs.umich.edu 2866102Sgblack@eecs.umich.edu if (req->isLLSC()) { 2875894Sgblack@eecs.umich.edu do_access = TheISA::handleLockedWrite(thread, req); 2885894Sgblack@eecs.umich.edu } else if (req->isCondSwap()) { 2895894Sgblack@eecs.umich.edu assert(res); 2905894Sgblack@eecs.umich.edu req->setExtraData(*res); 2915894Sgblack@eecs.umich.edu } 2925894Sgblack@eecs.umich.edu 2935894Sgblack@eecs.umich.edu if (do_access) { 2945894Sgblack@eecs.umich.edu dcache_pkt = pkt; 2955894Sgblack@eecs.umich.edu handleWritePacket(); 2965894Sgblack@eecs.umich.edu } else { 2975894Sgblack@eecs.umich.edu _status = DcacheWaitResponse; 2985894Sgblack@eecs.umich.edu completeDataAccess(pkt); 2995894Sgblack@eecs.umich.edu } 3005894Sgblack@eecs.umich.edu } 3015894Sgblack@eecs.umich.edu} 3025894Sgblack@eecs.umich.edu 3035894Sgblack@eecs.umich.eduvoid 3046973Stjones1@inf.ed.ac.ukTimingSimpleCPU::sendSplitData(RequestPtr req1, RequestPtr req2, 3056973Stjones1@inf.ed.ac.uk RequestPtr req, uint8_t *data, bool read) 3065894Sgblack@eecs.umich.edu{ 3075894Sgblack@eecs.umich.edu PacketPtr pkt1, pkt2; 3085894Sgblack@eecs.umich.edu buildSplitPacket(pkt1, pkt2, req1, req2, req, data, read); 3095894Sgblack@eecs.umich.edu if (req->getFlags().isSet(Request::NO_ACCESS)) { 3105894Sgblack@eecs.umich.edu assert(!dcache_pkt); 3115894Sgblack@eecs.umich.edu pkt1->makeResponse(); 3125894Sgblack@eecs.umich.edu completeDataAccess(pkt1); 3135894Sgblack@eecs.umich.edu } else if (read) { 3145894Sgblack@eecs.umich.edu if (handleReadPacket(pkt1)) { 3155894Sgblack@eecs.umich.edu SplitFragmentSenderState * send_state = 3165894Sgblack@eecs.umich.edu dynamic_cast<SplitFragmentSenderState *>(pkt1->senderState); 3175894Sgblack@eecs.umich.edu send_state->clearFromParent(); 3185894Sgblack@eecs.umich.edu if (handleReadPacket(pkt2)) { 3195894Sgblack@eecs.umich.edu send_state = dynamic_cast<SplitFragmentSenderState *>( 3205894Sgblack@eecs.umich.edu pkt1->senderState); 3215894Sgblack@eecs.umich.edu send_state->clearFromParent(); 3225894Sgblack@eecs.umich.edu } 3235894Sgblack@eecs.umich.edu } 3245894Sgblack@eecs.umich.edu } else { 3255894Sgblack@eecs.umich.edu dcache_pkt = pkt1; 3265894Sgblack@eecs.umich.edu if (handleWritePacket()) { 3275894Sgblack@eecs.umich.edu SplitFragmentSenderState * send_state = 3285894Sgblack@eecs.umich.edu dynamic_cast<SplitFragmentSenderState *>(pkt1->senderState); 3295894Sgblack@eecs.umich.edu send_state->clearFromParent(); 3305894Sgblack@eecs.umich.edu dcache_pkt = pkt2; 3315894Sgblack@eecs.umich.edu if (handleWritePacket()) { 3325894Sgblack@eecs.umich.edu send_state = dynamic_cast<SplitFragmentSenderState *>( 3335894Sgblack@eecs.umich.edu pkt1->senderState); 3345894Sgblack@eecs.umich.edu send_state->clearFromParent(); 3355894Sgblack@eecs.umich.edu } 3365894Sgblack@eecs.umich.edu } 3375894Sgblack@eecs.umich.edu } 3385894Sgblack@eecs.umich.edu} 3395894Sgblack@eecs.umich.edu 3405894Sgblack@eecs.umich.eduvoid 3415894Sgblack@eecs.umich.eduTimingSimpleCPU::translationFault(Fault fault) 3425894Sgblack@eecs.umich.edu{ 3436739Sgblack@eecs.umich.edu // fault may be NoFault in cases where a fault is suppressed, 3446739Sgblack@eecs.umich.edu // for instance prefetches. 3455894Sgblack@eecs.umich.edu numCycles += tickToCycles(curTick - previousTick); 3465894Sgblack@eecs.umich.edu previousTick = curTick; 3475894Sgblack@eecs.umich.edu 3485894Sgblack@eecs.umich.edu if (traceData) { 3495894Sgblack@eecs.umich.edu // Since there was a fault, we shouldn't trace this instruction. 3505894Sgblack@eecs.umich.edu delete traceData; 3515894Sgblack@eecs.umich.edu traceData = NULL; 3525744Sgblack@eecs.umich.edu } 3535744Sgblack@eecs.umich.edu 3545894Sgblack@eecs.umich.edu postExecute(); 3555894Sgblack@eecs.umich.edu 3565894Sgblack@eecs.umich.edu if (getState() == SimObject::Draining) { 3575894Sgblack@eecs.umich.edu advancePC(fault); 3585894Sgblack@eecs.umich.edu completeDrain(); 3595894Sgblack@eecs.umich.edu } else { 3605894Sgblack@eecs.umich.edu advanceInst(fault); 3615894Sgblack@eecs.umich.edu } 3625894Sgblack@eecs.umich.edu} 3635894Sgblack@eecs.umich.edu 3645894Sgblack@eecs.umich.eduvoid 3655894Sgblack@eecs.umich.eduTimingSimpleCPU::buildPacket(PacketPtr &pkt, RequestPtr req, bool read) 3665894Sgblack@eecs.umich.edu{ 3675894Sgblack@eecs.umich.edu MemCmd cmd; 3685894Sgblack@eecs.umich.edu if (read) { 3695894Sgblack@eecs.umich.edu cmd = MemCmd::ReadReq; 3706102Sgblack@eecs.umich.edu if (req->isLLSC()) 3715894Sgblack@eecs.umich.edu cmd = MemCmd::LoadLockedReq; 3725894Sgblack@eecs.umich.edu } else { 3735894Sgblack@eecs.umich.edu cmd = MemCmd::WriteReq; 3746102Sgblack@eecs.umich.edu if (req->isLLSC()) { 3755894Sgblack@eecs.umich.edu cmd = MemCmd::StoreCondReq; 3765894Sgblack@eecs.umich.edu } else if (req->isSwap()) { 3775894Sgblack@eecs.umich.edu cmd = MemCmd::SwapReq; 3785894Sgblack@eecs.umich.edu } 3795894Sgblack@eecs.umich.edu } 3805894Sgblack@eecs.umich.edu pkt = new Packet(req, cmd, Packet::Broadcast); 3815894Sgblack@eecs.umich.edu} 3825894Sgblack@eecs.umich.edu 3835894Sgblack@eecs.umich.eduvoid 3845894Sgblack@eecs.umich.eduTimingSimpleCPU::buildSplitPacket(PacketPtr &pkt1, PacketPtr &pkt2, 3855894Sgblack@eecs.umich.edu RequestPtr req1, RequestPtr req2, RequestPtr req, 3865894Sgblack@eecs.umich.edu uint8_t *data, bool read) 3875894Sgblack@eecs.umich.edu{ 3885894Sgblack@eecs.umich.edu pkt1 = pkt2 = NULL; 3895894Sgblack@eecs.umich.edu 3905744Sgblack@eecs.umich.edu assert(!req1->isMmapedIpr() && !req2->isMmapedIpr()); 3915744Sgblack@eecs.umich.edu 3925894Sgblack@eecs.umich.edu if (req->getFlags().isSet(Request::NO_ACCESS)) { 3935894Sgblack@eecs.umich.edu buildPacket(pkt1, req, read); 3945894Sgblack@eecs.umich.edu return; 3955894Sgblack@eecs.umich.edu } 3965894Sgblack@eecs.umich.edu 3975894Sgblack@eecs.umich.edu buildPacket(pkt1, req1, read); 3985894Sgblack@eecs.umich.edu buildPacket(pkt2, req2, read); 3995894Sgblack@eecs.umich.edu 4005744Sgblack@eecs.umich.edu req->setPhys(req1->getPaddr(), req->getSize(), req1->getFlags()); 4015744Sgblack@eecs.umich.edu PacketPtr pkt = new Packet(req, pkt1->cmd.responseCommand(), 4025744Sgblack@eecs.umich.edu Packet::Broadcast); 4035744Sgblack@eecs.umich.edu 4045744Sgblack@eecs.umich.edu pkt->dataDynamic<uint8_t>(data); 4055744Sgblack@eecs.umich.edu pkt1->dataStatic<uint8_t>(data); 4065744Sgblack@eecs.umich.edu pkt2->dataStatic<uint8_t>(data + req1->getSize()); 4075744Sgblack@eecs.umich.edu 4085744Sgblack@eecs.umich.edu SplitMainSenderState * main_send_state = new SplitMainSenderState; 4095744Sgblack@eecs.umich.edu pkt->senderState = main_send_state; 4105744Sgblack@eecs.umich.edu main_send_state->fragments[0] = pkt1; 4115744Sgblack@eecs.umich.edu main_send_state->fragments[1] = pkt2; 4125744Sgblack@eecs.umich.edu main_send_state->outstanding = 2; 4135744Sgblack@eecs.umich.edu pkt1->senderState = new SplitFragmentSenderState(pkt, 0); 4145744Sgblack@eecs.umich.edu pkt2->senderState = new SplitFragmentSenderState(pkt, 1); 4155744Sgblack@eecs.umich.edu} 4165744Sgblack@eecs.umich.edu 4172623SN/Atemplate <class T> 4182623SN/AFault 4192623SN/ATimingSimpleCPU::read(Addr addr, T &data, unsigned flags) 4202623SN/A{ 4215728Sgblack@eecs.umich.edu Fault fault; 4225728Sgblack@eecs.umich.edu const int asid = 0; 4236221Snate@binkert.org const ThreadID tid = 0; 4245728Sgblack@eecs.umich.edu const Addr pc = thread->readPC(); 4256227Snate@binkert.org unsigned block_size = dcachePort.peerBlockSize(); 4265728Sgblack@eecs.umich.edu int data_size = sizeof(T); 4276973Stjones1@inf.ed.ac.uk BaseTLB::Mode mode = BaseTLB::Read; 4282623SN/A 4297045Ssteve.reinhardt@amd.com if (traceData) { 4307045Ssteve.reinhardt@amd.com traceData->setAddr(addr); 4317045Ssteve.reinhardt@amd.com } 4327045Ssteve.reinhardt@amd.com 4335744Sgblack@eecs.umich.edu RequestPtr req = new Request(asid, addr, data_size, 4346221Snate@binkert.org flags, pc, _cpuId, tid); 4355728Sgblack@eecs.umich.edu 4365744Sgblack@eecs.umich.edu Addr split_addr = roundDown(addr + data_size - 1, block_size); 4375744Sgblack@eecs.umich.edu assert(split_addr <= addr || split_addr - addr < block_size); 4385728Sgblack@eecs.umich.edu 4397016SBrad.Beckmann@amd.com // This will need a new way to tell if it's hooked up to a cache or not. 4407016SBrad.Beckmann@amd.com if (req->isUncacheable()) 4417016SBrad.Beckmann@amd.com recordEvent("Uncached Write"); 4427016SBrad.Beckmann@amd.com 4435894Sgblack@eecs.umich.edu _status = DTBWaitResponse; 4445744Sgblack@eecs.umich.edu if (split_addr > addr) { 4455894Sgblack@eecs.umich.edu RequestPtr req1, req2; 4466102Sgblack@eecs.umich.edu assert(!req->isLLSC() && !req->isSwap()); 4475894Sgblack@eecs.umich.edu req->splitOnVaddr(split_addr, req1, req2); 4485894Sgblack@eecs.umich.edu 4496973Stjones1@inf.ed.ac.uk WholeTranslationState *state = 4506973Stjones1@inf.ed.ac.uk new WholeTranslationState(req, req1, req2, (uint8_t *)(new T), 4516973Stjones1@inf.ed.ac.uk NULL, mode); 4526973Stjones1@inf.ed.ac.uk DataTranslation<TimingSimpleCPU> *trans1 = 4536973Stjones1@inf.ed.ac.uk new DataTranslation<TimingSimpleCPU>(this, state, 0); 4546973Stjones1@inf.ed.ac.uk DataTranslation<TimingSimpleCPU> *trans2 = 4556973Stjones1@inf.ed.ac.uk new DataTranslation<TimingSimpleCPU>(this, state, 1); 4566973Stjones1@inf.ed.ac.uk 4576973Stjones1@inf.ed.ac.uk thread->dtb->translateTiming(req1, tc, trans1, mode); 4586973Stjones1@inf.ed.ac.uk thread->dtb->translateTiming(req2, tc, trans2, mode); 4595744Sgblack@eecs.umich.edu } else { 4606973Stjones1@inf.ed.ac.uk WholeTranslationState *state = 4616973Stjones1@inf.ed.ac.uk new WholeTranslationState(req, (uint8_t *)(new T), NULL, mode); 4626973Stjones1@inf.ed.ac.uk DataTranslation<TimingSimpleCPU> *translation 4636973Stjones1@inf.ed.ac.uk = new DataTranslation<TimingSimpleCPU>(this, state); 4646973Stjones1@inf.ed.ac.uk thread->dtb->translateTiming(req, tc, translation, mode); 4652623SN/A } 4662623SN/A 4675728Sgblack@eecs.umich.edu return NoFault; 4682623SN/A} 4692623SN/A 4702623SN/A#ifndef DOXYGEN_SHOULD_SKIP_THIS 4712623SN/A 4722623SN/Atemplate 4732623SN/AFault 4744040Ssaidi@eecs.umich.eduTimingSimpleCPU::read(Addr addr, Twin64_t &data, unsigned flags); 4754040Ssaidi@eecs.umich.edu 4764040Ssaidi@eecs.umich.edutemplate 4774040Ssaidi@eecs.umich.eduFault 4784115Ssaidi@eecs.umich.eduTimingSimpleCPU::read(Addr addr, Twin32_t &data, unsigned flags); 4794115Ssaidi@eecs.umich.edu 4804115Ssaidi@eecs.umich.edutemplate 4814115Ssaidi@eecs.umich.eduFault 4822623SN/ATimingSimpleCPU::read(Addr addr, uint64_t &data, unsigned flags); 4832623SN/A 4842623SN/Atemplate 4852623SN/AFault 4862623SN/ATimingSimpleCPU::read(Addr addr, uint32_t &data, unsigned flags); 4872623SN/A 4882623SN/Atemplate 4892623SN/AFault 4902623SN/ATimingSimpleCPU::read(Addr addr, uint16_t &data, unsigned flags); 4912623SN/A 4922623SN/Atemplate 4932623SN/AFault 4942623SN/ATimingSimpleCPU::read(Addr addr, uint8_t &data, unsigned flags); 4952623SN/A 4962623SN/A#endif //DOXYGEN_SHOULD_SKIP_THIS 4972623SN/A 4982623SN/Atemplate<> 4992623SN/AFault 5002623SN/ATimingSimpleCPU::read(Addr addr, double &data, unsigned flags) 5012623SN/A{ 5022623SN/A return read(addr, *(uint64_t*)&data, flags); 5032623SN/A} 5042623SN/A 5052623SN/Atemplate<> 5062623SN/AFault 5072623SN/ATimingSimpleCPU::read(Addr addr, float &data, unsigned flags) 5082623SN/A{ 5092623SN/A return read(addr, *(uint32_t*)&data, flags); 5102623SN/A} 5112623SN/A 5122623SN/Atemplate<> 5132623SN/AFault 5142623SN/ATimingSimpleCPU::read(Addr addr, int32_t &data, unsigned flags) 5152623SN/A{ 5162623SN/A return read(addr, (uint32_t&)data, flags); 5172623SN/A} 5182623SN/A 5195728Sgblack@eecs.umich.edubool 5205728Sgblack@eecs.umich.eduTimingSimpleCPU::handleWritePacket() 5215728Sgblack@eecs.umich.edu{ 5225728Sgblack@eecs.umich.edu RequestPtr req = dcache_pkt->req; 5235728Sgblack@eecs.umich.edu if (req->isMmapedIpr()) { 5245728Sgblack@eecs.umich.edu Tick delay; 5255728Sgblack@eecs.umich.edu delay = TheISA::handleIprWrite(thread->getTC(), dcache_pkt); 5265728Sgblack@eecs.umich.edu new IprEvent(dcache_pkt, this, nextCycle(curTick + delay)); 5275728Sgblack@eecs.umich.edu _status = DcacheWaitResponse; 5285728Sgblack@eecs.umich.edu dcache_pkt = NULL; 5295728Sgblack@eecs.umich.edu } else if (!dcachePort.sendTiming(dcache_pkt)) { 5305728Sgblack@eecs.umich.edu _status = DcacheRetry; 5315728Sgblack@eecs.umich.edu } else { 5325728Sgblack@eecs.umich.edu _status = DcacheWaitResponse; 5335728Sgblack@eecs.umich.edu // memory system takes ownership of packet 5345728Sgblack@eecs.umich.edu dcache_pkt = NULL; 5355728Sgblack@eecs.umich.edu } 5365728Sgblack@eecs.umich.edu return dcache_pkt == NULL; 5375728Sgblack@eecs.umich.edu} 5382623SN/A 5392623SN/Atemplate <class T> 5402623SN/AFault 5412623SN/ATimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res) 5422623SN/A{ 5435728Sgblack@eecs.umich.edu const int asid = 0; 5446221Snate@binkert.org const ThreadID tid = 0; 5455728Sgblack@eecs.umich.edu const Addr pc = thread->readPC(); 5466227Snate@binkert.org unsigned block_size = dcachePort.peerBlockSize(); 5475728Sgblack@eecs.umich.edu int data_size = sizeof(T); 5486973Stjones1@inf.ed.ac.uk BaseTLB::Mode mode = BaseTLB::Write; 5493169Sstever@eecs.umich.edu 5507045Ssteve.reinhardt@amd.com if (traceData) { 5517045Ssteve.reinhardt@amd.com traceData->setAddr(addr); 5527045Ssteve.reinhardt@amd.com traceData->setData(data); 5537045Ssteve.reinhardt@amd.com } 5547045Ssteve.reinhardt@amd.com 5555744Sgblack@eecs.umich.edu RequestPtr req = new Request(asid, addr, data_size, 5566221Snate@binkert.org flags, pc, _cpuId, tid); 5575728Sgblack@eecs.umich.edu 5585744Sgblack@eecs.umich.edu Addr split_addr = roundDown(addr + data_size - 1, block_size); 5595744Sgblack@eecs.umich.edu assert(split_addr <= addr || split_addr - addr < block_size); 5605728Sgblack@eecs.umich.edu 5617016SBrad.Beckmann@amd.com // This will need a new way to tell if it's hooked up to a cache or not. 5627016SBrad.Beckmann@amd.com if (req->isUncacheable()) 5637016SBrad.Beckmann@amd.com recordEvent("Uncached Write"); 5647016SBrad.Beckmann@amd.com 5655894Sgblack@eecs.umich.edu T *dataP = new T; 5666012Ssteve.reinhardt@amd.com *dataP = TheISA::htog(data); 5675894Sgblack@eecs.umich.edu _status = DTBWaitResponse; 5685744Sgblack@eecs.umich.edu if (split_addr > addr) { 5695894Sgblack@eecs.umich.edu RequestPtr req1, req2; 5706102Sgblack@eecs.umich.edu assert(!req->isLLSC() && !req->isSwap()); 5715894Sgblack@eecs.umich.edu req->splitOnVaddr(split_addr, req1, req2); 5725894Sgblack@eecs.umich.edu 5736973Stjones1@inf.ed.ac.uk WholeTranslationState *state = 5746973Stjones1@inf.ed.ac.uk new WholeTranslationState(req, req1, req2, (uint8_t *)dataP, 5756973Stjones1@inf.ed.ac.uk res, mode); 5766973Stjones1@inf.ed.ac.uk DataTranslation<TimingSimpleCPU> *trans1 = 5776973Stjones1@inf.ed.ac.uk new DataTranslation<TimingSimpleCPU>(this, state, 0); 5786973Stjones1@inf.ed.ac.uk DataTranslation<TimingSimpleCPU> *trans2 = 5796973Stjones1@inf.ed.ac.uk new DataTranslation<TimingSimpleCPU>(this, state, 1); 5806973Stjones1@inf.ed.ac.uk 5816973Stjones1@inf.ed.ac.uk thread->dtb->translateTiming(req1, tc, trans1, mode); 5826973Stjones1@inf.ed.ac.uk thread->dtb->translateTiming(req2, tc, trans2, mode); 5835744Sgblack@eecs.umich.edu } else { 5846973Stjones1@inf.ed.ac.uk WholeTranslationState *state = 5856973Stjones1@inf.ed.ac.uk new WholeTranslationState(req, (uint8_t *)dataP, res, mode); 5866973Stjones1@inf.ed.ac.uk DataTranslation<TimingSimpleCPU> *translation = 5876973Stjones1@inf.ed.ac.uk new DataTranslation<TimingSimpleCPU>(this, state); 5886973Stjones1@inf.ed.ac.uk thread->dtb->translateTiming(req, tc, translation, mode); 5892623SN/A } 5902623SN/A 5917045Ssteve.reinhardt@amd.com // Translation faults will be returned via finishTranslation() 5925728Sgblack@eecs.umich.edu return NoFault; 5932623SN/A} 5942623SN/A 5952623SN/A 5962623SN/A#ifndef DOXYGEN_SHOULD_SKIP_THIS 5972623SN/Atemplate 5982623SN/AFault 5994224Sgblack@eecs.umich.eduTimingSimpleCPU::write(Twin32_t data, Addr addr, 6004224Sgblack@eecs.umich.edu unsigned flags, uint64_t *res); 6014224Sgblack@eecs.umich.edu 6024224Sgblack@eecs.umich.edutemplate 6034224Sgblack@eecs.umich.eduFault 6044224Sgblack@eecs.umich.eduTimingSimpleCPU::write(Twin64_t data, Addr addr, 6054224Sgblack@eecs.umich.edu unsigned flags, uint64_t *res); 6064224Sgblack@eecs.umich.edu 6074224Sgblack@eecs.umich.edutemplate 6084224Sgblack@eecs.umich.eduFault 6092623SN/ATimingSimpleCPU::write(uint64_t data, Addr addr, 6102623SN/A unsigned flags, uint64_t *res); 6112623SN/A 6122623SN/Atemplate 6132623SN/AFault 6142623SN/ATimingSimpleCPU::write(uint32_t data, Addr addr, 6152623SN/A unsigned flags, uint64_t *res); 6162623SN/A 6172623SN/Atemplate 6182623SN/AFault 6192623SN/ATimingSimpleCPU::write(uint16_t data, Addr addr, 6202623SN/A unsigned flags, uint64_t *res); 6212623SN/A 6222623SN/Atemplate 6232623SN/AFault 6242623SN/ATimingSimpleCPU::write(uint8_t data, Addr addr, 6252623SN/A unsigned flags, uint64_t *res); 6262623SN/A 6272623SN/A#endif //DOXYGEN_SHOULD_SKIP_THIS 6282623SN/A 6292623SN/Atemplate<> 6302623SN/AFault 6312623SN/ATimingSimpleCPU::write(double data, Addr addr, unsigned flags, uint64_t *res) 6322623SN/A{ 6332623SN/A return write(*(uint64_t*)&data, addr, flags, res); 6342623SN/A} 6352623SN/A 6362623SN/Atemplate<> 6372623SN/AFault 6382623SN/ATimingSimpleCPU::write(float data, Addr addr, unsigned flags, uint64_t *res) 6392623SN/A{ 6402623SN/A return write(*(uint32_t*)&data, addr, flags, res); 6412623SN/A} 6422623SN/A 6432623SN/A 6442623SN/Atemplate<> 6452623SN/AFault 6462623SN/ATimingSimpleCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res) 6472623SN/A{ 6482623SN/A return write((uint32_t)data, addr, flags, res); 6492623SN/A} 6502623SN/A 6512623SN/A 6522623SN/Avoid 6536973Stjones1@inf.ed.ac.ukTimingSimpleCPU::finishTranslation(WholeTranslationState *state) 6546973Stjones1@inf.ed.ac.uk{ 6556973Stjones1@inf.ed.ac.uk _status = Running; 6566973Stjones1@inf.ed.ac.uk 6576973Stjones1@inf.ed.ac.uk if (state->getFault() != NoFault) { 6586973Stjones1@inf.ed.ac.uk if (state->isPrefetch()) { 6596973Stjones1@inf.ed.ac.uk state->setNoFault(); 6606973Stjones1@inf.ed.ac.uk } 6616973Stjones1@inf.ed.ac.uk delete state->data; 6626973Stjones1@inf.ed.ac.uk state->deleteReqs(); 6636973Stjones1@inf.ed.ac.uk translationFault(state->getFault()); 6646973Stjones1@inf.ed.ac.uk } else { 6656973Stjones1@inf.ed.ac.uk if (!state->isSplit) { 6666973Stjones1@inf.ed.ac.uk sendData(state->mainReq, state->data, state->res, 6676973Stjones1@inf.ed.ac.uk state->mode == BaseTLB::Read); 6686973Stjones1@inf.ed.ac.uk } else { 6696973Stjones1@inf.ed.ac.uk sendSplitData(state->sreqLow, state->sreqHigh, state->mainReq, 6706973Stjones1@inf.ed.ac.uk state->data, state->mode == BaseTLB::Read); 6716973Stjones1@inf.ed.ac.uk } 6726973Stjones1@inf.ed.ac.uk } 6736973Stjones1@inf.ed.ac.uk 6746973Stjones1@inf.ed.ac.uk delete state; 6756973Stjones1@inf.ed.ac.uk} 6766973Stjones1@inf.ed.ac.uk 6776973Stjones1@inf.ed.ac.uk 6786973Stjones1@inf.ed.ac.ukvoid 6792623SN/ATimingSimpleCPU::fetch() 6802623SN/A{ 6815221Ssaidi@eecs.umich.edu DPRINTF(SimpleCPU, "Fetch\n"); 6825221Ssaidi@eecs.umich.edu 6833387Sgblack@eecs.umich.edu if (!curStaticInst || !curStaticInst->isDelayedCommit()) 6843387Sgblack@eecs.umich.edu checkForInterrupts(); 6852631SN/A 6865348Ssaidi@eecs.umich.edu checkPcEventQueue(); 6875348Ssaidi@eecs.umich.edu 6885669Sgblack@eecs.umich.edu bool fromRom = isRomMicroPC(thread->readMicroPC()); 6892623SN/A 6905914Sgblack@eecs.umich.edu if (!fromRom && !curMacroStaticInst) { 6915669Sgblack@eecs.umich.edu Request *ifetch_req = new Request(); 6925712Shsul@eecs.umich.edu ifetch_req->setThreadContext(_cpuId, /* thread ID */ 0); 6935894Sgblack@eecs.umich.edu setupFetchRequest(ifetch_req); 6946023Snate@binkert.org thread->itb->translateTiming(ifetch_req, tc, &fetchTranslation, 6956023Snate@binkert.org BaseTLB::Execute); 6962623SN/A } else { 6975669Sgblack@eecs.umich.edu _status = IcacheWaitResponse; 6985669Sgblack@eecs.umich.edu completeIfetch(NULL); 6995894Sgblack@eecs.umich.edu 7005894Sgblack@eecs.umich.edu numCycles += tickToCycles(curTick - previousTick); 7015894Sgblack@eecs.umich.edu previousTick = curTick; 7025894Sgblack@eecs.umich.edu } 7035894Sgblack@eecs.umich.edu} 7045894Sgblack@eecs.umich.edu 7055894Sgblack@eecs.umich.edu 7065894Sgblack@eecs.umich.eduvoid 7075894Sgblack@eecs.umich.eduTimingSimpleCPU::sendFetch(Fault fault, RequestPtr req, ThreadContext *tc) 7085894Sgblack@eecs.umich.edu{ 7095894Sgblack@eecs.umich.edu if (fault == NoFault) { 7105894Sgblack@eecs.umich.edu ifetch_pkt = new Packet(req, MemCmd::ReadReq, Packet::Broadcast); 7115894Sgblack@eecs.umich.edu ifetch_pkt->dataStatic(&inst); 7125894Sgblack@eecs.umich.edu 7135894Sgblack@eecs.umich.edu if (!icachePort.sendTiming(ifetch_pkt)) { 7145894Sgblack@eecs.umich.edu // Need to wait for retry 7155894Sgblack@eecs.umich.edu _status = IcacheRetry; 7165894Sgblack@eecs.umich.edu } else { 7175894Sgblack@eecs.umich.edu // Need to wait for cache to respond 7185894Sgblack@eecs.umich.edu _status = IcacheWaitResponse; 7195894Sgblack@eecs.umich.edu // ownership of packet transferred to memory system 7205894Sgblack@eecs.umich.edu ifetch_pkt = NULL; 7215894Sgblack@eecs.umich.edu } 7225894Sgblack@eecs.umich.edu } else { 7235894Sgblack@eecs.umich.edu delete req; 7245894Sgblack@eecs.umich.edu // fetch fault: advance directly to next instruction (fault handler) 7255894Sgblack@eecs.umich.edu advanceInst(fault); 7262623SN/A } 7273222Sktlim@umich.edu 7285099Ssaidi@eecs.umich.edu numCycles += tickToCycles(curTick - previousTick); 7293222Sktlim@umich.edu previousTick = curTick; 7302623SN/A} 7312623SN/A 7322623SN/A 7332623SN/Avoid 7342644Sstever@eecs.umich.eduTimingSimpleCPU::advanceInst(Fault fault) 7352623SN/A{ 7365726Sgblack@eecs.umich.edu if (fault != NoFault || !stayAtPC) 7375726Sgblack@eecs.umich.edu advancePC(fault); 7382623SN/A 7392631SN/A if (_status == Running) { 7402631SN/A // kick off fetch of next instruction... callback from icache 7412631SN/A // response will cause that instruction to be executed, 7422631SN/A // keeping the CPU running. 7432631SN/A fetch(); 7442631SN/A } 7452623SN/A} 7462623SN/A 7472623SN/A 7482623SN/Avoid 7493349Sbinkertn@umich.eduTimingSimpleCPU::completeIfetch(PacketPtr pkt) 7502623SN/A{ 7515221Ssaidi@eecs.umich.edu DPRINTF(SimpleCPU, "Complete ICache Fetch\n"); 7525221Ssaidi@eecs.umich.edu 7532623SN/A // received a response from the icache: execute the received 7542623SN/A // instruction 7555669Sgblack@eecs.umich.edu 7565669Sgblack@eecs.umich.edu assert(!pkt || !pkt->isError()); 7572623SN/A assert(_status == IcacheWaitResponse); 7582798Sktlim@umich.edu 7592623SN/A _status = Running; 7602644Sstever@eecs.umich.edu 7615099Ssaidi@eecs.umich.edu numCycles += tickToCycles(curTick - previousTick); 7623222Sktlim@umich.edu previousTick = curTick; 7633222Sktlim@umich.edu 7642839Sktlim@umich.edu if (getState() == SimObject::Draining) { 7655669Sgblack@eecs.umich.edu if (pkt) { 7665669Sgblack@eecs.umich.edu delete pkt->req; 7675669Sgblack@eecs.umich.edu delete pkt; 7685669Sgblack@eecs.umich.edu } 7693658Sktlim@umich.edu 7702839Sktlim@umich.edu completeDrain(); 7712798Sktlim@umich.edu return; 7722798Sktlim@umich.edu } 7732798Sktlim@umich.edu 7742623SN/A preExecute(); 7755726Sgblack@eecs.umich.edu if (curStaticInst && 7765726Sgblack@eecs.umich.edu curStaticInst->isMemRef() && !curStaticInst->isDataPrefetch()) { 7772623SN/A // load or store: just send to dcache 7782623SN/A Fault fault = curStaticInst->initiateAcc(this, traceData); 7793170Sstever@eecs.umich.edu if (_status != Running) { 7803170Sstever@eecs.umich.edu // instruction will complete in dcache response callback 7815894Sgblack@eecs.umich.edu assert(_status == DcacheWaitResponse || 7825894Sgblack@eecs.umich.edu _status == DcacheRetry || DTBWaitResponse); 7833170Sstever@eecs.umich.edu assert(fault == NoFault); 7842644Sstever@eecs.umich.edu } else { 7855894Sgblack@eecs.umich.edu if (fault != NoFault && traceData) { 7865001Sgblack@eecs.umich.edu // If there was a fault, we shouldn't trace this instruction. 7875001Sgblack@eecs.umich.edu delete traceData; 7885001Sgblack@eecs.umich.edu traceData = NULL; 7893170Sstever@eecs.umich.edu } 7904998Sgblack@eecs.umich.edu 7912644Sstever@eecs.umich.edu postExecute(); 7925103Ssaidi@eecs.umich.edu // @todo remove me after debugging with legion done 7935103Ssaidi@eecs.umich.edu if (curStaticInst && (!curStaticInst->isMicroop() || 7945103Ssaidi@eecs.umich.edu curStaticInst->isFirstMicroop())) 7955103Ssaidi@eecs.umich.edu instCnt++; 7962644Sstever@eecs.umich.edu advanceInst(fault); 7972644Sstever@eecs.umich.edu } 7985726Sgblack@eecs.umich.edu } else if (curStaticInst) { 7992623SN/A // non-memory instruction: execute completely now 8002623SN/A Fault fault = curStaticInst->execute(this, traceData); 8014998Sgblack@eecs.umich.edu 8024998Sgblack@eecs.umich.edu // keep an instruction count 8034998Sgblack@eecs.umich.edu if (fault == NoFault) 8044998Sgblack@eecs.umich.edu countInst(); 8055001Sgblack@eecs.umich.edu else if (traceData) { 8065001Sgblack@eecs.umich.edu // If there was a fault, we shouldn't trace this instruction. 8075001Sgblack@eecs.umich.edu delete traceData; 8085001Sgblack@eecs.umich.edu traceData = NULL; 8095001Sgblack@eecs.umich.edu } 8104998Sgblack@eecs.umich.edu 8112644Sstever@eecs.umich.edu postExecute(); 8125103Ssaidi@eecs.umich.edu // @todo remove me after debugging with legion done 8135103Ssaidi@eecs.umich.edu if (curStaticInst && (!curStaticInst->isMicroop() || 8145103Ssaidi@eecs.umich.edu curStaticInst->isFirstMicroop())) 8155103Ssaidi@eecs.umich.edu instCnt++; 8162644Sstever@eecs.umich.edu advanceInst(fault); 8175726Sgblack@eecs.umich.edu } else { 8185726Sgblack@eecs.umich.edu advanceInst(NoFault); 8192623SN/A } 8203658Sktlim@umich.edu 8215669Sgblack@eecs.umich.edu if (pkt) { 8225669Sgblack@eecs.umich.edu delete pkt->req; 8235669Sgblack@eecs.umich.edu delete pkt; 8245669Sgblack@eecs.umich.edu } 8252623SN/A} 8262623SN/A 8272948Ssaidi@eecs.umich.eduvoid 8282948Ssaidi@eecs.umich.eduTimingSimpleCPU::IcachePort::ITickEvent::process() 8292948Ssaidi@eecs.umich.edu{ 8302948Ssaidi@eecs.umich.edu cpu->completeIfetch(pkt); 8312948Ssaidi@eecs.umich.edu} 8322623SN/A 8332623SN/Abool 8343349Sbinkertn@umich.eduTimingSimpleCPU::IcachePort::recvTiming(PacketPtr pkt) 8352623SN/A{ 8364986Ssaidi@eecs.umich.edu if (pkt->isResponse() && !pkt->wasNacked()) { 8373310Srdreslin@umich.edu // delay processing of returned data until next CPU clock edge 8384584Ssaidi@eecs.umich.edu Tick next_tick = cpu->nextCycle(curTick); 8392948Ssaidi@eecs.umich.edu 8403495Sktlim@umich.edu if (next_tick == curTick) 8413310Srdreslin@umich.edu cpu->completeIfetch(pkt); 8423310Srdreslin@umich.edu else 8433495Sktlim@umich.edu tickEvent.schedule(pkt, next_tick); 8442948Ssaidi@eecs.umich.edu 8453310Srdreslin@umich.edu return true; 8463310Srdreslin@umich.edu } 8474870Sstever@eecs.umich.edu else if (pkt->wasNacked()) { 8484433Ssaidi@eecs.umich.edu assert(cpu->_status == IcacheWaitResponse); 8494433Ssaidi@eecs.umich.edu pkt->reinitNacked(); 8504433Ssaidi@eecs.umich.edu if (!sendTiming(pkt)) { 8514433Ssaidi@eecs.umich.edu cpu->_status = IcacheRetry; 8524433Ssaidi@eecs.umich.edu cpu->ifetch_pkt = pkt; 8534433Ssaidi@eecs.umich.edu } 8543310Srdreslin@umich.edu } 8554433Ssaidi@eecs.umich.edu //Snooping a Coherence Request, do nothing 8564433Ssaidi@eecs.umich.edu return true; 8572623SN/A} 8582623SN/A 8592657Ssaidi@eecs.umich.eduvoid 8602623SN/ATimingSimpleCPU::IcachePort::recvRetry() 8612623SN/A{ 8622623SN/A // we shouldn't get a retry unless we have a packet that we're 8632623SN/A // waiting to transmit 8642623SN/A assert(cpu->ifetch_pkt != NULL); 8652623SN/A assert(cpu->_status == IcacheRetry); 8663349Sbinkertn@umich.edu PacketPtr tmp = cpu->ifetch_pkt; 8672657Ssaidi@eecs.umich.edu if (sendTiming(tmp)) { 8682657Ssaidi@eecs.umich.edu cpu->_status = IcacheWaitResponse; 8692657Ssaidi@eecs.umich.edu cpu->ifetch_pkt = NULL; 8702657Ssaidi@eecs.umich.edu } 8712623SN/A} 8722623SN/A 8732623SN/Avoid 8743349Sbinkertn@umich.eduTimingSimpleCPU::completeDataAccess(PacketPtr pkt) 8752623SN/A{ 8762623SN/A // received a response from the dcache: complete the load or store 8772623SN/A // instruction 8784870Sstever@eecs.umich.edu assert(!pkt->isError()); 8792623SN/A 8805099Ssaidi@eecs.umich.edu numCycles += tickToCycles(curTick - previousTick); 8813222Sktlim@umich.edu previousTick = curTick; 8823184Srdreslin@umich.edu 8835728Sgblack@eecs.umich.edu if (pkt->senderState) { 8845728Sgblack@eecs.umich.edu SplitFragmentSenderState * send_state = 8855728Sgblack@eecs.umich.edu dynamic_cast<SplitFragmentSenderState *>(pkt->senderState); 8865728Sgblack@eecs.umich.edu assert(send_state); 8875728Sgblack@eecs.umich.edu delete pkt->req; 8885728Sgblack@eecs.umich.edu delete pkt; 8895728Sgblack@eecs.umich.edu PacketPtr big_pkt = send_state->bigPkt; 8905728Sgblack@eecs.umich.edu delete send_state; 8915728Sgblack@eecs.umich.edu 8925728Sgblack@eecs.umich.edu SplitMainSenderState * main_send_state = 8935728Sgblack@eecs.umich.edu dynamic_cast<SplitMainSenderState *>(big_pkt->senderState); 8945728Sgblack@eecs.umich.edu assert(main_send_state); 8955728Sgblack@eecs.umich.edu // Record the fact that this packet is no longer outstanding. 8965728Sgblack@eecs.umich.edu assert(main_send_state->outstanding != 0); 8975728Sgblack@eecs.umich.edu main_send_state->outstanding--; 8985728Sgblack@eecs.umich.edu 8995728Sgblack@eecs.umich.edu if (main_send_state->outstanding) { 9005728Sgblack@eecs.umich.edu return; 9015728Sgblack@eecs.umich.edu } else { 9025728Sgblack@eecs.umich.edu delete main_send_state; 9035728Sgblack@eecs.umich.edu big_pkt->senderState = NULL; 9045728Sgblack@eecs.umich.edu pkt = big_pkt; 9055728Sgblack@eecs.umich.edu } 9065728Sgblack@eecs.umich.edu } 9075728Sgblack@eecs.umich.edu 9085894Sgblack@eecs.umich.edu assert(_status == DcacheWaitResponse || _status == DTBWaitResponse); 9095728Sgblack@eecs.umich.edu _status = Running; 9105728Sgblack@eecs.umich.edu 9112623SN/A Fault fault = curStaticInst->completeAcc(pkt, this, traceData); 9122623SN/A 9134998Sgblack@eecs.umich.edu // keep an instruction count 9144998Sgblack@eecs.umich.edu if (fault == NoFault) 9154998Sgblack@eecs.umich.edu countInst(); 9165001Sgblack@eecs.umich.edu else if (traceData) { 9175001Sgblack@eecs.umich.edu // If there was a fault, we shouldn't trace this instruction. 9185001Sgblack@eecs.umich.edu delete traceData; 9195001Sgblack@eecs.umich.edu traceData = NULL; 9205001Sgblack@eecs.umich.edu } 9214998Sgblack@eecs.umich.edu 9225507Sstever@gmail.com // the locked flag may be cleared on the response packet, so check 9235507Sstever@gmail.com // pkt->req and not pkt to see if it was a load-locked 9246102Sgblack@eecs.umich.edu if (pkt->isRead() && pkt->req->isLLSC()) { 9253170Sstever@eecs.umich.edu TheISA::handleLockedRead(thread, pkt->req); 9263170Sstever@eecs.umich.edu } 9273170Sstever@eecs.umich.edu 9282644Sstever@eecs.umich.edu delete pkt->req; 9292644Sstever@eecs.umich.edu delete pkt; 9302644Sstever@eecs.umich.edu 9313184Srdreslin@umich.edu postExecute(); 9323227Sktlim@umich.edu 9333201Shsul@eecs.umich.edu if (getState() == SimObject::Draining) { 9343201Shsul@eecs.umich.edu advancePC(fault); 9353201Shsul@eecs.umich.edu completeDrain(); 9363201Shsul@eecs.umich.edu 9373201Shsul@eecs.umich.edu return; 9383201Shsul@eecs.umich.edu } 9393201Shsul@eecs.umich.edu 9402644Sstever@eecs.umich.edu advanceInst(fault); 9412623SN/A} 9422623SN/A 9432623SN/A 9442798Sktlim@umich.eduvoid 9452839Sktlim@umich.eduTimingSimpleCPU::completeDrain() 9462798Sktlim@umich.edu{ 9472839Sktlim@umich.edu DPRINTF(Config, "Done draining\n"); 9482901Ssaidi@eecs.umich.edu changeState(SimObject::Drained); 9492839Sktlim@umich.edu drainEvent->process(); 9502798Sktlim@umich.edu} 9512623SN/A 9524192Sktlim@umich.eduvoid 9534192Sktlim@umich.eduTimingSimpleCPU::DcachePort::setPeer(Port *port) 9544192Sktlim@umich.edu{ 9554192Sktlim@umich.edu Port::setPeer(port); 9564192Sktlim@umich.edu 9574192Sktlim@umich.edu#if FULL_SYSTEM 9584192Sktlim@umich.edu // Update the ThreadContext's memory ports (Functional/Virtual 9594192Sktlim@umich.edu // Ports) 9605497Ssaidi@eecs.umich.edu cpu->tcBase()->connectMemPorts(cpu->tcBase()); 9614192Sktlim@umich.edu#endif 9624192Sktlim@umich.edu} 9634192Sktlim@umich.edu 9642623SN/Abool 9653349Sbinkertn@umich.eduTimingSimpleCPU::DcachePort::recvTiming(PacketPtr pkt) 9662623SN/A{ 9674986Ssaidi@eecs.umich.edu if (pkt->isResponse() && !pkt->wasNacked()) { 9683310Srdreslin@umich.edu // delay processing of returned data until next CPU clock edge 9694584Ssaidi@eecs.umich.edu Tick next_tick = cpu->nextCycle(curTick); 9702948Ssaidi@eecs.umich.edu 9715728Sgblack@eecs.umich.edu if (next_tick == curTick) { 9723310Srdreslin@umich.edu cpu->completeDataAccess(pkt); 9735728Sgblack@eecs.umich.edu } else { 9743495Sktlim@umich.edu tickEvent.schedule(pkt, next_tick); 9755728Sgblack@eecs.umich.edu } 9762948Ssaidi@eecs.umich.edu 9773310Srdreslin@umich.edu return true; 9783310Srdreslin@umich.edu } 9794870Sstever@eecs.umich.edu else if (pkt->wasNacked()) { 9804433Ssaidi@eecs.umich.edu assert(cpu->_status == DcacheWaitResponse); 9814433Ssaidi@eecs.umich.edu pkt->reinitNacked(); 9824433Ssaidi@eecs.umich.edu if (!sendTiming(pkt)) { 9834433Ssaidi@eecs.umich.edu cpu->_status = DcacheRetry; 9844433Ssaidi@eecs.umich.edu cpu->dcache_pkt = pkt; 9854433Ssaidi@eecs.umich.edu } 9863310Srdreslin@umich.edu } 9874433Ssaidi@eecs.umich.edu //Snooping a Coherence Request, do nothing 9884433Ssaidi@eecs.umich.edu return true; 9892948Ssaidi@eecs.umich.edu} 9902948Ssaidi@eecs.umich.edu 9912948Ssaidi@eecs.umich.eduvoid 9922948Ssaidi@eecs.umich.eduTimingSimpleCPU::DcachePort::DTickEvent::process() 9932948Ssaidi@eecs.umich.edu{ 9942630SN/A cpu->completeDataAccess(pkt); 9952623SN/A} 9962623SN/A 9972657Ssaidi@eecs.umich.eduvoid 9982623SN/ATimingSimpleCPU::DcachePort::recvRetry() 9992623SN/A{ 10002623SN/A // we shouldn't get a retry unless we have a packet that we're 10012623SN/A // waiting to transmit 10022623SN/A assert(cpu->dcache_pkt != NULL); 10032623SN/A assert(cpu->_status == DcacheRetry); 10043349Sbinkertn@umich.edu PacketPtr tmp = cpu->dcache_pkt; 10055728Sgblack@eecs.umich.edu if (tmp->senderState) { 10065728Sgblack@eecs.umich.edu // This is a packet from a split access. 10075728Sgblack@eecs.umich.edu SplitFragmentSenderState * send_state = 10085728Sgblack@eecs.umich.edu dynamic_cast<SplitFragmentSenderState *>(tmp->senderState); 10095728Sgblack@eecs.umich.edu assert(send_state); 10105728Sgblack@eecs.umich.edu PacketPtr big_pkt = send_state->bigPkt; 10115728Sgblack@eecs.umich.edu 10125728Sgblack@eecs.umich.edu SplitMainSenderState * main_send_state = 10135728Sgblack@eecs.umich.edu dynamic_cast<SplitMainSenderState *>(big_pkt->senderState); 10145728Sgblack@eecs.umich.edu assert(main_send_state); 10155728Sgblack@eecs.umich.edu 10165728Sgblack@eecs.umich.edu if (sendTiming(tmp)) { 10175728Sgblack@eecs.umich.edu // If we were able to send without retrying, record that fact 10185728Sgblack@eecs.umich.edu // and try sending the other fragment. 10195728Sgblack@eecs.umich.edu send_state->clearFromParent(); 10205728Sgblack@eecs.umich.edu int other_index = main_send_state->getPendingFragment(); 10215728Sgblack@eecs.umich.edu if (other_index > 0) { 10225728Sgblack@eecs.umich.edu tmp = main_send_state->fragments[other_index]; 10235728Sgblack@eecs.umich.edu cpu->dcache_pkt = tmp; 10245728Sgblack@eecs.umich.edu if ((big_pkt->isRead() && cpu->handleReadPacket(tmp)) || 10255728Sgblack@eecs.umich.edu (big_pkt->isWrite() && cpu->handleWritePacket())) { 10265728Sgblack@eecs.umich.edu main_send_state->fragments[other_index] = NULL; 10275728Sgblack@eecs.umich.edu } 10285728Sgblack@eecs.umich.edu } else { 10295728Sgblack@eecs.umich.edu cpu->_status = DcacheWaitResponse; 10305728Sgblack@eecs.umich.edu // memory system takes ownership of packet 10315728Sgblack@eecs.umich.edu cpu->dcache_pkt = NULL; 10325728Sgblack@eecs.umich.edu } 10335728Sgblack@eecs.umich.edu } 10345728Sgblack@eecs.umich.edu } else if (sendTiming(tmp)) { 10352657Ssaidi@eecs.umich.edu cpu->_status = DcacheWaitResponse; 10363170Sstever@eecs.umich.edu // memory system takes ownership of packet 10372657Ssaidi@eecs.umich.edu cpu->dcache_pkt = NULL; 10382657Ssaidi@eecs.umich.edu } 10392623SN/A} 10402623SN/A 10415606Snate@binkert.orgTimingSimpleCPU::IprEvent::IprEvent(Packet *_pkt, TimingSimpleCPU *_cpu, 10425606Snate@binkert.org Tick t) 10435606Snate@binkert.org : pkt(_pkt), cpu(_cpu) 10445103Ssaidi@eecs.umich.edu{ 10455606Snate@binkert.org cpu->schedule(this, t); 10465103Ssaidi@eecs.umich.edu} 10475103Ssaidi@eecs.umich.edu 10485103Ssaidi@eecs.umich.eduvoid 10495103Ssaidi@eecs.umich.eduTimingSimpleCPU::IprEvent::process() 10505103Ssaidi@eecs.umich.edu{ 10515103Ssaidi@eecs.umich.edu cpu->completeDataAccess(pkt); 10525103Ssaidi@eecs.umich.edu} 10535103Ssaidi@eecs.umich.edu 10545103Ssaidi@eecs.umich.educonst char * 10555336Shines@cs.fsu.eduTimingSimpleCPU::IprEvent::description() const 10565103Ssaidi@eecs.umich.edu{ 10575103Ssaidi@eecs.umich.edu return "Timing Simple CPU Delay IPR event"; 10585103Ssaidi@eecs.umich.edu} 10595103Ssaidi@eecs.umich.edu 10602623SN/A 10615315Sstever@gmail.comvoid 10625315Sstever@gmail.comTimingSimpleCPU::printAddr(Addr a) 10635315Sstever@gmail.com{ 10645315Sstever@gmail.com dcachePort.printAddr(a); 10655315Sstever@gmail.com} 10665315Sstever@gmail.com 10675315Sstever@gmail.com 10682623SN/A//////////////////////////////////////////////////////////////////////// 10692623SN/A// 10702623SN/A// TimingSimpleCPU Simulation Object 10712623SN/A// 10724762Snate@binkert.orgTimingSimpleCPU * 10734762Snate@binkert.orgTimingSimpleCPUParams::create() 10742623SN/A{ 10755529Snate@binkert.org numThreads = 1; 10765529Snate@binkert.org#if !FULL_SYSTEM 10774762Snate@binkert.org if (workload.size() != 1) 10784762Snate@binkert.org panic("only one workload allowed"); 10792623SN/A#endif 10805529Snate@binkert.org return new TimingSimpleCPU(this); 10812623SN/A} 1082