timing.cc revision 6739
12623SN/A/* 22623SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 32623SN/A * All rights reserved. 42623SN/A * 52623SN/A * Redistribution and use in source and binary forms, with or without 62623SN/A * modification, are permitted provided that the following conditions are 72623SN/A * met: redistributions of source code must retain the above copyright 82623SN/A * notice, this list of conditions and the following disclaimer; 92623SN/A * redistributions in binary form must reproduce the above copyright 102623SN/A * notice, this list of conditions and the following disclaimer in the 112623SN/A * documentation and/or other materials provided with the distribution; 122623SN/A * neither the name of the copyright holders nor the names of its 132623SN/A * contributors may be used to endorse or promote products derived from 142623SN/A * this software without specific prior written permission. 152623SN/A * 162623SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172623SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182623SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192623SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202623SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212623SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222623SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232623SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242623SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252623SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262623SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 292623SN/A */ 302623SN/A 313170Sstever@eecs.umich.edu#include "arch/locked_mem.hh" 325103Ssaidi@eecs.umich.edu#include "arch/mmaped_ipr.hh" 332623SN/A#include "arch/utility.hh" 344040Ssaidi@eecs.umich.edu#include "base/bigint.hh" 356658Snate@binkert.org#include "config/the_isa.hh" 362623SN/A#include "cpu/exetrace.hh" 372623SN/A#include "cpu/simple/timing.hh" 383348Sbinkertn@umich.edu#include "mem/packet.hh" 393348Sbinkertn@umich.edu#include "mem/packet_access.hh" 404762Snate@binkert.org#include "params/TimingSimpleCPU.hh" 412901Ssaidi@eecs.umich.edu#include "sim/system.hh" 422623SN/A 432623SN/Ausing namespace std; 442623SN/Ausing namespace TheISA; 452623SN/A 462856Srdreslin@umich.eduPort * 472856Srdreslin@umich.eduTimingSimpleCPU::getPort(const std::string &if_name, int idx) 482856Srdreslin@umich.edu{ 492856Srdreslin@umich.edu if (if_name == "dcache_port") 502856Srdreslin@umich.edu return &dcachePort; 512856Srdreslin@umich.edu else if (if_name == "icache_port") 522856Srdreslin@umich.edu return &icachePort; 532856Srdreslin@umich.edu else 542856Srdreslin@umich.edu panic("No Such Port\n"); 552856Srdreslin@umich.edu} 562623SN/A 572623SN/Avoid 582623SN/ATimingSimpleCPU::init() 592623SN/A{ 602623SN/A BaseCPU::init(); 612623SN/A#if FULL_SYSTEM 622680Sktlim@umich.edu for (int i = 0; i < threadContexts.size(); ++i) { 632680Sktlim@umich.edu ThreadContext *tc = threadContexts[i]; 642623SN/A 652623SN/A // initialize CPU, including PC 665712Shsul@eecs.umich.edu TheISA::initCPU(tc, _cpuId); 672623SN/A } 682623SN/A#endif 692623SN/A} 702623SN/A 712623SN/ATick 723349Sbinkertn@umich.eduTimingSimpleCPU::CpuPort::recvAtomic(PacketPtr pkt) 732623SN/A{ 742623SN/A panic("TimingSimpleCPU doesn't expect recvAtomic callback!"); 752623SN/A return curTick; 762623SN/A} 772623SN/A 782623SN/Avoid 793349Sbinkertn@umich.eduTimingSimpleCPU::CpuPort::recvFunctional(PacketPtr pkt) 802623SN/A{ 813184Srdreslin@umich.edu //No internal storage to update, jusst return 823184Srdreslin@umich.edu return; 832623SN/A} 842623SN/A 852623SN/Avoid 862623SN/ATimingSimpleCPU::CpuPort::recvStatusChange(Status status) 872623SN/A{ 883647Srdreslin@umich.edu if (status == RangeChange) { 893647Srdreslin@umich.edu if (!snoopRangeSent) { 903647Srdreslin@umich.edu snoopRangeSent = true; 913647Srdreslin@umich.edu sendStatusChange(Port::RangeChange); 923647Srdreslin@umich.edu } 932631SN/A return; 943647Srdreslin@umich.edu } 952631SN/A 962623SN/A panic("TimingSimpleCPU doesn't expect recvStatusChange callback!"); 972623SN/A} 982623SN/A 992948Ssaidi@eecs.umich.edu 1002948Ssaidi@eecs.umich.eduvoid 1013349Sbinkertn@umich.eduTimingSimpleCPU::CpuPort::TickEvent::schedule(PacketPtr _pkt, Tick t) 1022948Ssaidi@eecs.umich.edu{ 1032948Ssaidi@eecs.umich.edu pkt = _pkt; 1045606Snate@binkert.org cpu->schedule(this, t); 1052948Ssaidi@eecs.umich.edu} 1062948Ssaidi@eecs.umich.edu 1075529Snate@binkert.orgTimingSimpleCPU::TimingSimpleCPU(TimingSimpleCPUParams *p) 1085894Sgblack@eecs.umich.edu : BaseSimpleCPU(p), fetchTranslation(this), icachePort(this, p->clock), 1095894Sgblack@eecs.umich.edu dcachePort(this, p->clock), fetchEvent(this) 1102623SN/A{ 1112623SN/A _status = Idle; 1123647Srdreslin@umich.edu 1133647Srdreslin@umich.edu icachePort.snoopRangeSent = false; 1143647Srdreslin@umich.edu dcachePort.snoopRangeSent = false; 1153647Srdreslin@umich.edu 1162623SN/A ifetch_pkt = dcache_pkt = NULL; 1172839Sktlim@umich.edu drainEvent = NULL; 1183222Sktlim@umich.edu previousTick = 0; 1192901Ssaidi@eecs.umich.edu changeState(SimObject::Running); 1202623SN/A} 1212623SN/A 1222623SN/A 1232623SN/ATimingSimpleCPU::~TimingSimpleCPU() 1242623SN/A{ 1252623SN/A} 1262623SN/A 1272623SN/Avoid 1282623SN/ATimingSimpleCPU::serialize(ostream &os) 1292623SN/A{ 1302915Sktlim@umich.edu SimObject::State so_state = SimObject::getState(); 1312915Sktlim@umich.edu SERIALIZE_ENUM(so_state); 1322623SN/A BaseSimpleCPU::serialize(os); 1332623SN/A} 1342623SN/A 1352623SN/Avoid 1362623SN/ATimingSimpleCPU::unserialize(Checkpoint *cp, const string §ion) 1372623SN/A{ 1382915Sktlim@umich.edu SimObject::State so_state; 1392915Sktlim@umich.edu UNSERIALIZE_ENUM(so_state); 1402623SN/A BaseSimpleCPU::unserialize(cp, section); 1412798Sktlim@umich.edu} 1422798Sktlim@umich.edu 1432901Ssaidi@eecs.umich.eduunsigned int 1442839Sktlim@umich.eduTimingSimpleCPU::drain(Event *drain_event) 1452798Sktlim@umich.edu{ 1462839Sktlim@umich.edu // TimingSimpleCPU is ready to drain if it's not waiting for 1472798Sktlim@umich.edu // an access to complete. 1485496Ssaidi@eecs.umich.edu if (_status == Idle || _status == Running || _status == SwitchedOut) { 1492901Ssaidi@eecs.umich.edu changeState(SimObject::Drained); 1502901Ssaidi@eecs.umich.edu return 0; 1512798Sktlim@umich.edu } else { 1522839Sktlim@umich.edu changeState(SimObject::Draining); 1532839Sktlim@umich.edu drainEvent = drain_event; 1542901Ssaidi@eecs.umich.edu return 1; 1552798Sktlim@umich.edu } 1562623SN/A} 1572623SN/A 1582623SN/Avoid 1592798Sktlim@umich.eduTimingSimpleCPU::resume() 1602623SN/A{ 1615221Ssaidi@eecs.umich.edu DPRINTF(SimpleCPU, "Resume\n"); 1622798Sktlim@umich.edu if (_status != SwitchedOut && _status != Idle) { 1634762Snate@binkert.org assert(system->getMemoryMode() == Enums::timing); 1643201Shsul@eecs.umich.edu 1655710Scws3k@cs.virginia.edu if (fetchEvent.scheduled()) 1665710Scws3k@cs.virginia.edu deschedule(fetchEvent); 1672915Sktlim@umich.edu 1685710Scws3k@cs.virginia.edu schedule(fetchEvent, nextCycle()); 1692623SN/A } 1702798Sktlim@umich.edu 1712901Ssaidi@eecs.umich.edu changeState(SimObject::Running); 1722798Sktlim@umich.edu} 1732798Sktlim@umich.edu 1742798Sktlim@umich.eduvoid 1752798Sktlim@umich.eduTimingSimpleCPU::switchOut() 1762798Sktlim@umich.edu{ 1775496Ssaidi@eecs.umich.edu assert(_status == Running || _status == Idle); 1782798Sktlim@umich.edu _status = SwitchedOut; 1795099Ssaidi@eecs.umich.edu numCycles += tickToCycles(curTick - previousTick); 1802867Sktlim@umich.edu 1812867Sktlim@umich.edu // If we've been scheduled to resume but are then told to switch out, 1822867Sktlim@umich.edu // we'll need to cancel it. 1835710Scws3k@cs.virginia.edu if (fetchEvent.scheduled()) 1845606Snate@binkert.org deschedule(fetchEvent); 1852623SN/A} 1862623SN/A 1872623SN/A 1882623SN/Avoid 1892623SN/ATimingSimpleCPU::takeOverFrom(BaseCPU *oldCPU) 1902623SN/A{ 1914192Sktlim@umich.edu BaseCPU::takeOverFrom(oldCPU, &icachePort, &dcachePort); 1922623SN/A 1932680Sktlim@umich.edu // if any of this CPU's ThreadContexts are active, mark the CPU as 1942623SN/A // running and schedule its tick event. 1952680Sktlim@umich.edu for (int i = 0; i < threadContexts.size(); ++i) { 1962680Sktlim@umich.edu ThreadContext *tc = threadContexts[i]; 1972680Sktlim@umich.edu if (tc->status() == ThreadContext::Active && _status != Running) { 1982623SN/A _status = Running; 1992623SN/A break; 2002623SN/A } 2012623SN/A } 2023201Shsul@eecs.umich.edu 2033201Shsul@eecs.umich.edu if (_status != Running) { 2043201Shsul@eecs.umich.edu _status = Idle; 2053201Shsul@eecs.umich.edu } 2065169Ssaidi@eecs.umich.edu assert(threadContexts.size() == 1); 2075101Ssaidi@eecs.umich.edu previousTick = curTick; 2082623SN/A} 2092623SN/A 2102623SN/A 2112623SN/Avoid 2122623SN/ATimingSimpleCPU::activateContext(int thread_num, int delay) 2132623SN/A{ 2145221Ssaidi@eecs.umich.edu DPRINTF(SimpleCPU, "ActivateContext %d (%d cycles)\n", thread_num, delay); 2155221Ssaidi@eecs.umich.edu 2162623SN/A assert(thread_num == 0); 2172683Sktlim@umich.edu assert(thread); 2182623SN/A 2192623SN/A assert(_status == Idle); 2202623SN/A 2212623SN/A notIdleFraction++; 2222623SN/A _status = Running; 2233686Sktlim@umich.edu 2242623SN/A // kick things off by initiating the fetch of the next instruction 2255606Snate@binkert.org schedule(fetchEvent, nextCycle(curTick + ticks(delay))); 2262623SN/A} 2272623SN/A 2282623SN/A 2292623SN/Avoid 2302623SN/ATimingSimpleCPU::suspendContext(int thread_num) 2312623SN/A{ 2325221Ssaidi@eecs.umich.edu DPRINTF(SimpleCPU, "SuspendContext %d\n", thread_num); 2335221Ssaidi@eecs.umich.edu 2342623SN/A assert(thread_num == 0); 2352683Sktlim@umich.edu assert(thread); 2362623SN/A 2376043Sgblack@eecs.umich.edu if (_status == Idle) 2386043Sgblack@eecs.umich.edu return; 2396043Sgblack@eecs.umich.edu 2402644Sstever@eecs.umich.edu assert(_status == Running); 2412623SN/A 2422644Sstever@eecs.umich.edu // just change status to Idle... if status != Running, 2432644Sstever@eecs.umich.edu // completeInst() will not initiate fetch of next instruction. 2442623SN/A 2452623SN/A notIdleFraction--; 2462623SN/A _status = Idle; 2472623SN/A} 2482623SN/A 2495728Sgblack@eecs.umich.edubool 2505728Sgblack@eecs.umich.eduTimingSimpleCPU::handleReadPacket(PacketPtr pkt) 2515728Sgblack@eecs.umich.edu{ 2525728Sgblack@eecs.umich.edu RequestPtr req = pkt->req; 2535728Sgblack@eecs.umich.edu if (req->isMmapedIpr()) { 2545728Sgblack@eecs.umich.edu Tick delay; 2555728Sgblack@eecs.umich.edu delay = TheISA::handleIprRead(thread->getTC(), pkt); 2565728Sgblack@eecs.umich.edu new IprEvent(pkt, this, nextCycle(curTick + delay)); 2575728Sgblack@eecs.umich.edu _status = DcacheWaitResponse; 2585728Sgblack@eecs.umich.edu dcache_pkt = NULL; 2595728Sgblack@eecs.umich.edu } else if (!dcachePort.sendTiming(pkt)) { 2605728Sgblack@eecs.umich.edu _status = DcacheRetry; 2615728Sgblack@eecs.umich.edu dcache_pkt = pkt; 2625728Sgblack@eecs.umich.edu } else { 2635728Sgblack@eecs.umich.edu _status = DcacheWaitResponse; 2645728Sgblack@eecs.umich.edu // memory system takes ownership of packet 2655728Sgblack@eecs.umich.edu dcache_pkt = NULL; 2665728Sgblack@eecs.umich.edu } 2675728Sgblack@eecs.umich.edu return dcache_pkt == NULL; 2685728Sgblack@eecs.umich.edu} 2692623SN/A 2705894Sgblack@eecs.umich.eduvoid 2715894Sgblack@eecs.umich.eduTimingSimpleCPU::sendData(Fault fault, RequestPtr req, 2725894Sgblack@eecs.umich.edu uint8_t *data, uint64_t *res, bool read) 2735744Sgblack@eecs.umich.edu{ 2745894Sgblack@eecs.umich.edu _status = Running; 2755894Sgblack@eecs.umich.edu if (fault != NoFault) { 2766739Sgblack@eecs.umich.edu if (req->isPrefetch()) 2776739Sgblack@eecs.umich.edu fault = NoFault; 2785894Sgblack@eecs.umich.edu delete data; 2795894Sgblack@eecs.umich.edu delete req; 2805744Sgblack@eecs.umich.edu 2815894Sgblack@eecs.umich.edu translationFault(fault); 2825894Sgblack@eecs.umich.edu return; 2835894Sgblack@eecs.umich.edu } 2845894Sgblack@eecs.umich.edu PacketPtr pkt; 2855894Sgblack@eecs.umich.edu buildPacket(pkt, req, read); 2865894Sgblack@eecs.umich.edu pkt->dataDynamic<uint8_t>(data); 2875894Sgblack@eecs.umich.edu if (req->getFlags().isSet(Request::NO_ACCESS)) { 2885894Sgblack@eecs.umich.edu assert(!dcache_pkt); 2895894Sgblack@eecs.umich.edu pkt->makeResponse(); 2905894Sgblack@eecs.umich.edu completeDataAccess(pkt); 2915894Sgblack@eecs.umich.edu } else if (read) { 2925894Sgblack@eecs.umich.edu handleReadPacket(pkt); 2935894Sgblack@eecs.umich.edu } else { 2945894Sgblack@eecs.umich.edu bool do_access = true; // flag to suppress cache access 2955894Sgblack@eecs.umich.edu 2966102Sgblack@eecs.umich.edu if (req->isLLSC()) { 2975894Sgblack@eecs.umich.edu do_access = TheISA::handleLockedWrite(thread, req); 2985894Sgblack@eecs.umich.edu } else if (req->isCondSwap()) { 2995894Sgblack@eecs.umich.edu assert(res); 3005894Sgblack@eecs.umich.edu req->setExtraData(*res); 3015894Sgblack@eecs.umich.edu } 3025894Sgblack@eecs.umich.edu 3035894Sgblack@eecs.umich.edu if (do_access) { 3045894Sgblack@eecs.umich.edu dcache_pkt = pkt; 3055894Sgblack@eecs.umich.edu handleWritePacket(); 3065894Sgblack@eecs.umich.edu } else { 3075894Sgblack@eecs.umich.edu _status = DcacheWaitResponse; 3085894Sgblack@eecs.umich.edu completeDataAccess(pkt); 3095894Sgblack@eecs.umich.edu } 3105894Sgblack@eecs.umich.edu } 3115894Sgblack@eecs.umich.edu} 3125894Sgblack@eecs.umich.edu 3135894Sgblack@eecs.umich.eduvoid 3145894Sgblack@eecs.umich.eduTimingSimpleCPU::sendSplitData(Fault fault1, Fault fault2, 3155894Sgblack@eecs.umich.edu RequestPtr req1, RequestPtr req2, RequestPtr req, 3165894Sgblack@eecs.umich.edu uint8_t *data, bool read) 3175894Sgblack@eecs.umich.edu{ 3185894Sgblack@eecs.umich.edu _status = Running; 3195894Sgblack@eecs.umich.edu if (fault1 != NoFault || fault2 != NoFault) { 3206739Sgblack@eecs.umich.edu if (req1->isPrefetch()) 3216739Sgblack@eecs.umich.edu fault1 = NoFault; 3226739Sgblack@eecs.umich.edu if (req2->isPrefetch()) 3236739Sgblack@eecs.umich.edu fault2 = NoFault; 3245894Sgblack@eecs.umich.edu delete data; 3255890Sgblack@eecs.umich.edu delete req1; 3265894Sgblack@eecs.umich.edu delete req2; 3275894Sgblack@eecs.umich.edu if (fault1 != NoFault) 3285894Sgblack@eecs.umich.edu translationFault(fault1); 3295894Sgblack@eecs.umich.edu else if (fault2 != NoFault) 3305894Sgblack@eecs.umich.edu translationFault(fault2); 3315894Sgblack@eecs.umich.edu return; 3325894Sgblack@eecs.umich.edu } 3335894Sgblack@eecs.umich.edu PacketPtr pkt1, pkt2; 3345894Sgblack@eecs.umich.edu buildSplitPacket(pkt1, pkt2, req1, req2, req, data, read); 3355894Sgblack@eecs.umich.edu if (req->getFlags().isSet(Request::NO_ACCESS)) { 3365894Sgblack@eecs.umich.edu assert(!dcache_pkt); 3375894Sgblack@eecs.umich.edu pkt1->makeResponse(); 3385894Sgblack@eecs.umich.edu completeDataAccess(pkt1); 3395894Sgblack@eecs.umich.edu } else if (read) { 3405894Sgblack@eecs.umich.edu if (handleReadPacket(pkt1)) { 3415894Sgblack@eecs.umich.edu SplitFragmentSenderState * send_state = 3425894Sgblack@eecs.umich.edu dynamic_cast<SplitFragmentSenderState *>(pkt1->senderState); 3435894Sgblack@eecs.umich.edu send_state->clearFromParent(); 3445894Sgblack@eecs.umich.edu if (handleReadPacket(pkt2)) { 3455894Sgblack@eecs.umich.edu send_state = dynamic_cast<SplitFragmentSenderState *>( 3465894Sgblack@eecs.umich.edu pkt1->senderState); 3475894Sgblack@eecs.umich.edu send_state->clearFromParent(); 3485894Sgblack@eecs.umich.edu } 3495894Sgblack@eecs.umich.edu } 3505894Sgblack@eecs.umich.edu } else { 3515894Sgblack@eecs.umich.edu dcache_pkt = pkt1; 3525894Sgblack@eecs.umich.edu if (handleWritePacket()) { 3535894Sgblack@eecs.umich.edu SplitFragmentSenderState * send_state = 3545894Sgblack@eecs.umich.edu dynamic_cast<SplitFragmentSenderState *>(pkt1->senderState); 3555894Sgblack@eecs.umich.edu send_state->clearFromParent(); 3565894Sgblack@eecs.umich.edu dcache_pkt = pkt2; 3575894Sgblack@eecs.umich.edu if (handleWritePacket()) { 3585894Sgblack@eecs.umich.edu send_state = dynamic_cast<SplitFragmentSenderState *>( 3595894Sgblack@eecs.umich.edu pkt1->senderState); 3605894Sgblack@eecs.umich.edu send_state->clearFromParent(); 3615894Sgblack@eecs.umich.edu } 3625894Sgblack@eecs.umich.edu } 3635894Sgblack@eecs.umich.edu } 3645894Sgblack@eecs.umich.edu} 3655894Sgblack@eecs.umich.edu 3665894Sgblack@eecs.umich.eduvoid 3675894Sgblack@eecs.umich.eduTimingSimpleCPU::translationFault(Fault fault) 3685894Sgblack@eecs.umich.edu{ 3696739Sgblack@eecs.umich.edu // fault may be NoFault in cases where a fault is suppressed, 3706739Sgblack@eecs.umich.edu // for instance prefetches. 3715894Sgblack@eecs.umich.edu numCycles += tickToCycles(curTick - previousTick); 3725894Sgblack@eecs.umich.edu previousTick = curTick; 3735894Sgblack@eecs.umich.edu 3745894Sgblack@eecs.umich.edu if (traceData) { 3755894Sgblack@eecs.umich.edu // Since there was a fault, we shouldn't trace this instruction. 3765894Sgblack@eecs.umich.edu delete traceData; 3775894Sgblack@eecs.umich.edu traceData = NULL; 3785744Sgblack@eecs.umich.edu } 3795744Sgblack@eecs.umich.edu 3805894Sgblack@eecs.umich.edu postExecute(); 3815894Sgblack@eecs.umich.edu 3825894Sgblack@eecs.umich.edu if (getState() == SimObject::Draining) { 3835894Sgblack@eecs.umich.edu advancePC(fault); 3845894Sgblack@eecs.umich.edu completeDrain(); 3855894Sgblack@eecs.umich.edu } else { 3865894Sgblack@eecs.umich.edu advanceInst(fault); 3875894Sgblack@eecs.umich.edu } 3885894Sgblack@eecs.umich.edu} 3895894Sgblack@eecs.umich.edu 3905894Sgblack@eecs.umich.eduvoid 3915894Sgblack@eecs.umich.eduTimingSimpleCPU::buildPacket(PacketPtr &pkt, RequestPtr req, bool read) 3925894Sgblack@eecs.umich.edu{ 3935894Sgblack@eecs.umich.edu MemCmd cmd; 3945894Sgblack@eecs.umich.edu if (read) { 3955894Sgblack@eecs.umich.edu cmd = MemCmd::ReadReq; 3966102Sgblack@eecs.umich.edu if (req->isLLSC()) 3975894Sgblack@eecs.umich.edu cmd = MemCmd::LoadLockedReq; 3985894Sgblack@eecs.umich.edu } else { 3995894Sgblack@eecs.umich.edu cmd = MemCmd::WriteReq; 4006102Sgblack@eecs.umich.edu if (req->isLLSC()) { 4015894Sgblack@eecs.umich.edu cmd = MemCmd::StoreCondReq; 4025894Sgblack@eecs.umich.edu } else if (req->isSwap()) { 4035894Sgblack@eecs.umich.edu cmd = MemCmd::SwapReq; 4045894Sgblack@eecs.umich.edu } 4055894Sgblack@eecs.umich.edu } 4065894Sgblack@eecs.umich.edu pkt = new Packet(req, cmd, Packet::Broadcast); 4075894Sgblack@eecs.umich.edu} 4085894Sgblack@eecs.umich.edu 4095894Sgblack@eecs.umich.eduvoid 4105894Sgblack@eecs.umich.eduTimingSimpleCPU::buildSplitPacket(PacketPtr &pkt1, PacketPtr &pkt2, 4115894Sgblack@eecs.umich.edu RequestPtr req1, RequestPtr req2, RequestPtr req, 4125894Sgblack@eecs.umich.edu uint8_t *data, bool read) 4135894Sgblack@eecs.umich.edu{ 4145894Sgblack@eecs.umich.edu pkt1 = pkt2 = NULL; 4155894Sgblack@eecs.umich.edu 4165744Sgblack@eecs.umich.edu assert(!req1->isMmapedIpr() && !req2->isMmapedIpr()); 4175744Sgblack@eecs.umich.edu 4185894Sgblack@eecs.umich.edu if (req->getFlags().isSet(Request::NO_ACCESS)) { 4195894Sgblack@eecs.umich.edu buildPacket(pkt1, req, read); 4205894Sgblack@eecs.umich.edu return; 4215894Sgblack@eecs.umich.edu } 4225894Sgblack@eecs.umich.edu 4235894Sgblack@eecs.umich.edu buildPacket(pkt1, req1, read); 4245894Sgblack@eecs.umich.edu buildPacket(pkt2, req2, read); 4255894Sgblack@eecs.umich.edu 4265744Sgblack@eecs.umich.edu req->setPhys(req1->getPaddr(), req->getSize(), req1->getFlags()); 4275744Sgblack@eecs.umich.edu PacketPtr pkt = new Packet(req, pkt1->cmd.responseCommand(), 4285744Sgblack@eecs.umich.edu Packet::Broadcast); 4295744Sgblack@eecs.umich.edu 4305744Sgblack@eecs.umich.edu pkt->dataDynamic<uint8_t>(data); 4315744Sgblack@eecs.umich.edu pkt1->dataStatic<uint8_t>(data); 4325744Sgblack@eecs.umich.edu pkt2->dataStatic<uint8_t>(data + req1->getSize()); 4335744Sgblack@eecs.umich.edu 4345744Sgblack@eecs.umich.edu SplitMainSenderState * main_send_state = new SplitMainSenderState; 4355744Sgblack@eecs.umich.edu pkt->senderState = main_send_state; 4365744Sgblack@eecs.umich.edu main_send_state->fragments[0] = pkt1; 4375744Sgblack@eecs.umich.edu main_send_state->fragments[1] = pkt2; 4385744Sgblack@eecs.umich.edu main_send_state->outstanding = 2; 4395744Sgblack@eecs.umich.edu pkt1->senderState = new SplitFragmentSenderState(pkt, 0); 4405744Sgblack@eecs.umich.edu pkt2->senderState = new SplitFragmentSenderState(pkt, 1); 4415744Sgblack@eecs.umich.edu} 4425744Sgblack@eecs.umich.edu 4432623SN/Atemplate <class T> 4442623SN/AFault 4452623SN/ATimingSimpleCPU::read(Addr addr, T &data, unsigned flags) 4462623SN/A{ 4475728Sgblack@eecs.umich.edu Fault fault; 4485728Sgblack@eecs.umich.edu const int asid = 0; 4496221Snate@binkert.org const ThreadID tid = 0; 4505728Sgblack@eecs.umich.edu const Addr pc = thread->readPC(); 4516227Snate@binkert.org unsigned block_size = dcachePort.peerBlockSize(); 4525728Sgblack@eecs.umich.edu int data_size = sizeof(T); 4532623SN/A 4545744Sgblack@eecs.umich.edu RequestPtr req = new Request(asid, addr, data_size, 4556221Snate@binkert.org flags, pc, _cpuId, tid); 4565728Sgblack@eecs.umich.edu 4575744Sgblack@eecs.umich.edu Addr split_addr = roundDown(addr + data_size - 1, block_size); 4585744Sgblack@eecs.umich.edu assert(split_addr <= addr || split_addr - addr < block_size); 4595728Sgblack@eecs.umich.edu 4605894Sgblack@eecs.umich.edu 4615894Sgblack@eecs.umich.edu _status = DTBWaitResponse; 4625744Sgblack@eecs.umich.edu if (split_addr > addr) { 4635894Sgblack@eecs.umich.edu RequestPtr req1, req2; 4646102Sgblack@eecs.umich.edu assert(!req->isLLSC() && !req->isSwap()); 4655894Sgblack@eecs.umich.edu req->splitOnVaddr(split_addr, req1, req2); 4665894Sgblack@eecs.umich.edu 4675894Sgblack@eecs.umich.edu typedef SplitDataTranslation::WholeTranslationState WholeState; 4685894Sgblack@eecs.umich.edu WholeState *state = new WholeState(req1, req2, req, 4696023Snate@binkert.org (uint8_t *)(new T), BaseTLB::Read); 4705894Sgblack@eecs.umich.edu thread->dtb->translateTiming(req1, tc, 4716023Snate@binkert.org new SplitDataTranslation(this, 0, state), BaseTLB::Read); 4725894Sgblack@eecs.umich.edu thread->dtb->translateTiming(req2, tc, 4736023Snate@binkert.org new SplitDataTranslation(this, 1, state), BaseTLB::Read); 4745744Sgblack@eecs.umich.edu } else { 4756023Snate@binkert.org DataTranslation *translation = 4766023Snate@binkert.org new DataTranslation(this, (uint8_t *)(new T), NULL, BaseTLB::Read); 4776023Snate@binkert.org thread->dtb->translateTiming(req, tc, translation, BaseTLB::Read); 4782623SN/A } 4792623SN/A 4805408Sgblack@eecs.umich.edu if (traceData) { 4815408Sgblack@eecs.umich.edu traceData->setData(data); 4825728Sgblack@eecs.umich.edu traceData->setAddr(addr); 4835408Sgblack@eecs.umich.edu } 4845728Sgblack@eecs.umich.edu 4855728Sgblack@eecs.umich.edu // This will need a new way to tell if it has a dcache attached. 4865728Sgblack@eecs.umich.edu if (req->isUncacheable()) 4875728Sgblack@eecs.umich.edu recordEvent("Uncached Read"); 4885728Sgblack@eecs.umich.edu 4895728Sgblack@eecs.umich.edu return NoFault; 4902623SN/A} 4912623SN/A 4922623SN/A#ifndef DOXYGEN_SHOULD_SKIP_THIS 4932623SN/A 4942623SN/Atemplate 4952623SN/AFault 4964040Ssaidi@eecs.umich.eduTimingSimpleCPU::read(Addr addr, Twin64_t &data, unsigned flags); 4974040Ssaidi@eecs.umich.edu 4984040Ssaidi@eecs.umich.edutemplate 4994040Ssaidi@eecs.umich.eduFault 5004115Ssaidi@eecs.umich.eduTimingSimpleCPU::read(Addr addr, Twin32_t &data, unsigned flags); 5014115Ssaidi@eecs.umich.edu 5024115Ssaidi@eecs.umich.edutemplate 5034115Ssaidi@eecs.umich.eduFault 5042623SN/ATimingSimpleCPU::read(Addr addr, uint64_t &data, unsigned flags); 5052623SN/A 5062623SN/Atemplate 5072623SN/AFault 5082623SN/ATimingSimpleCPU::read(Addr addr, uint32_t &data, unsigned flags); 5092623SN/A 5102623SN/Atemplate 5112623SN/AFault 5122623SN/ATimingSimpleCPU::read(Addr addr, uint16_t &data, unsigned flags); 5132623SN/A 5142623SN/Atemplate 5152623SN/AFault 5162623SN/ATimingSimpleCPU::read(Addr addr, uint8_t &data, unsigned flags); 5172623SN/A 5182623SN/A#endif //DOXYGEN_SHOULD_SKIP_THIS 5192623SN/A 5202623SN/Atemplate<> 5212623SN/AFault 5222623SN/ATimingSimpleCPU::read(Addr addr, double &data, unsigned flags) 5232623SN/A{ 5242623SN/A return read(addr, *(uint64_t*)&data, flags); 5252623SN/A} 5262623SN/A 5272623SN/Atemplate<> 5282623SN/AFault 5292623SN/ATimingSimpleCPU::read(Addr addr, float &data, unsigned flags) 5302623SN/A{ 5312623SN/A return read(addr, *(uint32_t*)&data, flags); 5322623SN/A} 5332623SN/A 5342623SN/A 5352623SN/Atemplate<> 5362623SN/AFault 5372623SN/ATimingSimpleCPU::read(Addr addr, int32_t &data, unsigned flags) 5382623SN/A{ 5392623SN/A return read(addr, (uint32_t&)data, flags); 5402623SN/A} 5412623SN/A 5425728Sgblack@eecs.umich.edubool 5435728Sgblack@eecs.umich.eduTimingSimpleCPU::handleWritePacket() 5445728Sgblack@eecs.umich.edu{ 5455728Sgblack@eecs.umich.edu RequestPtr req = dcache_pkt->req; 5465728Sgblack@eecs.umich.edu if (req->isMmapedIpr()) { 5475728Sgblack@eecs.umich.edu Tick delay; 5485728Sgblack@eecs.umich.edu delay = TheISA::handleIprWrite(thread->getTC(), dcache_pkt); 5495728Sgblack@eecs.umich.edu new IprEvent(dcache_pkt, this, nextCycle(curTick + delay)); 5505728Sgblack@eecs.umich.edu _status = DcacheWaitResponse; 5515728Sgblack@eecs.umich.edu dcache_pkt = NULL; 5525728Sgblack@eecs.umich.edu } else if (!dcachePort.sendTiming(dcache_pkt)) { 5535728Sgblack@eecs.umich.edu _status = DcacheRetry; 5545728Sgblack@eecs.umich.edu } else { 5555728Sgblack@eecs.umich.edu _status = DcacheWaitResponse; 5565728Sgblack@eecs.umich.edu // memory system takes ownership of packet 5575728Sgblack@eecs.umich.edu dcache_pkt = NULL; 5585728Sgblack@eecs.umich.edu } 5595728Sgblack@eecs.umich.edu return dcache_pkt == NULL; 5605728Sgblack@eecs.umich.edu} 5612623SN/A 5622623SN/Atemplate <class T> 5632623SN/AFault 5642623SN/ATimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res) 5652623SN/A{ 5665728Sgblack@eecs.umich.edu const int asid = 0; 5676221Snate@binkert.org const ThreadID tid = 0; 5685728Sgblack@eecs.umich.edu const Addr pc = thread->readPC(); 5696227Snate@binkert.org unsigned block_size = dcachePort.peerBlockSize(); 5705728Sgblack@eecs.umich.edu int data_size = sizeof(T); 5713169Sstever@eecs.umich.edu 5725744Sgblack@eecs.umich.edu RequestPtr req = new Request(asid, addr, data_size, 5736221Snate@binkert.org flags, pc, _cpuId, tid); 5745728Sgblack@eecs.umich.edu 5755744Sgblack@eecs.umich.edu Addr split_addr = roundDown(addr + data_size - 1, block_size); 5765744Sgblack@eecs.umich.edu assert(split_addr <= addr || split_addr - addr < block_size); 5775728Sgblack@eecs.umich.edu 5785894Sgblack@eecs.umich.edu T *dataP = new T; 5796012Ssteve.reinhardt@amd.com *dataP = TheISA::htog(data); 5805894Sgblack@eecs.umich.edu _status = DTBWaitResponse; 5815744Sgblack@eecs.umich.edu if (split_addr > addr) { 5825894Sgblack@eecs.umich.edu RequestPtr req1, req2; 5836102Sgblack@eecs.umich.edu assert(!req->isLLSC() && !req->isSwap()); 5845894Sgblack@eecs.umich.edu req->splitOnVaddr(split_addr, req1, req2); 5855894Sgblack@eecs.umich.edu 5865894Sgblack@eecs.umich.edu typedef SplitDataTranslation::WholeTranslationState WholeState; 5875894Sgblack@eecs.umich.edu WholeState *state = new WholeState(req1, req2, req, 5886023Snate@binkert.org (uint8_t *)dataP, BaseTLB::Write); 5895894Sgblack@eecs.umich.edu thread->dtb->translateTiming(req1, tc, 5906023Snate@binkert.org new SplitDataTranslation(this, 0, state), BaseTLB::Write); 5915894Sgblack@eecs.umich.edu thread->dtb->translateTiming(req2, tc, 5926023Snate@binkert.org new SplitDataTranslation(this, 1, state), BaseTLB::Write); 5935744Sgblack@eecs.umich.edu } else { 5946023Snate@binkert.org DataTranslation *translation = 5956023Snate@binkert.org new DataTranslation(this, (uint8_t *)dataP, res, BaseTLB::Write); 5966023Snate@binkert.org thread->dtb->translateTiming(req, tc, translation, BaseTLB::Write); 5972623SN/A } 5982623SN/A 5995408Sgblack@eecs.umich.edu if (traceData) { 6005728Sgblack@eecs.umich.edu traceData->setAddr(req->getVaddr()); 6015408Sgblack@eecs.umich.edu traceData->setData(data); 6025408Sgblack@eecs.umich.edu } 6032623SN/A 6045728Sgblack@eecs.umich.edu // This will need a new way to tell if it's hooked up to a cache or not. 6055728Sgblack@eecs.umich.edu if (req->isUncacheable()) 6065728Sgblack@eecs.umich.edu recordEvent("Uncached Write"); 6075728Sgblack@eecs.umich.edu 6082623SN/A // If the write needs to have a fault on the access, consider calling 6092623SN/A // changeStatus() and changing it to "bad addr write" or something. 6105728Sgblack@eecs.umich.edu return NoFault; 6112623SN/A} 6122623SN/A 6132623SN/A 6142623SN/A#ifndef DOXYGEN_SHOULD_SKIP_THIS 6152623SN/Atemplate 6162623SN/AFault 6174224Sgblack@eecs.umich.eduTimingSimpleCPU::write(Twin32_t data, Addr addr, 6184224Sgblack@eecs.umich.edu unsigned flags, uint64_t *res); 6194224Sgblack@eecs.umich.edu 6204224Sgblack@eecs.umich.edutemplate 6214224Sgblack@eecs.umich.eduFault 6224224Sgblack@eecs.umich.eduTimingSimpleCPU::write(Twin64_t data, Addr addr, 6234224Sgblack@eecs.umich.edu unsigned flags, uint64_t *res); 6244224Sgblack@eecs.umich.edu 6254224Sgblack@eecs.umich.edutemplate 6264224Sgblack@eecs.umich.eduFault 6272623SN/ATimingSimpleCPU::write(uint64_t data, Addr addr, 6282623SN/A unsigned flags, uint64_t *res); 6292623SN/A 6302623SN/Atemplate 6312623SN/AFault 6322623SN/ATimingSimpleCPU::write(uint32_t data, Addr addr, 6332623SN/A unsigned flags, uint64_t *res); 6342623SN/A 6352623SN/Atemplate 6362623SN/AFault 6372623SN/ATimingSimpleCPU::write(uint16_t data, Addr addr, 6382623SN/A unsigned flags, uint64_t *res); 6392623SN/A 6402623SN/Atemplate 6412623SN/AFault 6422623SN/ATimingSimpleCPU::write(uint8_t data, Addr addr, 6432623SN/A unsigned flags, uint64_t *res); 6442623SN/A 6452623SN/A#endif //DOXYGEN_SHOULD_SKIP_THIS 6462623SN/A 6472623SN/Atemplate<> 6482623SN/AFault 6492623SN/ATimingSimpleCPU::write(double data, Addr addr, unsigned flags, uint64_t *res) 6502623SN/A{ 6512623SN/A return write(*(uint64_t*)&data, addr, flags, res); 6522623SN/A} 6532623SN/A 6542623SN/Atemplate<> 6552623SN/AFault 6562623SN/ATimingSimpleCPU::write(float data, Addr addr, unsigned flags, uint64_t *res) 6572623SN/A{ 6582623SN/A return write(*(uint32_t*)&data, addr, flags, res); 6592623SN/A} 6602623SN/A 6612623SN/A 6622623SN/Atemplate<> 6632623SN/AFault 6642623SN/ATimingSimpleCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res) 6652623SN/A{ 6662623SN/A return write((uint32_t)data, addr, flags, res); 6672623SN/A} 6682623SN/A 6692623SN/A 6702623SN/Avoid 6712623SN/ATimingSimpleCPU::fetch() 6722623SN/A{ 6735221Ssaidi@eecs.umich.edu DPRINTF(SimpleCPU, "Fetch\n"); 6745221Ssaidi@eecs.umich.edu 6753387Sgblack@eecs.umich.edu if (!curStaticInst || !curStaticInst->isDelayedCommit()) 6763387Sgblack@eecs.umich.edu checkForInterrupts(); 6772631SN/A 6785348Ssaidi@eecs.umich.edu checkPcEventQueue(); 6795348Ssaidi@eecs.umich.edu 6805669Sgblack@eecs.umich.edu bool fromRom = isRomMicroPC(thread->readMicroPC()); 6812623SN/A 6825914Sgblack@eecs.umich.edu if (!fromRom && !curMacroStaticInst) { 6835669Sgblack@eecs.umich.edu Request *ifetch_req = new Request(); 6845712Shsul@eecs.umich.edu ifetch_req->setThreadContext(_cpuId, /* thread ID */ 0); 6855894Sgblack@eecs.umich.edu setupFetchRequest(ifetch_req); 6866023Snate@binkert.org thread->itb->translateTiming(ifetch_req, tc, &fetchTranslation, 6876023Snate@binkert.org BaseTLB::Execute); 6882623SN/A } else { 6895669Sgblack@eecs.umich.edu _status = IcacheWaitResponse; 6905669Sgblack@eecs.umich.edu completeIfetch(NULL); 6915894Sgblack@eecs.umich.edu 6925894Sgblack@eecs.umich.edu numCycles += tickToCycles(curTick - previousTick); 6935894Sgblack@eecs.umich.edu previousTick = curTick; 6945894Sgblack@eecs.umich.edu } 6955894Sgblack@eecs.umich.edu} 6965894Sgblack@eecs.umich.edu 6975894Sgblack@eecs.umich.edu 6985894Sgblack@eecs.umich.eduvoid 6995894Sgblack@eecs.umich.eduTimingSimpleCPU::sendFetch(Fault fault, RequestPtr req, ThreadContext *tc) 7005894Sgblack@eecs.umich.edu{ 7015894Sgblack@eecs.umich.edu if (fault == NoFault) { 7025894Sgblack@eecs.umich.edu ifetch_pkt = new Packet(req, MemCmd::ReadReq, Packet::Broadcast); 7035894Sgblack@eecs.umich.edu ifetch_pkt->dataStatic(&inst); 7045894Sgblack@eecs.umich.edu 7055894Sgblack@eecs.umich.edu if (!icachePort.sendTiming(ifetch_pkt)) { 7065894Sgblack@eecs.umich.edu // Need to wait for retry 7075894Sgblack@eecs.umich.edu _status = IcacheRetry; 7085894Sgblack@eecs.umich.edu } else { 7095894Sgblack@eecs.umich.edu // Need to wait for cache to respond 7105894Sgblack@eecs.umich.edu _status = IcacheWaitResponse; 7115894Sgblack@eecs.umich.edu // ownership of packet transferred to memory system 7125894Sgblack@eecs.umich.edu ifetch_pkt = NULL; 7135894Sgblack@eecs.umich.edu } 7145894Sgblack@eecs.umich.edu } else { 7155894Sgblack@eecs.umich.edu delete req; 7165894Sgblack@eecs.umich.edu // fetch fault: advance directly to next instruction (fault handler) 7175894Sgblack@eecs.umich.edu advanceInst(fault); 7182623SN/A } 7193222Sktlim@umich.edu 7205099Ssaidi@eecs.umich.edu numCycles += tickToCycles(curTick - previousTick); 7213222Sktlim@umich.edu previousTick = curTick; 7222623SN/A} 7232623SN/A 7242623SN/A 7252623SN/Avoid 7262644Sstever@eecs.umich.eduTimingSimpleCPU::advanceInst(Fault fault) 7272623SN/A{ 7285726Sgblack@eecs.umich.edu if (fault != NoFault || !stayAtPC) 7295726Sgblack@eecs.umich.edu advancePC(fault); 7302623SN/A 7312631SN/A if (_status == Running) { 7322631SN/A // kick off fetch of next instruction... callback from icache 7332631SN/A // response will cause that instruction to be executed, 7342631SN/A // keeping the CPU running. 7352631SN/A fetch(); 7362631SN/A } 7372623SN/A} 7382623SN/A 7392623SN/A 7402623SN/Avoid 7413349Sbinkertn@umich.eduTimingSimpleCPU::completeIfetch(PacketPtr pkt) 7422623SN/A{ 7435221Ssaidi@eecs.umich.edu DPRINTF(SimpleCPU, "Complete ICache Fetch\n"); 7445221Ssaidi@eecs.umich.edu 7452623SN/A // received a response from the icache: execute the received 7462623SN/A // instruction 7475669Sgblack@eecs.umich.edu 7485669Sgblack@eecs.umich.edu assert(!pkt || !pkt->isError()); 7492623SN/A assert(_status == IcacheWaitResponse); 7502798Sktlim@umich.edu 7512623SN/A _status = Running; 7522644Sstever@eecs.umich.edu 7535099Ssaidi@eecs.umich.edu numCycles += tickToCycles(curTick - previousTick); 7543222Sktlim@umich.edu previousTick = curTick; 7553222Sktlim@umich.edu 7562839Sktlim@umich.edu if (getState() == SimObject::Draining) { 7575669Sgblack@eecs.umich.edu if (pkt) { 7585669Sgblack@eecs.umich.edu delete pkt->req; 7595669Sgblack@eecs.umich.edu delete pkt; 7605669Sgblack@eecs.umich.edu } 7613658Sktlim@umich.edu 7622839Sktlim@umich.edu completeDrain(); 7632798Sktlim@umich.edu return; 7642798Sktlim@umich.edu } 7652798Sktlim@umich.edu 7662623SN/A preExecute(); 7675726Sgblack@eecs.umich.edu if (curStaticInst && 7685726Sgblack@eecs.umich.edu curStaticInst->isMemRef() && !curStaticInst->isDataPrefetch()) { 7692623SN/A // load or store: just send to dcache 7702623SN/A Fault fault = curStaticInst->initiateAcc(this, traceData); 7713170Sstever@eecs.umich.edu if (_status != Running) { 7723170Sstever@eecs.umich.edu // instruction will complete in dcache response callback 7735894Sgblack@eecs.umich.edu assert(_status == DcacheWaitResponse || 7745894Sgblack@eecs.umich.edu _status == DcacheRetry || DTBWaitResponse); 7753170Sstever@eecs.umich.edu assert(fault == NoFault); 7762644Sstever@eecs.umich.edu } else { 7775894Sgblack@eecs.umich.edu if (fault != NoFault && traceData) { 7785001Sgblack@eecs.umich.edu // If there was a fault, we shouldn't trace this instruction. 7795001Sgblack@eecs.umich.edu delete traceData; 7805001Sgblack@eecs.umich.edu traceData = NULL; 7813170Sstever@eecs.umich.edu } 7824998Sgblack@eecs.umich.edu 7832644Sstever@eecs.umich.edu postExecute(); 7845103Ssaidi@eecs.umich.edu // @todo remove me after debugging with legion done 7855103Ssaidi@eecs.umich.edu if (curStaticInst && (!curStaticInst->isMicroop() || 7865103Ssaidi@eecs.umich.edu curStaticInst->isFirstMicroop())) 7875103Ssaidi@eecs.umich.edu instCnt++; 7882644Sstever@eecs.umich.edu advanceInst(fault); 7892644Sstever@eecs.umich.edu } 7905726Sgblack@eecs.umich.edu } else if (curStaticInst) { 7912623SN/A // non-memory instruction: execute completely now 7922623SN/A Fault fault = curStaticInst->execute(this, traceData); 7934998Sgblack@eecs.umich.edu 7944998Sgblack@eecs.umich.edu // keep an instruction count 7954998Sgblack@eecs.umich.edu if (fault == NoFault) 7964998Sgblack@eecs.umich.edu countInst(); 7975001Sgblack@eecs.umich.edu else if (traceData) { 7985001Sgblack@eecs.umich.edu // If there was a fault, we shouldn't trace this instruction. 7995001Sgblack@eecs.umich.edu delete traceData; 8005001Sgblack@eecs.umich.edu traceData = NULL; 8015001Sgblack@eecs.umich.edu } 8024998Sgblack@eecs.umich.edu 8032644Sstever@eecs.umich.edu postExecute(); 8045103Ssaidi@eecs.umich.edu // @todo remove me after debugging with legion done 8055103Ssaidi@eecs.umich.edu if (curStaticInst && (!curStaticInst->isMicroop() || 8065103Ssaidi@eecs.umich.edu curStaticInst->isFirstMicroop())) 8075103Ssaidi@eecs.umich.edu instCnt++; 8082644Sstever@eecs.umich.edu advanceInst(fault); 8095726Sgblack@eecs.umich.edu } else { 8105726Sgblack@eecs.umich.edu advanceInst(NoFault); 8112623SN/A } 8123658Sktlim@umich.edu 8135669Sgblack@eecs.umich.edu if (pkt) { 8145669Sgblack@eecs.umich.edu delete pkt->req; 8155669Sgblack@eecs.umich.edu delete pkt; 8165669Sgblack@eecs.umich.edu } 8172623SN/A} 8182623SN/A 8192948Ssaidi@eecs.umich.eduvoid 8202948Ssaidi@eecs.umich.eduTimingSimpleCPU::IcachePort::ITickEvent::process() 8212948Ssaidi@eecs.umich.edu{ 8222948Ssaidi@eecs.umich.edu cpu->completeIfetch(pkt); 8232948Ssaidi@eecs.umich.edu} 8242623SN/A 8252623SN/Abool 8263349Sbinkertn@umich.eduTimingSimpleCPU::IcachePort::recvTiming(PacketPtr pkt) 8272623SN/A{ 8284986Ssaidi@eecs.umich.edu if (pkt->isResponse() && !pkt->wasNacked()) { 8293310Srdreslin@umich.edu // delay processing of returned data until next CPU clock edge 8304584Ssaidi@eecs.umich.edu Tick next_tick = cpu->nextCycle(curTick); 8312948Ssaidi@eecs.umich.edu 8323495Sktlim@umich.edu if (next_tick == curTick) 8333310Srdreslin@umich.edu cpu->completeIfetch(pkt); 8343310Srdreslin@umich.edu else 8353495Sktlim@umich.edu tickEvent.schedule(pkt, next_tick); 8362948Ssaidi@eecs.umich.edu 8373310Srdreslin@umich.edu return true; 8383310Srdreslin@umich.edu } 8394870Sstever@eecs.umich.edu else if (pkt->wasNacked()) { 8404433Ssaidi@eecs.umich.edu assert(cpu->_status == IcacheWaitResponse); 8414433Ssaidi@eecs.umich.edu pkt->reinitNacked(); 8424433Ssaidi@eecs.umich.edu if (!sendTiming(pkt)) { 8434433Ssaidi@eecs.umich.edu cpu->_status = IcacheRetry; 8444433Ssaidi@eecs.umich.edu cpu->ifetch_pkt = pkt; 8454433Ssaidi@eecs.umich.edu } 8463310Srdreslin@umich.edu } 8474433Ssaidi@eecs.umich.edu //Snooping a Coherence Request, do nothing 8484433Ssaidi@eecs.umich.edu return true; 8492623SN/A} 8502623SN/A 8512657Ssaidi@eecs.umich.eduvoid 8522623SN/ATimingSimpleCPU::IcachePort::recvRetry() 8532623SN/A{ 8542623SN/A // we shouldn't get a retry unless we have a packet that we're 8552623SN/A // waiting to transmit 8562623SN/A assert(cpu->ifetch_pkt != NULL); 8572623SN/A assert(cpu->_status == IcacheRetry); 8583349Sbinkertn@umich.edu PacketPtr tmp = cpu->ifetch_pkt; 8592657Ssaidi@eecs.umich.edu if (sendTiming(tmp)) { 8602657Ssaidi@eecs.umich.edu cpu->_status = IcacheWaitResponse; 8612657Ssaidi@eecs.umich.edu cpu->ifetch_pkt = NULL; 8622657Ssaidi@eecs.umich.edu } 8632623SN/A} 8642623SN/A 8652623SN/Avoid 8663349Sbinkertn@umich.eduTimingSimpleCPU::completeDataAccess(PacketPtr pkt) 8672623SN/A{ 8682623SN/A // received a response from the dcache: complete the load or store 8692623SN/A // instruction 8704870Sstever@eecs.umich.edu assert(!pkt->isError()); 8712623SN/A 8725099Ssaidi@eecs.umich.edu numCycles += tickToCycles(curTick - previousTick); 8733222Sktlim@umich.edu previousTick = curTick; 8743184Srdreslin@umich.edu 8755728Sgblack@eecs.umich.edu if (pkt->senderState) { 8765728Sgblack@eecs.umich.edu SplitFragmentSenderState * send_state = 8775728Sgblack@eecs.umich.edu dynamic_cast<SplitFragmentSenderState *>(pkt->senderState); 8785728Sgblack@eecs.umich.edu assert(send_state); 8795728Sgblack@eecs.umich.edu delete pkt->req; 8805728Sgblack@eecs.umich.edu delete pkt; 8815728Sgblack@eecs.umich.edu PacketPtr big_pkt = send_state->bigPkt; 8825728Sgblack@eecs.umich.edu delete send_state; 8835728Sgblack@eecs.umich.edu 8845728Sgblack@eecs.umich.edu SplitMainSenderState * main_send_state = 8855728Sgblack@eecs.umich.edu dynamic_cast<SplitMainSenderState *>(big_pkt->senderState); 8865728Sgblack@eecs.umich.edu assert(main_send_state); 8875728Sgblack@eecs.umich.edu // Record the fact that this packet is no longer outstanding. 8885728Sgblack@eecs.umich.edu assert(main_send_state->outstanding != 0); 8895728Sgblack@eecs.umich.edu main_send_state->outstanding--; 8905728Sgblack@eecs.umich.edu 8915728Sgblack@eecs.umich.edu if (main_send_state->outstanding) { 8925728Sgblack@eecs.umich.edu return; 8935728Sgblack@eecs.umich.edu } else { 8945728Sgblack@eecs.umich.edu delete main_send_state; 8955728Sgblack@eecs.umich.edu big_pkt->senderState = NULL; 8965728Sgblack@eecs.umich.edu pkt = big_pkt; 8975728Sgblack@eecs.umich.edu } 8985728Sgblack@eecs.umich.edu } 8995728Sgblack@eecs.umich.edu 9005894Sgblack@eecs.umich.edu assert(_status == DcacheWaitResponse || _status == DTBWaitResponse); 9015728Sgblack@eecs.umich.edu _status = Running; 9025728Sgblack@eecs.umich.edu 9032623SN/A Fault fault = curStaticInst->completeAcc(pkt, this, traceData); 9042623SN/A 9054998Sgblack@eecs.umich.edu // keep an instruction count 9064998Sgblack@eecs.umich.edu if (fault == NoFault) 9074998Sgblack@eecs.umich.edu countInst(); 9085001Sgblack@eecs.umich.edu else if (traceData) { 9095001Sgblack@eecs.umich.edu // If there was a fault, we shouldn't trace this instruction. 9105001Sgblack@eecs.umich.edu delete traceData; 9115001Sgblack@eecs.umich.edu traceData = NULL; 9125001Sgblack@eecs.umich.edu } 9134998Sgblack@eecs.umich.edu 9145507Sstever@gmail.com // the locked flag may be cleared on the response packet, so check 9155507Sstever@gmail.com // pkt->req and not pkt to see if it was a load-locked 9166102Sgblack@eecs.umich.edu if (pkt->isRead() && pkt->req->isLLSC()) { 9173170Sstever@eecs.umich.edu TheISA::handleLockedRead(thread, pkt->req); 9183170Sstever@eecs.umich.edu } 9193170Sstever@eecs.umich.edu 9202644Sstever@eecs.umich.edu delete pkt->req; 9212644Sstever@eecs.umich.edu delete pkt; 9222644Sstever@eecs.umich.edu 9233184Srdreslin@umich.edu postExecute(); 9243227Sktlim@umich.edu 9253201Shsul@eecs.umich.edu if (getState() == SimObject::Draining) { 9263201Shsul@eecs.umich.edu advancePC(fault); 9273201Shsul@eecs.umich.edu completeDrain(); 9283201Shsul@eecs.umich.edu 9293201Shsul@eecs.umich.edu return; 9303201Shsul@eecs.umich.edu } 9313201Shsul@eecs.umich.edu 9322644Sstever@eecs.umich.edu advanceInst(fault); 9332623SN/A} 9342623SN/A 9352623SN/A 9362798Sktlim@umich.eduvoid 9372839Sktlim@umich.eduTimingSimpleCPU::completeDrain() 9382798Sktlim@umich.edu{ 9392839Sktlim@umich.edu DPRINTF(Config, "Done draining\n"); 9402901Ssaidi@eecs.umich.edu changeState(SimObject::Drained); 9412839Sktlim@umich.edu drainEvent->process(); 9422798Sktlim@umich.edu} 9432623SN/A 9444192Sktlim@umich.eduvoid 9454192Sktlim@umich.eduTimingSimpleCPU::DcachePort::setPeer(Port *port) 9464192Sktlim@umich.edu{ 9474192Sktlim@umich.edu Port::setPeer(port); 9484192Sktlim@umich.edu 9494192Sktlim@umich.edu#if FULL_SYSTEM 9504192Sktlim@umich.edu // Update the ThreadContext's memory ports (Functional/Virtual 9514192Sktlim@umich.edu // Ports) 9525497Ssaidi@eecs.umich.edu cpu->tcBase()->connectMemPorts(cpu->tcBase()); 9534192Sktlim@umich.edu#endif 9544192Sktlim@umich.edu} 9554192Sktlim@umich.edu 9562623SN/Abool 9573349Sbinkertn@umich.eduTimingSimpleCPU::DcachePort::recvTiming(PacketPtr pkt) 9582623SN/A{ 9594986Ssaidi@eecs.umich.edu if (pkt->isResponse() && !pkt->wasNacked()) { 9603310Srdreslin@umich.edu // delay processing of returned data until next CPU clock edge 9614584Ssaidi@eecs.umich.edu Tick next_tick = cpu->nextCycle(curTick); 9622948Ssaidi@eecs.umich.edu 9635728Sgblack@eecs.umich.edu if (next_tick == curTick) { 9643310Srdreslin@umich.edu cpu->completeDataAccess(pkt); 9655728Sgblack@eecs.umich.edu } else { 9663495Sktlim@umich.edu tickEvent.schedule(pkt, next_tick); 9675728Sgblack@eecs.umich.edu } 9682948Ssaidi@eecs.umich.edu 9693310Srdreslin@umich.edu return true; 9703310Srdreslin@umich.edu } 9714870Sstever@eecs.umich.edu else if (pkt->wasNacked()) { 9724433Ssaidi@eecs.umich.edu assert(cpu->_status == DcacheWaitResponse); 9734433Ssaidi@eecs.umich.edu pkt->reinitNacked(); 9744433Ssaidi@eecs.umich.edu if (!sendTiming(pkt)) { 9754433Ssaidi@eecs.umich.edu cpu->_status = DcacheRetry; 9764433Ssaidi@eecs.umich.edu cpu->dcache_pkt = pkt; 9774433Ssaidi@eecs.umich.edu } 9783310Srdreslin@umich.edu } 9794433Ssaidi@eecs.umich.edu //Snooping a Coherence Request, do nothing 9804433Ssaidi@eecs.umich.edu return true; 9812948Ssaidi@eecs.umich.edu} 9822948Ssaidi@eecs.umich.edu 9832948Ssaidi@eecs.umich.eduvoid 9842948Ssaidi@eecs.umich.eduTimingSimpleCPU::DcachePort::DTickEvent::process() 9852948Ssaidi@eecs.umich.edu{ 9862630SN/A cpu->completeDataAccess(pkt); 9872623SN/A} 9882623SN/A 9892657Ssaidi@eecs.umich.eduvoid 9902623SN/ATimingSimpleCPU::DcachePort::recvRetry() 9912623SN/A{ 9922623SN/A // we shouldn't get a retry unless we have a packet that we're 9932623SN/A // waiting to transmit 9942623SN/A assert(cpu->dcache_pkt != NULL); 9952623SN/A assert(cpu->_status == DcacheRetry); 9963349Sbinkertn@umich.edu PacketPtr tmp = cpu->dcache_pkt; 9975728Sgblack@eecs.umich.edu if (tmp->senderState) { 9985728Sgblack@eecs.umich.edu // This is a packet from a split access. 9995728Sgblack@eecs.umich.edu SplitFragmentSenderState * send_state = 10005728Sgblack@eecs.umich.edu dynamic_cast<SplitFragmentSenderState *>(tmp->senderState); 10015728Sgblack@eecs.umich.edu assert(send_state); 10025728Sgblack@eecs.umich.edu PacketPtr big_pkt = send_state->bigPkt; 10035728Sgblack@eecs.umich.edu 10045728Sgblack@eecs.umich.edu SplitMainSenderState * main_send_state = 10055728Sgblack@eecs.umich.edu dynamic_cast<SplitMainSenderState *>(big_pkt->senderState); 10065728Sgblack@eecs.umich.edu assert(main_send_state); 10075728Sgblack@eecs.umich.edu 10085728Sgblack@eecs.umich.edu if (sendTiming(tmp)) { 10095728Sgblack@eecs.umich.edu // If we were able to send without retrying, record that fact 10105728Sgblack@eecs.umich.edu // and try sending the other fragment. 10115728Sgblack@eecs.umich.edu send_state->clearFromParent(); 10125728Sgblack@eecs.umich.edu int other_index = main_send_state->getPendingFragment(); 10135728Sgblack@eecs.umich.edu if (other_index > 0) { 10145728Sgblack@eecs.umich.edu tmp = main_send_state->fragments[other_index]; 10155728Sgblack@eecs.umich.edu cpu->dcache_pkt = tmp; 10165728Sgblack@eecs.umich.edu if ((big_pkt->isRead() && cpu->handleReadPacket(tmp)) || 10175728Sgblack@eecs.umich.edu (big_pkt->isWrite() && cpu->handleWritePacket())) { 10185728Sgblack@eecs.umich.edu main_send_state->fragments[other_index] = NULL; 10195728Sgblack@eecs.umich.edu } 10205728Sgblack@eecs.umich.edu } else { 10215728Sgblack@eecs.umich.edu cpu->_status = DcacheWaitResponse; 10225728Sgblack@eecs.umich.edu // memory system takes ownership of packet 10235728Sgblack@eecs.umich.edu cpu->dcache_pkt = NULL; 10245728Sgblack@eecs.umich.edu } 10255728Sgblack@eecs.umich.edu } 10265728Sgblack@eecs.umich.edu } else if (sendTiming(tmp)) { 10272657Ssaidi@eecs.umich.edu cpu->_status = DcacheWaitResponse; 10283170Sstever@eecs.umich.edu // memory system takes ownership of packet 10292657Ssaidi@eecs.umich.edu cpu->dcache_pkt = NULL; 10302657Ssaidi@eecs.umich.edu } 10312623SN/A} 10322623SN/A 10335606Snate@binkert.orgTimingSimpleCPU::IprEvent::IprEvent(Packet *_pkt, TimingSimpleCPU *_cpu, 10345606Snate@binkert.org Tick t) 10355606Snate@binkert.org : pkt(_pkt), cpu(_cpu) 10365103Ssaidi@eecs.umich.edu{ 10375606Snate@binkert.org cpu->schedule(this, t); 10385103Ssaidi@eecs.umich.edu} 10395103Ssaidi@eecs.umich.edu 10405103Ssaidi@eecs.umich.eduvoid 10415103Ssaidi@eecs.umich.eduTimingSimpleCPU::IprEvent::process() 10425103Ssaidi@eecs.umich.edu{ 10435103Ssaidi@eecs.umich.edu cpu->completeDataAccess(pkt); 10445103Ssaidi@eecs.umich.edu} 10455103Ssaidi@eecs.umich.edu 10465103Ssaidi@eecs.umich.educonst char * 10475336Shines@cs.fsu.eduTimingSimpleCPU::IprEvent::description() const 10485103Ssaidi@eecs.umich.edu{ 10495103Ssaidi@eecs.umich.edu return "Timing Simple CPU Delay IPR event"; 10505103Ssaidi@eecs.umich.edu} 10515103Ssaidi@eecs.umich.edu 10522623SN/A 10535315Sstever@gmail.comvoid 10545315Sstever@gmail.comTimingSimpleCPU::printAddr(Addr a) 10555315Sstever@gmail.com{ 10565315Sstever@gmail.com dcachePort.printAddr(a); 10575315Sstever@gmail.com} 10585315Sstever@gmail.com 10595315Sstever@gmail.com 10602623SN/A//////////////////////////////////////////////////////////////////////// 10612623SN/A// 10622623SN/A// TimingSimpleCPU Simulation Object 10632623SN/A// 10644762Snate@binkert.orgTimingSimpleCPU * 10654762Snate@binkert.orgTimingSimpleCPUParams::create() 10662623SN/A{ 10675529Snate@binkert.org numThreads = 1; 10685529Snate@binkert.org#if !FULL_SYSTEM 10694762Snate@binkert.org if (workload.size() != 1) 10704762Snate@binkert.org panic("only one workload allowed"); 10712623SN/A#endif 10725529Snate@binkert.org return new TimingSimpleCPU(this); 10732623SN/A} 1074