timing.cc revision 5744
12623SN/A/* 22623SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 32623SN/A * All rights reserved. 42623SN/A * 52623SN/A * Redistribution and use in source and binary forms, with or without 62623SN/A * modification, are permitted provided that the following conditions are 72623SN/A * met: redistributions of source code must retain the above copyright 82623SN/A * notice, this list of conditions and the following disclaimer; 92623SN/A * redistributions in binary form must reproduce the above copyright 102623SN/A * notice, this list of conditions and the following disclaimer in the 112623SN/A * documentation and/or other materials provided with the distribution; 122623SN/A * neither the name of the copyright holders nor the names of its 132623SN/A * contributors may be used to endorse or promote products derived from 142623SN/A * this software without specific prior written permission. 152623SN/A * 162623SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172623SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182623SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192623SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202623SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212623SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222623SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232623SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242623SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252623SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262623SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 292623SN/A */ 302623SN/A 313170Sstever@eecs.umich.edu#include "arch/locked_mem.hh" 325103Ssaidi@eecs.umich.edu#include "arch/mmaped_ipr.hh" 332623SN/A#include "arch/utility.hh" 344040Ssaidi@eecs.umich.edu#include "base/bigint.hh" 352623SN/A#include "cpu/exetrace.hh" 362623SN/A#include "cpu/simple/timing.hh" 373348Sbinkertn@umich.edu#include "mem/packet.hh" 383348Sbinkertn@umich.edu#include "mem/packet_access.hh" 394762Snate@binkert.org#include "params/TimingSimpleCPU.hh" 402901Ssaidi@eecs.umich.edu#include "sim/system.hh" 412623SN/A 422623SN/Ausing namespace std; 432623SN/Ausing namespace TheISA; 442623SN/A 452856Srdreslin@umich.eduPort * 462856Srdreslin@umich.eduTimingSimpleCPU::getPort(const std::string &if_name, int idx) 472856Srdreslin@umich.edu{ 482856Srdreslin@umich.edu if (if_name == "dcache_port") 492856Srdreslin@umich.edu return &dcachePort; 502856Srdreslin@umich.edu else if (if_name == "icache_port") 512856Srdreslin@umich.edu return &icachePort; 522856Srdreslin@umich.edu else 532856Srdreslin@umich.edu panic("No Such Port\n"); 542856Srdreslin@umich.edu} 552623SN/A 562623SN/Avoid 572623SN/ATimingSimpleCPU::init() 582623SN/A{ 592623SN/A BaseCPU::init(); 602623SN/A#if FULL_SYSTEM 612680Sktlim@umich.edu for (int i = 0; i < threadContexts.size(); ++i) { 622680Sktlim@umich.edu ThreadContext *tc = threadContexts[i]; 632623SN/A 642623SN/A // initialize CPU, including PC 655712Shsul@eecs.umich.edu TheISA::initCPU(tc, _cpuId); 662623SN/A } 672623SN/A#endif 682623SN/A} 692623SN/A 702623SN/ATick 713349Sbinkertn@umich.eduTimingSimpleCPU::CpuPort::recvAtomic(PacketPtr pkt) 722623SN/A{ 732623SN/A panic("TimingSimpleCPU doesn't expect recvAtomic callback!"); 742623SN/A return curTick; 752623SN/A} 762623SN/A 772623SN/Avoid 783349Sbinkertn@umich.eduTimingSimpleCPU::CpuPort::recvFunctional(PacketPtr pkt) 792623SN/A{ 803184Srdreslin@umich.edu //No internal storage to update, jusst return 813184Srdreslin@umich.edu return; 822623SN/A} 832623SN/A 842623SN/Avoid 852623SN/ATimingSimpleCPU::CpuPort::recvStatusChange(Status status) 862623SN/A{ 873647Srdreslin@umich.edu if (status == RangeChange) { 883647Srdreslin@umich.edu if (!snoopRangeSent) { 893647Srdreslin@umich.edu snoopRangeSent = true; 903647Srdreslin@umich.edu sendStatusChange(Port::RangeChange); 913647Srdreslin@umich.edu } 922631SN/A return; 933647Srdreslin@umich.edu } 942631SN/A 952623SN/A panic("TimingSimpleCPU doesn't expect recvStatusChange callback!"); 962623SN/A} 972623SN/A 982948Ssaidi@eecs.umich.edu 992948Ssaidi@eecs.umich.eduvoid 1003349Sbinkertn@umich.eduTimingSimpleCPU::CpuPort::TickEvent::schedule(PacketPtr _pkt, Tick t) 1012948Ssaidi@eecs.umich.edu{ 1022948Ssaidi@eecs.umich.edu pkt = _pkt; 1035606Snate@binkert.org cpu->schedule(this, t); 1042948Ssaidi@eecs.umich.edu} 1052948Ssaidi@eecs.umich.edu 1065529Snate@binkert.orgTimingSimpleCPU::TimingSimpleCPU(TimingSimpleCPUParams *p) 1075710Scws3k@cs.virginia.edu : BaseSimpleCPU(p), icachePort(this, p->clock), dcachePort(this, p->clock), fetchEvent(this) 1082623SN/A{ 1092623SN/A _status = Idle; 1103647Srdreslin@umich.edu 1113647Srdreslin@umich.edu icachePort.snoopRangeSent = false; 1123647Srdreslin@umich.edu dcachePort.snoopRangeSent = false; 1133647Srdreslin@umich.edu 1142623SN/A ifetch_pkt = dcache_pkt = NULL; 1152839Sktlim@umich.edu drainEvent = NULL; 1163222Sktlim@umich.edu previousTick = 0; 1172901Ssaidi@eecs.umich.edu changeState(SimObject::Running); 1182623SN/A} 1192623SN/A 1202623SN/A 1212623SN/ATimingSimpleCPU::~TimingSimpleCPU() 1222623SN/A{ 1232623SN/A} 1242623SN/A 1252623SN/Avoid 1262623SN/ATimingSimpleCPU::serialize(ostream &os) 1272623SN/A{ 1282915Sktlim@umich.edu SimObject::State so_state = SimObject::getState(); 1292915Sktlim@umich.edu SERIALIZE_ENUM(so_state); 1302623SN/A BaseSimpleCPU::serialize(os); 1312623SN/A} 1322623SN/A 1332623SN/Avoid 1342623SN/ATimingSimpleCPU::unserialize(Checkpoint *cp, const string §ion) 1352623SN/A{ 1362915Sktlim@umich.edu SimObject::State so_state; 1372915Sktlim@umich.edu UNSERIALIZE_ENUM(so_state); 1382623SN/A BaseSimpleCPU::unserialize(cp, section); 1392798Sktlim@umich.edu} 1402798Sktlim@umich.edu 1412901Ssaidi@eecs.umich.eduunsigned int 1422839Sktlim@umich.eduTimingSimpleCPU::drain(Event *drain_event) 1432798Sktlim@umich.edu{ 1442839Sktlim@umich.edu // TimingSimpleCPU is ready to drain if it's not waiting for 1452798Sktlim@umich.edu // an access to complete. 1465496Ssaidi@eecs.umich.edu if (_status == Idle || _status == Running || _status == SwitchedOut) { 1472901Ssaidi@eecs.umich.edu changeState(SimObject::Drained); 1482901Ssaidi@eecs.umich.edu return 0; 1492798Sktlim@umich.edu } else { 1502839Sktlim@umich.edu changeState(SimObject::Draining); 1512839Sktlim@umich.edu drainEvent = drain_event; 1522901Ssaidi@eecs.umich.edu return 1; 1532798Sktlim@umich.edu } 1542623SN/A} 1552623SN/A 1562623SN/Avoid 1572798Sktlim@umich.eduTimingSimpleCPU::resume() 1582623SN/A{ 1595221Ssaidi@eecs.umich.edu DPRINTF(SimpleCPU, "Resume\n"); 1602798Sktlim@umich.edu if (_status != SwitchedOut && _status != Idle) { 1614762Snate@binkert.org assert(system->getMemoryMode() == Enums::timing); 1623201Shsul@eecs.umich.edu 1635710Scws3k@cs.virginia.edu if (fetchEvent.scheduled()) 1645710Scws3k@cs.virginia.edu deschedule(fetchEvent); 1652915Sktlim@umich.edu 1665710Scws3k@cs.virginia.edu schedule(fetchEvent, nextCycle()); 1672623SN/A } 1682798Sktlim@umich.edu 1692901Ssaidi@eecs.umich.edu changeState(SimObject::Running); 1702798Sktlim@umich.edu} 1712798Sktlim@umich.edu 1722798Sktlim@umich.eduvoid 1732798Sktlim@umich.eduTimingSimpleCPU::switchOut() 1742798Sktlim@umich.edu{ 1755496Ssaidi@eecs.umich.edu assert(_status == Running || _status == Idle); 1762798Sktlim@umich.edu _status = SwitchedOut; 1775099Ssaidi@eecs.umich.edu numCycles += tickToCycles(curTick - previousTick); 1782867Sktlim@umich.edu 1792867Sktlim@umich.edu // If we've been scheduled to resume but are then told to switch out, 1802867Sktlim@umich.edu // we'll need to cancel it. 1815710Scws3k@cs.virginia.edu if (fetchEvent.scheduled()) 1825606Snate@binkert.org deschedule(fetchEvent); 1832623SN/A} 1842623SN/A 1852623SN/A 1862623SN/Avoid 1872623SN/ATimingSimpleCPU::takeOverFrom(BaseCPU *oldCPU) 1882623SN/A{ 1894192Sktlim@umich.edu BaseCPU::takeOverFrom(oldCPU, &icachePort, &dcachePort); 1902623SN/A 1912680Sktlim@umich.edu // if any of this CPU's ThreadContexts are active, mark the CPU as 1922623SN/A // running and schedule its tick event. 1932680Sktlim@umich.edu for (int i = 0; i < threadContexts.size(); ++i) { 1942680Sktlim@umich.edu ThreadContext *tc = threadContexts[i]; 1952680Sktlim@umich.edu if (tc->status() == ThreadContext::Active && _status != Running) { 1962623SN/A _status = Running; 1972623SN/A break; 1982623SN/A } 1992623SN/A } 2003201Shsul@eecs.umich.edu 2013201Shsul@eecs.umich.edu if (_status != Running) { 2023201Shsul@eecs.umich.edu _status = Idle; 2033201Shsul@eecs.umich.edu } 2045169Ssaidi@eecs.umich.edu assert(threadContexts.size() == 1); 2055101Ssaidi@eecs.umich.edu previousTick = curTick; 2062623SN/A} 2072623SN/A 2082623SN/A 2092623SN/Avoid 2102623SN/ATimingSimpleCPU::activateContext(int thread_num, int delay) 2112623SN/A{ 2125221Ssaidi@eecs.umich.edu DPRINTF(SimpleCPU, "ActivateContext %d (%d cycles)\n", thread_num, delay); 2135221Ssaidi@eecs.umich.edu 2142623SN/A assert(thread_num == 0); 2152683Sktlim@umich.edu assert(thread); 2162623SN/A 2172623SN/A assert(_status == Idle); 2182623SN/A 2192623SN/A notIdleFraction++; 2202623SN/A _status = Running; 2213686Sktlim@umich.edu 2222623SN/A // kick things off by initiating the fetch of the next instruction 2235606Snate@binkert.org schedule(fetchEvent, nextCycle(curTick + ticks(delay))); 2242623SN/A} 2252623SN/A 2262623SN/A 2272623SN/Avoid 2282623SN/ATimingSimpleCPU::suspendContext(int thread_num) 2292623SN/A{ 2305221Ssaidi@eecs.umich.edu DPRINTF(SimpleCPU, "SuspendContext %d\n", thread_num); 2315221Ssaidi@eecs.umich.edu 2322623SN/A assert(thread_num == 0); 2332683Sktlim@umich.edu assert(thread); 2342623SN/A 2352644Sstever@eecs.umich.edu assert(_status == Running); 2362623SN/A 2372644Sstever@eecs.umich.edu // just change status to Idle... if status != Running, 2382644Sstever@eecs.umich.edu // completeInst() will not initiate fetch of next instruction. 2392623SN/A 2402623SN/A notIdleFraction--; 2412623SN/A _status = Idle; 2422623SN/A} 2432623SN/A 2445728Sgblack@eecs.umich.edubool 2455728Sgblack@eecs.umich.eduTimingSimpleCPU::handleReadPacket(PacketPtr pkt) 2465728Sgblack@eecs.umich.edu{ 2475728Sgblack@eecs.umich.edu RequestPtr req = pkt->req; 2485728Sgblack@eecs.umich.edu if (req->isMmapedIpr()) { 2495728Sgblack@eecs.umich.edu Tick delay; 2505728Sgblack@eecs.umich.edu delay = TheISA::handleIprRead(thread->getTC(), pkt); 2515728Sgblack@eecs.umich.edu new IprEvent(pkt, this, nextCycle(curTick + delay)); 2525728Sgblack@eecs.umich.edu _status = DcacheWaitResponse; 2535728Sgblack@eecs.umich.edu dcache_pkt = NULL; 2545728Sgblack@eecs.umich.edu } else if (!dcachePort.sendTiming(pkt)) { 2555728Sgblack@eecs.umich.edu _status = DcacheRetry; 2565728Sgblack@eecs.umich.edu dcache_pkt = pkt; 2575728Sgblack@eecs.umich.edu } else { 2585728Sgblack@eecs.umich.edu _status = DcacheWaitResponse; 2595728Sgblack@eecs.umich.edu // memory system takes ownership of packet 2605728Sgblack@eecs.umich.edu dcache_pkt = NULL; 2615728Sgblack@eecs.umich.edu } 2625728Sgblack@eecs.umich.edu return dcache_pkt == NULL; 2635728Sgblack@eecs.umich.edu} 2642623SN/A 2655744Sgblack@eecs.umich.eduFault 2665744Sgblack@eecs.umich.eduTimingSimpleCPU::buildSplitPacket(PacketPtr &pkt1, PacketPtr &pkt2, 2675744Sgblack@eecs.umich.edu RequestPtr &req, Addr split_addr, uint8_t *data, bool read) 2685744Sgblack@eecs.umich.edu{ 2695744Sgblack@eecs.umich.edu Fault fault; 2705744Sgblack@eecs.umich.edu RequestPtr req1, req2; 2715744Sgblack@eecs.umich.edu assert(!req->isLocked() && !req->isSwap()); 2725744Sgblack@eecs.umich.edu req->splitOnVaddr(split_addr, req1, req2); 2735744Sgblack@eecs.umich.edu 2745744Sgblack@eecs.umich.edu pkt1 = pkt2 = NULL; 2755744Sgblack@eecs.umich.edu if ((fault = buildPacket(pkt1, req1, read)) != NoFault || 2765744Sgblack@eecs.umich.edu (fault = buildPacket(pkt2, req2, read)) != NoFault) { 2775744Sgblack@eecs.umich.edu delete req; 2785744Sgblack@eecs.umich.edu delete pkt1; 2795744Sgblack@eecs.umich.edu req = NULL; 2805744Sgblack@eecs.umich.edu pkt1 = NULL; 2815744Sgblack@eecs.umich.edu return fault; 2825744Sgblack@eecs.umich.edu } 2835744Sgblack@eecs.umich.edu 2845744Sgblack@eecs.umich.edu assert(!req1->isMmapedIpr() && !req2->isMmapedIpr()); 2855744Sgblack@eecs.umich.edu 2865744Sgblack@eecs.umich.edu req->setPhys(req1->getPaddr(), req->getSize(), req1->getFlags()); 2875744Sgblack@eecs.umich.edu PacketPtr pkt = new Packet(req, pkt1->cmd.responseCommand(), 2885744Sgblack@eecs.umich.edu Packet::Broadcast); 2895744Sgblack@eecs.umich.edu 2905744Sgblack@eecs.umich.edu pkt->dataDynamic<uint8_t>(data); 2915744Sgblack@eecs.umich.edu pkt1->dataStatic<uint8_t>(data); 2925744Sgblack@eecs.umich.edu pkt2->dataStatic<uint8_t>(data + req1->getSize()); 2935744Sgblack@eecs.umich.edu 2945744Sgblack@eecs.umich.edu SplitMainSenderState * main_send_state = new SplitMainSenderState; 2955744Sgblack@eecs.umich.edu pkt->senderState = main_send_state; 2965744Sgblack@eecs.umich.edu main_send_state->fragments[0] = pkt1; 2975744Sgblack@eecs.umich.edu main_send_state->fragments[1] = pkt2; 2985744Sgblack@eecs.umich.edu main_send_state->outstanding = 2; 2995744Sgblack@eecs.umich.edu pkt1->senderState = new SplitFragmentSenderState(pkt, 0); 3005744Sgblack@eecs.umich.edu pkt2->senderState = new SplitFragmentSenderState(pkt, 1); 3015744Sgblack@eecs.umich.edu return fault; 3025744Sgblack@eecs.umich.edu} 3035744Sgblack@eecs.umich.edu 3045744Sgblack@eecs.umich.eduFault 3055744Sgblack@eecs.umich.eduTimingSimpleCPU::buildPacket(PacketPtr &pkt, RequestPtr &req, bool read) 3065744Sgblack@eecs.umich.edu{ 3075744Sgblack@eecs.umich.edu Fault fault = read ? thread->translateDataReadReq(req) : 3085744Sgblack@eecs.umich.edu thread->translateDataWriteReq(req); 3095744Sgblack@eecs.umich.edu MemCmd cmd; 3105744Sgblack@eecs.umich.edu if (fault != NoFault) { 3115744Sgblack@eecs.umich.edu delete req; 3125744Sgblack@eecs.umich.edu req = NULL; 3135744Sgblack@eecs.umich.edu pkt = NULL; 3145744Sgblack@eecs.umich.edu return fault; 3155744Sgblack@eecs.umich.edu } else if (read) { 3165744Sgblack@eecs.umich.edu cmd = MemCmd::ReadReq; 3175744Sgblack@eecs.umich.edu if (req->isLocked()) 3185744Sgblack@eecs.umich.edu cmd = MemCmd::LoadLockedReq; 3195744Sgblack@eecs.umich.edu } else { 3205744Sgblack@eecs.umich.edu cmd = MemCmd::WriteReq; 3215744Sgblack@eecs.umich.edu if (req->isLocked()) { 3225744Sgblack@eecs.umich.edu cmd = MemCmd::StoreCondReq; 3235744Sgblack@eecs.umich.edu } else if (req->isSwap()) { 3245744Sgblack@eecs.umich.edu cmd = MemCmd::SwapReq; 3255744Sgblack@eecs.umich.edu } 3265744Sgblack@eecs.umich.edu } 3275744Sgblack@eecs.umich.edu pkt = new Packet(req, cmd, Packet::Broadcast); 3285744Sgblack@eecs.umich.edu return NoFault; 3295744Sgblack@eecs.umich.edu} 3305744Sgblack@eecs.umich.edu 3312623SN/Atemplate <class T> 3322623SN/AFault 3332623SN/ATimingSimpleCPU::read(Addr addr, T &data, unsigned flags) 3342623SN/A{ 3355728Sgblack@eecs.umich.edu Fault fault; 3365728Sgblack@eecs.umich.edu const int asid = 0; 3375728Sgblack@eecs.umich.edu const int thread_id = 0; 3385728Sgblack@eecs.umich.edu const Addr pc = thread->readPC(); 3395728Sgblack@eecs.umich.edu int block_size = dcachePort.peerBlockSize(); 3405728Sgblack@eecs.umich.edu int data_size = sizeof(T); 3412623SN/A 3425744Sgblack@eecs.umich.edu PacketPtr pkt; 3435744Sgblack@eecs.umich.edu RequestPtr req = new Request(asid, addr, data_size, 3445744Sgblack@eecs.umich.edu flags, pc, _cpuId, thread_id); 3455728Sgblack@eecs.umich.edu 3465744Sgblack@eecs.umich.edu Addr split_addr = roundDown(addr + data_size - 1, block_size); 3475744Sgblack@eecs.umich.edu assert(split_addr <= addr || split_addr - addr < block_size); 3485728Sgblack@eecs.umich.edu 3495744Sgblack@eecs.umich.edu if (split_addr > addr) { 3505744Sgblack@eecs.umich.edu PacketPtr pkt1, pkt2; 3515744Sgblack@eecs.umich.edu this->buildSplitPacket(pkt1, pkt2, req, 3525744Sgblack@eecs.umich.edu split_addr, (uint8_t *)(new T), true); 3535744Sgblack@eecs.umich.edu if (handleReadPacket(pkt1)) { 3545744Sgblack@eecs.umich.edu SplitFragmentSenderState * send_state = 3555744Sgblack@eecs.umich.edu dynamic_cast<SplitFragmentSenderState *>(pkt1->senderState); 3565744Sgblack@eecs.umich.edu send_state->clearFromParent(); 3575744Sgblack@eecs.umich.edu if (handleReadPacket(pkt2)) { 3585744Sgblack@eecs.umich.edu send_state = 3595744Sgblack@eecs.umich.edu dynamic_cast<SplitFragmentSenderState *>(pkt1->senderState); 3605744Sgblack@eecs.umich.edu send_state->clearFromParent(); 3615744Sgblack@eecs.umich.edu } 3625744Sgblack@eecs.umich.edu } 3635744Sgblack@eecs.umich.edu } else { 3645744Sgblack@eecs.umich.edu Fault fault = buildPacket(pkt, req, true); 3655728Sgblack@eecs.umich.edu if (fault != NoFault) { 3665728Sgblack@eecs.umich.edu return fault; 3675728Sgblack@eecs.umich.edu } 3683169Sstever@eecs.umich.edu pkt->dataDynamic<T>(new T); 3692623SN/A 3705728Sgblack@eecs.umich.edu handleReadPacket(pkt); 3712623SN/A } 3722623SN/A 3735408Sgblack@eecs.umich.edu if (traceData) { 3745408Sgblack@eecs.umich.edu traceData->setData(data); 3755728Sgblack@eecs.umich.edu traceData->setAddr(addr); 3765408Sgblack@eecs.umich.edu } 3775728Sgblack@eecs.umich.edu 3785728Sgblack@eecs.umich.edu // This will need a new way to tell if it has a dcache attached. 3795728Sgblack@eecs.umich.edu if (req->isUncacheable()) 3805728Sgblack@eecs.umich.edu recordEvent("Uncached Read"); 3815728Sgblack@eecs.umich.edu 3825728Sgblack@eecs.umich.edu return NoFault; 3832623SN/A} 3842623SN/A 3855177Sgblack@eecs.umich.eduFault 3865177Sgblack@eecs.umich.eduTimingSimpleCPU::translateDataReadAddr(Addr vaddr, Addr &paddr, 3875177Sgblack@eecs.umich.edu int size, unsigned flags) 3885177Sgblack@eecs.umich.edu{ 3895177Sgblack@eecs.umich.edu Request *req = 3905712Shsul@eecs.umich.edu new Request(0, vaddr, size, flags, thread->readPC(), _cpuId, 0); 3915177Sgblack@eecs.umich.edu 3925177Sgblack@eecs.umich.edu if (traceData) { 3935177Sgblack@eecs.umich.edu traceData->setAddr(vaddr); 3945177Sgblack@eecs.umich.edu } 3955177Sgblack@eecs.umich.edu 3965177Sgblack@eecs.umich.edu Fault fault = thread->translateDataWriteReq(req); 3975177Sgblack@eecs.umich.edu 3985177Sgblack@eecs.umich.edu if (fault == NoFault) 3995177Sgblack@eecs.umich.edu paddr = req->getPaddr(); 4005177Sgblack@eecs.umich.edu 4015177Sgblack@eecs.umich.edu delete req; 4025177Sgblack@eecs.umich.edu return fault; 4035177Sgblack@eecs.umich.edu} 4045177Sgblack@eecs.umich.edu 4052623SN/A#ifndef DOXYGEN_SHOULD_SKIP_THIS 4062623SN/A 4072623SN/Atemplate 4082623SN/AFault 4094040Ssaidi@eecs.umich.eduTimingSimpleCPU::read(Addr addr, Twin64_t &data, unsigned flags); 4104040Ssaidi@eecs.umich.edu 4114040Ssaidi@eecs.umich.edutemplate 4124040Ssaidi@eecs.umich.eduFault 4134115Ssaidi@eecs.umich.eduTimingSimpleCPU::read(Addr addr, Twin32_t &data, unsigned flags); 4144115Ssaidi@eecs.umich.edu 4154115Ssaidi@eecs.umich.edutemplate 4164115Ssaidi@eecs.umich.eduFault 4172623SN/ATimingSimpleCPU::read(Addr addr, uint64_t &data, unsigned flags); 4182623SN/A 4192623SN/Atemplate 4202623SN/AFault 4212623SN/ATimingSimpleCPU::read(Addr addr, uint32_t &data, unsigned flags); 4222623SN/A 4232623SN/Atemplate 4242623SN/AFault 4252623SN/ATimingSimpleCPU::read(Addr addr, uint16_t &data, unsigned flags); 4262623SN/A 4272623SN/Atemplate 4282623SN/AFault 4292623SN/ATimingSimpleCPU::read(Addr addr, uint8_t &data, unsigned flags); 4302623SN/A 4312623SN/A#endif //DOXYGEN_SHOULD_SKIP_THIS 4322623SN/A 4332623SN/Atemplate<> 4342623SN/AFault 4352623SN/ATimingSimpleCPU::read(Addr addr, double &data, unsigned flags) 4362623SN/A{ 4372623SN/A return read(addr, *(uint64_t*)&data, flags); 4382623SN/A} 4392623SN/A 4402623SN/Atemplate<> 4412623SN/AFault 4422623SN/ATimingSimpleCPU::read(Addr addr, float &data, unsigned flags) 4432623SN/A{ 4442623SN/A return read(addr, *(uint32_t*)&data, flags); 4452623SN/A} 4462623SN/A 4472623SN/A 4482623SN/Atemplate<> 4492623SN/AFault 4502623SN/ATimingSimpleCPU::read(Addr addr, int32_t &data, unsigned flags) 4512623SN/A{ 4522623SN/A return read(addr, (uint32_t&)data, flags); 4532623SN/A} 4542623SN/A 4555728Sgblack@eecs.umich.edubool 4565728Sgblack@eecs.umich.eduTimingSimpleCPU::handleWritePacket() 4575728Sgblack@eecs.umich.edu{ 4585728Sgblack@eecs.umich.edu RequestPtr req = dcache_pkt->req; 4595728Sgblack@eecs.umich.edu if (req->isMmapedIpr()) { 4605728Sgblack@eecs.umich.edu Tick delay; 4615728Sgblack@eecs.umich.edu delay = TheISA::handleIprWrite(thread->getTC(), dcache_pkt); 4625728Sgblack@eecs.umich.edu new IprEvent(dcache_pkt, this, nextCycle(curTick + delay)); 4635728Sgblack@eecs.umich.edu _status = DcacheWaitResponse; 4645728Sgblack@eecs.umich.edu dcache_pkt = NULL; 4655728Sgblack@eecs.umich.edu } else if (!dcachePort.sendTiming(dcache_pkt)) { 4665728Sgblack@eecs.umich.edu _status = DcacheRetry; 4675728Sgblack@eecs.umich.edu } else { 4685728Sgblack@eecs.umich.edu _status = DcacheWaitResponse; 4695728Sgblack@eecs.umich.edu // memory system takes ownership of packet 4705728Sgblack@eecs.umich.edu dcache_pkt = NULL; 4715728Sgblack@eecs.umich.edu } 4725728Sgblack@eecs.umich.edu return dcache_pkt == NULL; 4735728Sgblack@eecs.umich.edu} 4742623SN/A 4752623SN/Atemplate <class T> 4762623SN/AFault 4772623SN/ATimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res) 4782623SN/A{ 4795728Sgblack@eecs.umich.edu const int asid = 0; 4805728Sgblack@eecs.umich.edu const int thread_id = 0; 4815728Sgblack@eecs.umich.edu const Addr pc = thread->readPC(); 4825728Sgblack@eecs.umich.edu int block_size = dcachePort.peerBlockSize(); 4835728Sgblack@eecs.umich.edu int data_size = sizeof(T); 4843169Sstever@eecs.umich.edu 4855744Sgblack@eecs.umich.edu RequestPtr req = new Request(asid, addr, data_size, 4865744Sgblack@eecs.umich.edu flags, pc, _cpuId, thread_id); 4875728Sgblack@eecs.umich.edu 4885744Sgblack@eecs.umich.edu Addr split_addr = roundDown(addr + data_size - 1, block_size); 4895744Sgblack@eecs.umich.edu assert(split_addr <= addr || split_addr - addr < block_size); 4905728Sgblack@eecs.umich.edu 4915744Sgblack@eecs.umich.edu if (split_addr > addr) { 4925744Sgblack@eecs.umich.edu PacketPtr pkt1, pkt2; 4935744Sgblack@eecs.umich.edu T *dataP = new T; 4945744Sgblack@eecs.umich.edu *dataP = data; 4955744Sgblack@eecs.umich.edu Fault fault = this->buildSplitPacket(pkt1, pkt2, req, split_addr, 4965744Sgblack@eecs.umich.edu (uint8_t *)dataP, false); 4975744Sgblack@eecs.umich.edu if (fault != NoFault) 4985728Sgblack@eecs.umich.edu return fault; 4995744Sgblack@eecs.umich.edu dcache_pkt = pkt1; 5005744Sgblack@eecs.umich.edu if (handleWritePacket()) { 5015744Sgblack@eecs.umich.edu SplitFragmentSenderState * send_state = 5025744Sgblack@eecs.umich.edu dynamic_cast<SplitFragmentSenderState *>(pkt1->senderState); 5035744Sgblack@eecs.umich.edu send_state->clearFromParent(); 5045744Sgblack@eecs.umich.edu dcache_pkt = pkt2; 5055744Sgblack@eecs.umich.edu if (handleReadPacket(pkt2)) { 5065744Sgblack@eecs.umich.edu send_state = 5075744Sgblack@eecs.umich.edu dynamic_cast<SplitFragmentSenderState *>(pkt1->senderState); 5085744Sgblack@eecs.umich.edu send_state->clearFromParent(); 5095744Sgblack@eecs.umich.edu } 5105728Sgblack@eecs.umich.edu } 5115744Sgblack@eecs.umich.edu } else { 5125744Sgblack@eecs.umich.edu bool do_access = true; // flag to suppress cache access 5135744Sgblack@eecs.umich.edu 5145744Sgblack@eecs.umich.edu Fault fault = buildPacket(dcache_pkt, req, false); 5155744Sgblack@eecs.umich.edu if (fault != NoFault) 5165728Sgblack@eecs.umich.edu return fault; 5175744Sgblack@eecs.umich.edu 5185744Sgblack@eecs.umich.edu if (req->isLocked()) { 5195744Sgblack@eecs.umich.edu do_access = TheISA::handleLockedWrite(thread, req); 5205744Sgblack@eecs.umich.edu } else if (req->isCondSwap()) { 5215744Sgblack@eecs.umich.edu assert(res); 5225744Sgblack@eecs.umich.edu req->setExtraData(*res); 5235728Sgblack@eecs.umich.edu } 5245728Sgblack@eecs.umich.edu 5254881Sstever@eecs.umich.edu dcache_pkt->allocate(); 5265728Sgblack@eecs.umich.edu if (req->isMmapedIpr()) 5275728Sgblack@eecs.umich.edu dcache_pkt->set(htog(data)); 5285728Sgblack@eecs.umich.edu else 5295728Sgblack@eecs.umich.edu dcache_pkt->set(data); 5303170Sstever@eecs.umich.edu 5315728Sgblack@eecs.umich.edu if (do_access) 5325728Sgblack@eecs.umich.edu handleWritePacket(); 5332623SN/A } 5342623SN/A 5355408Sgblack@eecs.umich.edu if (traceData) { 5365728Sgblack@eecs.umich.edu traceData->setAddr(req->getVaddr()); 5375408Sgblack@eecs.umich.edu traceData->setData(data); 5385408Sgblack@eecs.umich.edu } 5392623SN/A 5405728Sgblack@eecs.umich.edu // This will need a new way to tell if it's hooked up to a cache or not. 5415728Sgblack@eecs.umich.edu if (req->isUncacheable()) 5425728Sgblack@eecs.umich.edu recordEvent("Uncached Write"); 5435728Sgblack@eecs.umich.edu 5442623SN/A // If the write needs to have a fault on the access, consider calling 5452623SN/A // changeStatus() and changing it to "bad addr write" or something. 5465728Sgblack@eecs.umich.edu return NoFault; 5472623SN/A} 5482623SN/A 5495177Sgblack@eecs.umich.eduFault 5505177Sgblack@eecs.umich.eduTimingSimpleCPU::translateDataWriteAddr(Addr vaddr, Addr &paddr, 5515177Sgblack@eecs.umich.edu int size, unsigned flags) 5525177Sgblack@eecs.umich.edu{ 5535177Sgblack@eecs.umich.edu Request *req = 5545712Shsul@eecs.umich.edu new Request(0, vaddr, size, flags, thread->readPC(), _cpuId, 0); 5555177Sgblack@eecs.umich.edu 5565177Sgblack@eecs.umich.edu if (traceData) { 5575177Sgblack@eecs.umich.edu traceData->setAddr(vaddr); 5585177Sgblack@eecs.umich.edu } 5595177Sgblack@eecs.umich.edu 5605177Sgblack@eecs.umich.edu Fault fault = thread->translateDataWriteReq(req); 5615177Sgblack@eecs.umich.edu 5625177Sgblack@eecs.umich.edu if (fault == NoFault) 5635177Sgblack@eecs.umich.edu paddr = req->getPaddr(); 5645177Sgblack@eecs.umich.edu 5655177Sgblack@eecs.umich.edu delete req; 5665177Sgblack@eecs.umich.edu return fault; 5675177Sgblack@eecs.umich.edu} 5685177Sgblack@eecs.umich.edu 5692623SN/A 5702623SN/A#ifndef DOXYGEN_SHOULD_SKIP_THIS 5712623SN/Atemplate 5722623SN/AFault 5734224Sgblack@eecs.umich.eduTimingSimpleCPU::write(Twin32_t data, Addr addr, 5744224Sgblack@eecs.umich.edu unsigned flags, uint64_t *res); 5754224Sgblack@eecs.umich.edu 5764224Sgblack@eecs.umich.edutemplate 5774224Sgblack@eecs.umich.eduFault 5784224Sgblack@eecs.umich.eduTimingSimpleCPU::write(Twin64_t data, Addr addr, 5794224Sgblack@eecs.umich.edu unsigned flags, uint64_t *res); 5804224Sgblack@eecs.umich.edu 5814224Sgblack@eecs.umich.edutemplate 5824224Sgblack@eecs.umich.eduFault 5832623SN/ATimingSimpleCPU::write(uint64_t data, Addr addr, 5842623SN/A unsigned flags, uint64_t *res); 5852623SN/A 5862623SN/Atemplate 5872623SN/AFault 5882623SN/ATimingSimpleCPU::write(uint32_t data, Addr addr, 5892623SN/A unsigned flags, uint64_t *res); 5902623SN/A 5912623SN/Atemplate 5922623SN/AFault 5932623SN/ATimingSimpleCPU::write(uint16_t data, Addr addr, 5942623SN/A unsigned flags, uint64_t *res); 5952623SN/A 5962623SN/Atemplate 5972623SN/AFault 5982623SN/ATimingSimpleCPU::write(uint8_t data, Addr addr, 5992623SN/A unsigned flags, uint64_t *res); 6002623SN/A 6012623SN/A#endif //DOXYGEN_SHOULD_SKIP_THIS 6022623SN/A 6032623SN/Atemplate<> 6042623SN/AFault 6052623SN/ATimingSimpleCPU::write(double data, Addr addr, unsigned flags, uint64_t *res) 6062623SN/A{ 6072623SN/A return write(*(uint64_t*)&data, addr, flags, res); 6082623SN/A} 6092623SN/A 6102623SN/Atemplate<> 6112623SN/AFault 6122623SN/ATimingSimpleCPU::write(float data, Addr addr, unsigned flags, uint64_t *res) 6132623SN/A{ 6142623SN/A return write(*(uint32_t*)&data, addr, flags, res); 6152623SN/A} 6162623SN/A 6172623SN/A 6182623SN/Atemplate<> 6192623SN/AFault 6202623SN/ATimingSimpleCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res) 6212623SN/A{ 6222623SN/A return write((uint32_t)data, addr, flags, res); 6232623SN/A} 6242623SN/A 6252623SN/A 6262623SN/Avoid 6272623SN/ATimingSimpleCPU::fetch() 6282623SN/A{ 6295221Ssaidi@eecs.umich.edu DPRINTF(SimpleCPU, "Fetch\n"); 6305221Ssaidi@eecs.umich.edu 6313387Sgblack@eecs.umich.edu if (!curStaticInst || !curStaticInst->isDelayedCommit()) 6323387Sgblack@eecs.umich.edu checkForInterrupts(); 6332631SN/A 6345348Ssaidi@eecs.umich.edu checkPcEventQueue(); 6355348Ssaidi@eecs.umich.edu 6365669Sgblack@eecs.umich.edu bool fromRom = isRomMicroPC(thread->readMicroPC()); 6372623SN/A 6385669Sgblack@eecs.umich.edu if (!fromRom) { 6395669Sgblack@eecs.umich.edu Request *ifetch_req = new Request(); 6405712Shsul@eecs.umich.edu ifetch_req->setThreadContext(_cpuId, /* thread ID */ 0); 6415669Sgblack@eecs.umich.edu Fault fault = setupFetchRequest(ifetch_req); 6422623SN/A 6435669Sgblack@eecs.umich.edu ifetch_pkt = new Packet(ifetch_req, MemCmd::ReadReq, Packet::Broadcast); 6445669Sgblack@eecs.umich.edu ifetch_pkt->dataStatic(&inst); 6455669Sgblack@eecs.umich.edu 6465669Sgblack@eecs.umich.edu if (fault == NoFault) { 6475669Sgblack@eecs.umich.edu if (!icachePort.sendTiming(ifetch_pkt)) { 6485669Sgblack@eecs.umich.edu // Need to wait for retry 6495669Sgblack@eecs.umich.edu _status = IcacheRetry; 6505669Sgblack@eecs.umich.edu } else { 6515669Sgblack@eecs.umich.edu // Need to wait for cache to respond 6525669Sgblack@eecs.umich.edu _status = IcacheWaitResponse; 6535669Sgblack@eecs.umich.edu // ownership of packet transferred to memory system 6545669Sgblack@eecs.umich.edu ifetch_pkt = NULL; 6555669Sgblack@eecs.umich.edu } 6562623SN/A } else { 6575669Sgblack@eecs.umich.edu delete ifetch_req; 6585669Sgblack@eecs.umich.edu delete ifetch_pkt; 6595669Sgblack@eecs.umich.edu // fetch fault: advance directly to next instruction (fault handler) 6605669Sgblack@eecs.umich.edu advanceInst(fault); 6612623SN/A } 6622623SN/A } else { 6635669Sgblack@eecs.umich.edu _status = IcacheWaitResponse; 6645669Sgblack@eecs.umich.edu completeIfetch(NULL); 6652623SN/A } 6663222Sktlim@umich.edu 6675099Ssaidi@eecs.umich.edu numCycles += tickToCycles(curTick - previousTick); 6683222Sktlim@umich.edu previousTick = curTick; 6692623SN/A} 6702623SN/A 6712623SN/A 6722623SN/Avoid 6732644Sstever@eecs.umich.eduTimingSimpleCPU::advanceInst(Fault fault) 6742623SN/A{ 6755726Sgblack@eecs.umich.edu if (fault != NoFault || !stayAtPC) 6765726Sgblack@eecs.umich.edu advancePC(fault); 6772623SN/A 6782631SN/A if (_status == Running) { 6792631SN/A // kick off fetch of next instruction... callback from icache 6802631SN/A // response will cause that instruction to be executed, 6812631SN/A // keeping the CPU running. 6822631SN/A fetch(); 6832631SN/A } 6842623SN/A} 6852623SN/A 6862623SN/A 6872623SN/Avoid 6883349Sbinkertn@umich.eduTimingSimpleCPU::completeIfetch(PacketPtr pkt) 6892623SN/A{ 6905221Ssaidi@eecs.umich.edu DPRINTF(SimpleCPU, "Complete ICache Fetch\n"); 6915221Ssaidi@eecs.umich.edu 6922623SN/A // received a response from the icache: execute the received 6932623SN/A // instruction 6945669Sgblack@eecs.umich.edu 6955669Sgblack@eecs.umich.edu assert(!pkt || !pkt->isError()); 6962623SN/A assert(_status == IcacheWaitResponse); 6972798Sktlim@umich.edu 6982623SN/A _status = Running; 6992644Sstever@eecs.umich.edu 7005099Ssaidi@eecs.umich.edu numCycles += tickToCycles(curTick - previousTick); 7013222Sktlim@umich.edu previousTick = curTick; 7023222Sktlim@umich.edu 7032839Sktlim@umich.edu if (getState() == SimObject::Draining) { 7045669Sgblack@eecs.umich.edu if (pkt) { 7055669Sgblack@eecs.umich.edu delete pkt->req; 7065669Sgblack@eecs.umich.edu delete pkt; 7075669Sgblack@eecs.umich.edu } 7083658Sktlim@umich.edu 7092839Sktlim@umich.edu completeDrain(); 7102798Sktlim@umich.edu return; 7112798Sktlim@umich.edu } 7122798Sktlim@umich.edu 7132623SN/A preExecute(); 7145726Sgblack@eecs.umich.edu if (curStaticInst && 7155726Sgblack@eecs.umich.edu curStaticInst->isMemRef() && !curStaticInst->isDataPrefetch()) { 7162623SN/A // load or store: just send to dcache 7172623SN/A Fault fault = curStaticInst->initiateAcc(this, traceData); 7183170Sstever@eecs.umich.edu if (_status != Running) { 7193170Sstever@eecs.umich.edu // instruction will complete in dcache response callback 7203170Sstever@eecs.umich.edu assert(_status == DcacheWaitResponse || _status == DcacheRetry); 7213170Sstever@eecs.umich.edu assert(fault == NoFault); 7222644Sstever@eecs.umich.edu } else { 7233170Sstever@eecs.umich.edu if (fault == NoFault) { 7245335Shines@cs.fsu.edu // Note that ARM can have NULL packets if the instruction gets 7255335Shines@cs.fsu.edu // squashed due to predication 7263170Sstever@eecs.umich.edu // early fail on store conditional: complete now 7275335Shines@cs.fsu.edu assert(dcache_pkt != NULL || THE_ISA == ARM_ISA); 7285335Shines@cs.fsu.edu 7293170Sstever@eecs.umich.edu fault = curStaticInst->completeAcc(dcache_pkt, this, 7303170Sstever@eecs.umich.edu traceData); 7315335Shines@cs.fsu.edu if (dcache_pkt != NULL) 7325335Shines@cs.fsu.edu { 7335335Shines@cs.fsu.edu delete dcache_pkt->req; 7345335Shines@cs.fsu.edu delete dcache_pkt; 7355335Shines@cs.fsu.edu dcache_pkt = NULL; 7365335Shines@cs.fsu.edu } 7374998Sgblack@eecs.umich.edu 7384998Sgblack@eecs.umich.edu // keep an instruction count 7394998Sgblack@eecs.umich.edu if (fault == NoFault) 7404998Sgblack@eecs.umich.edu countInst(); 7415001Sgblack@eecs.umich.edu } else if (traceData) { 7425001Sgblack@eecs.umich.edu // If there was a fault, we shouldn't trace this instruction. 7435001Sgblack@eecs.umich.edu delete traceData; 7445001Sgblack@eecs.umich.edu traceData = NULL; 7453170Sstever@eecs.umich.edu } 7464998Sgblack@eecs.umich.edu 7472644Sstever@eecs.umich.edu postExecute(); 7485103Ssaidi@eecs.umich.edu // @todo remove me after debugging with legion done 7495103Ssaidi@eecs.umich.edu if (curStaticInst && (!curStaticInst->isMicroop() || 7505103Ssaidi@eecs.umich.edu curStaticInst->isFirstMicroop())) 7515103Ssaidi@eecs.umich.edu instCnt++; 7522644Sstever@eecs.umich.edu advanceInst(fault); 7532644Sstever@eecs.umich.edu } 7545726Sgblack@eecs.umich.edu } else if (curStaticInst) { 7552623SN/A // non-memory instruction: execute completely now 7562623SN/A Fault fault = curStaticInst->execute(this, traceData); 7574998Sgblack@eecs.umich.edu 7584998Sgblack@eecs.umich.edu // keep an instruction count 7594998Sgblack@eecs.umich.edu if (fault == NoFault) 7604998Sgblack@eecs.umich.edu countInst(); 7615001Sgblack@eecs.umich.edu else if (traceData) { 7625001Sgblack@eecs.umich.edu // If there was a fault, we shouldn't trace this instruction. 7635001Sgblack@eecs.umich.edu delete traceData; 7645001Sgblack@eecs.umich.edu traceData = NULL; 7655001Sgblack@eecs.umich.edu } 7664998Sgblack@eecs.umich.edu 7672644Sstever@eecs.umich.edu postExecute(); 7685103Ssaidi@eecs.umich.edu // @todo remove me after debugging with legion done 7695103Ssaidi@eecs.umich.edu if (curStaticInst && (!curStaticInst->isMicroop() || 7705103Ssaidi@eecs.umich.edu curStaticInst->isFirstMicroop())) 7715103Ssaidi@eecs.umich.edu instCnt++; 7722644Sstever@eecs.umich.edu advanceInst(fault); 7735726Sgblack@eecs.umich.edu } else { 7745726Sgblack@eecs.umich.edu advanceInst(NoFault); 7752623SN/A } 7763658Sktlim@umich.edu 7775669Sgblack@eecs.umich.edu if (pkt) { 7785669Sgblack@eecs.umich.edu delete pkt->req; 7795669Sgblack@eecs.umich.edu delete pkt; 7805669Sgblack@eecs.umich.edu } 7812623SN/A} 7822623SN/A 7832948Ssaidi@eecs.umich.eduvoid 7842948Ssaidi@eecs.umich.eduTimingSimpleCPU::IcachePort::ITickEvent::process() 7852948Ssaidi@eecs.umich.edu{ 7862948Ssaidi@eecs.umich.edu cpu->completeIfetch(pkt); 7872948Ssaidi@eecs.umich.edu} 7882623SN/A 7892623SN/Abool 7903349Sbinkertn@umich.eduTimingSimpleCPU::IcachePort::recvTiming(PacketPtr pkt) 7912623SN/A{ 7924986Ssaidi@eecs.umich.edu if (pkt->isResponse() && !pkt->wasNacked()) { 7933310Srdreslin@umich.edu // delay processing of returned data until next CPU clock edge 7944584Ssaidi@eecs.umich.edu Tick next_tick = cpu->nextCycle(curTick); 7952948Ssaidi@eecs.umich.edu 7963495Sktlim@umich.edu if (next_tick == curTick) 7973310Srdreslin@umich.edu cpu->completeIfetch(pkt); 7983310Srdreslin@umich.edu else 7993495Sktlim@umich.edu tickEvent.schedule(pkt, next_tick); 8002948Ssaidi@eecs.umich.edu 8013310Srdreslin@umich.edu return true; 8023310Srdreslin@umich.edu } 8034870Sstever@eecs.umich.edu else if (pkt->wasNacked()) { 8044433Ssaidi@eecs.umich.edu assert(cpu->_status == IcacheWaitResponse); 8054433Ssaidi@eecs.umich.edu pkt->reinitNacked(); 8064433Ssaidi@eecs.umich.edu if (!sendTiming(pkt)) { 8074433Ssaidi@eecs.umich.edu cpu->_status = IcacheRetry; 8084433Ssaidi@eecs.umich.edu cpu->ifetch_pkt = pkt; 8094433Ssaidi@eecs.umich.edu } 8103310Srdreslin@umich.edu } 8114433Ssaidi@eecs.umich.edu //Snooping a Coherence Request, do nothing 8124433Ssaidi@eecs.umich.edu return true; 8132623SN/A} 8142623SN/A 8152657Ssaidi@eecs.umich.eduvoid 8162623SN/ATimingSimpleCPU::IcachePort::recvRetry() 8172623SN/A{ 8182623SN/A // we shouldn't get a retry unless we have a packet that we're 8192623SN/A // waiting to transmit 8202623SN/A assert(cpu->ifetch_pkt != NULL); 8212623SN/A assert(cpu->_status == IcacheRetry); 8223349Sbinkertn@umich.edu PacketPtr tmp = cpu->ifetch_pkt; 8232657Ssaidi@eecs.umich.edu if (sendTiming(tmp)) { 8242657Ssaidi@eecs.umich.edu cpu->_status = IcacheWaitResponse; 8252657Ssaidi@eecs.umich.edu cpu->ifetch_pkt = NULL; 8262657Ssaidi@eecs.umich.edu } 8272623SN/A} 8282623SN/A 8292623SN/Avoid 8303349Sbinkertn@umich.eduTimingSimpleCPU::completeDataAccess(PacketPtr pkt) 8312623SN/A{ 8322623SN/A // received a response from the dcache: complete the load or store 8332623SN/A // instruction 8344870Sstever@eecs.umich.edu assert(!pkt->isError()); 8352623SN/A 8365099Ssaidi@eecs.umich.edu numCycles += tickToCycles(curTick - previousTick); 8373222Sktlim@umich.edu previousTick = curTick; 8383184Srdreslin@umich.edu 8395728Sgblack@eecs.umich.edu if (pkt->senderState) { 8405728Sgblack@eecs.umich.edu SplitFragmentSenderState * send_state = 8415728Sgblack@eecs.umich.edu dynamic_cast<SplitFragmentSenderState *>(pkt->senderState); 8425728Sgblack@eecs.umich.edu assert(send_state); 8435728Sgblack@eecs.umich.edu delete pkt->req; 8445728Sgblack@eecs.umich.edu delete pkt; 8455728Sgblack@eecs.umich.edu PacketPtr big_pkt = send_state->bigPkt; 8465728Sgblack@eecs.umich.edu delete send_state; 8475728Sgblack@eecs.umich.edu 8485728Sgblack@eecs.umich.edu SplitMainSenderState * main_send_state = 8495728Sgblack@eecs.umich.edu dynamic_cast<SplitMainSenderState *>(big_pkt->senderState); 8505728Sgblack@eecs.umich.edu assert(main_send_state); 8515728Sgblack@eecs.umich.edu // Record the fact that this packet is no longer outstanding. 8525728Sgblack@eecs.umich.edu assert(main_send_state->outstanding != 0); 8535728Sgblack@eecs.umich.edu main_send_state->outstanding--; 8545728Sgblack@eecs.umich.edu 8555728Sgblack@eecs.umich.edu if (main_send_state->outstanding) { 8565728Sgblack@eecs.umich.edu return; 8575728Sgblack@eecs.umich.edu } else { 8585728Sgblack@eecs.umich.edu delete main_send_state; 8595728Sgblack@eecs.umich.edu big_pkt->senderState = NULL; 8605728Sgblack@eecs.umich.edu pkt = big_pkt; 8615728Sgblack@eecs.umich.edu } 8625728Sgblack@eecs.umich.edu } 8635728Sgblack@eecs.umich.edu 8645728Sgblack@eecs.umich.edu assert(_status == DcacheWaitResponse); 8655728Sgblack@eecs.umich.edu _status = Running; 8665728Sgblack@eecs.umich.edu 8672623SN/A Fault fault = curStaticInst->completeAcc(pkt, this, traceData); 8682623SN/A 8694998Sgblack@eecs.umich.edu // keep an instruction count 8704998Sgblack@eecs.umich.edu if (fault == NoFault) 8714998Sgblack@eecs.umich.edu countInst(); 8725001Sgblack@eecs.umich.edu else if (traceData) { 8735001Sgblack@eecs.umich.edu // If there was a fault, we shouldn't trace this instruction. 8745001Sgblack@eecs.umich.edu delete traceData; 8755001Sgblack@eecs.umich.edu traceData = NULL; 8765001Sgblack@eecs.umich.edu } 8774998Sgblack@eecs.umich.edu 8785507Sstever@gmail.com // the locked flag may be cleared on the response packet, so check 8795507Sstever@gmail.com // pkt->req and not pkt to see if it was a load-locked 8805507Sstever@gmail.com if (pkt->isRead() && pkt->req->isLocked()) { 8813170Sstever@eecs.umich.edu TheISA::handleLockedRead(thread, pkt->req); 8823170Sstever@eecs.umich.edu } 8833170Sstever@eecs.umich.edu 8842644Sstever@eecs.umich.edu delete pkt->req; 8852644Sstever@eecs.umich.edu delete pkt; 8862644Sstever@eecs.umich.edu 8873184Srdreslin@umich.edu postExecute(); 8883227Sktlim@umich.edu 8893201Shsul@eecs.umich.edu if (getState() == SimObject::Draining) { 8903201Shsul@eecs.umich.edu advancePC(fault); 8913201Shsul@eecs.umich.edu completeDrain(); 8923201Shsul@eecs.umich.edu 8933201Shsul@eecs.umich.edu return; 8943201Shsul@eecs.umich.edu } 8953201Shsul@eecs.umich.edu 8962644Sstever@eecs.umich.edu advanceInst(fault); 8972623SN/A} 8982623SN/A 8992623SN/A 9002798Sktlim@umich.eduvoid 9012839Sktlim@umich.eduTimingSimpleCPU::completeDrain() 9022798Sktlim@umich.edu{ 9032839Sktlim@umich.edu DPRINTF(Config, "Done draining\n"); 9042901Ssaidi@eecs.umich.edu changeState(SimObject::Drained); 9052839Sktlim@umich.edu drainEvent->process(); 9062798Sktlim@umich.edu} 9072623SN/A 9084192Sktlim@umich.eduvoid 9094192Sktlim@umich.eduTimingSimpleCPU::DcachePort::setPeer(Port *port) 9104192Sktlim@umich.edu{ 9114192Sktlim@umich.edu Port::setPeer(port); 9124192Sktlim@umich.edu 9134192Sktlim@umich.edu#if FULL_SYSTEM 9144192Sktlim@umich.edu // Update the ThreadContext's memory ports (Functional/Virtual 9154192Sktlim@umich.edu // Ports) 9165497Ssaidi@eecs.umich.edu cpu->tcBase()->connectMemPorts(cpu->tcBase()); 9174192Sktlim@umich.edu#endif 9184192Sktlim@umich.edu} 9194192Sktlim@umich.edu 9202623SN/Abool 9213349Sbinkertn@umich.eduTimingSimpleCPU::DcachePort::recvTiming(PacketPtr pkt) 9222623SN/A{ 9234986Ssaidi@eecs.umich.edu if (pkt->isResponse() && !pkt->wasNacked()) { 9243310Srdreslin@umich.edu // delay processing of returned data until next CPU clock edge 9254584Ssaidi@eecs.umich.edu Tick next_tick = cpu->nextCycle(curTick); 9262948Ssaidi@eecs.umich.edu 9275728Sgblack@eecs.umich.edu if (next_tick == curTick) { 9283310Srdreslin@umich.edu cpu->completeDataAccess(pkt); 9295728Sgblack@eecs.umich.edu } else { 9303495Sktlim@umich.edu tickEvent.schedule(pkt, next_tick); 9315728Sgblack@eecs.umich.edu } 9322948Ssaidi@eecs.umich.edu 9333310Srdreslin@umich.edu return true; 9343310Srdreslin@umich.edu } 9354870Sstever@eecs.umich.edu else if (pkt->wasNacked()) { 9364433Ssaidi@eecs.umich.edu assert(cpu->_status == DcacheWaitResponse); 9374433Ssaidi@eecs.umich.edu pkt->reinitNacked(); 9384433Ssaidi@eecs.umich.edu if (!sendTiming(pkt)) { 9394433Ssaidi@eecs.umich.edu cpu->_status = DcacheRetry; 9404433Ssaidi@eecs.umich.edu cpu->dcache_pkt = pkt; 9414433Ssaidi@eecs.umich.edu } 9423310Srdreslin@umich.edu } 9434433Ssaidi@eecs.umich.edu //Snooping a Coherence Request, do nothing 9444433Ssaidi@eecs.umich.edu return true; 9452948Ssaidi@eecs.umich.edu} 9462948Ssaidi@eecs.umich.edu 9472948Ssaidi@eecs.umich.eduvoid 9482948Ssaidi@eecs.umich.eduTimingSimpleCPU::DcachePort::DTickEvent::process() 9492948Ssaidi@eecs.umich.edu{ 9502630SN/A cpu->completeDataAccess(pkt); 9512623SN/A} 9522623SN/A 9532657Ssaidi@eecs.umich.eduvoid 9542623SN/ATimingSimpleCPU::DcachePort::recvRetry() 9552623SN/A{ 9562623SN/A // we shouldn't get a retry unless we have a packet that we're 9572623SN/A // waiting to transmit 9582623SN/A assert(cpu->dcache_pkt != NULL); 9592623SN/A assert(cpu->_status == DcacheRetry); 9603349Sbinkertn@umich.edu PacketPtr tmp = cpu->dcache_pkt; 9615728Sgblack@eecs.umich.edu if (tmp->senderState) { 9625728Sgblack@eecs.umich.edu // This is a packet from a split access. 9635728Sgblack@eecs.umich.edu SplitFragmentSenderState * send_state = 9645728Sgblack@eecs.umich.edu dynamic_cast<SplitFragmentSenderState *>(tmp->senderState); 9655728Sgblack@eecs.umich.edu assert(send_state); 9665728Sgblack@eecs.umich.edu PacketPtr big_pkt = send_state->bigPkt; 9675728Sgblack@eecs.umich.edu 9685728Sgblack@eecs.umich.edu SplitMainSenderState * main_send_state = 9695728Sgblack@eecs.umich.edu dynamic_cast<SplitMainSenderState *>(big_pkt->senderState); 9705728Sgblack@eecs.umich.edu assert(main_send_state); 9715728Sgblack@eecs.umich.edu 9725728Sgblack@eecs.umich.edu if (sendTiming(tmp)) { 9735728Sgblack@eecs.umich.edu // If we were able to send without retrying, record that fact 9745728Sgblack@eecs.umich.edu // and try sending the other fragment. 9755728Sgblack@eecs.umich.edu send_state->clearFromParent(); 9765728Sgblack@eecs.umich.edu int other_index = main_send_state->getPendingFragment(); 9775728Sgblack@eecs.umich.edu if (other_index > 0) { 9785728Sgblack@eecs.umich.edu tmp = main_send_state->fragments[other_index]; 9795728Sgblack@eecs.umich.edu cpu->dcache_pkt = tmp; 9805728Sgblack@eecs.umich.edu if ((big_pkt->isRead() && cpu->handleReadPacket(tmp)) || 9815728Sgblack@eecs.umich.edu (big_pkt->isWrite() && cpu->handleWritePacket())) { 9825728Sgblack@eecs.umich.edu main_send_state->fragments[other_index] = NULL; 9835728Sgblack@eecs.umich.edu } 9845728Sgblack@eecs.umich.edu } else { 9855728Sgblack@eecs.umich.edu cpu->_status = DcacheWaitResponse; 9865728Sgblack@eecs.umich.edu // memory system takes ownership of packet 9875728Sgblack@eecs.umich.edu cpu->dcache_pkt = NULL; 9885728Sgblack@eecs.umich.edu } 9895728Sgblack@eecs.umich.edu } 9905728Sgblack@eecs.umich.edu } else if (sendTiming(tmp)) { 9912657Ssaidi@eecs.umich.edu cpu->_status = DcacheWaitResponse; 9923170Sstever@eecs.umich.edu // memory system takes ownership of packet 9932657Ssaidi@eecs.umich.edu cpu->dcache_pkt = NULL; 9942657Ssaidi@eecs.umich.edu } 9952623SN/A} 9962623SN/A 9975606Snate@binkert.orgTimingSimpleCPU::IprEvent::IprEvent(Packet *_pkt, TimingSimpleCPU *_cpu, 9985606Snate@binkert.org Tick t) 9995606Snate@binkert.org : pkt(_pkt), cpu(_cpu) 10005103Ssaidi@eecs.umich.edu{ 10015606Snate@binkert.org cpu->schedule(this, t); 10025103Ssaidi@eecs.umich.edu} 10035103Ssaidi@eecs.umich.edu 10045103Ssaidi@eecs.umich.eduvoid 10055103Ssaidi@eecs.umich.eduTimingSimpleCPU::IprEvent::process() 10065103Ssaidi@eecs.umich.edu{ 10075103Ssaidi@eecs.umich.edu cpu->completeDataAccess(pkt); 10085103Ssaidi@eecs.umich.edu} 10095103Ssaidi@eecs.umich.edu 10105103Ssaidi@eecs.umich.educonst char * 10115336Shines@cs.fsu.eduTimingSimpleCPU::IprEvent::description() const 10125103Ssaidi@eecs.umich.edu{ 10135103Ssaidi@eecs.umich.edu return "Timing Simple CPU Delay IPR event"; 10145103Ssaidi@eecs.umich.edu} 10155103Ssaidi@eecs.umich.edu 10162623SN/A 10175315Sstever@gmail.comvoid 10185315Sstever@gmail.comTimingSimpleCPU::printAddr(Addr a) 10195315Sstever@gmail.com{ 10205315Sstever@gmail.com dcachePort.printAddr(a); 10215315Sstever@gmail.com} 10225315Sstever@gmail.com 10235315Sstever@gmail.com 10242623SN/A//////////////////////////////////////////////////////////////////////// 10252623SN/A// 10262623SN/A// TimingSimpleCPU Simulation Object 10272623SN/A// 10284762Snate@binkert.orgTimingSimpleCPU * 10294762Snate@binkert.orgTimingSimpleCPUParams::create() 10302623SN/A{ 10315529Snate@binkert.org numThreads = 1; 10325529Snate@binkert.org#if !FULL_SYSTEM 10334762Snate@binkert.org if (workload.size() != 1) 10344762Snate@binkert.org panic("only one workload allowed"); 10352623SN/A#endif 10365529Snate@binkert.org return new TimingSimpleCPU(this); 10372623SN/A} 1038