timing.cc revision 5710
12623SN/A/* 22623SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 32623SN/A * All rights reserved. 42623SN/A * 52623SN/A * Redistribution and use in source and binary forms, with or without 62623SN/A * modification, are permitted provided that the following conditions are 72623SN/A * met: redistributions of source code must retain the above copyright 82623SN/A * notice, this list of conditions and the following disclaimer; 92623SN/A * redistributions in binary form must reproduce the above copyright 102623SN/A * notice, this list of conditions and the following disclaimer in the 112623SN/A * documentation and/or other materials provided with the distribution; 122623SN/A * neither the name of the copyright holders nor the names of its 132623SN/A * contributors may be used to endorse or promote products derived from 142623SN/A * this software without specific prior written permission. 152623SN/A * 162623SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172623SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182623SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192623SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202623SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212623SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222623SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232623SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242623SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252623SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262623SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 292623SN/A */ 302623SN/A 313170Sstever@eecs.umich.edu#include "arch/locked_mem.hh" 325103Ssaidi@eecs.umich.edu#include "arch/mmaped_ipr.hh" 332623SN/A#include "arch/utility.hh" 344040Ssaidi@eecs.umich.edu#include "base/bigint.hh" 352623SN/A#include "cpu/exetrace.hh" 362623SN/A#include "cpu/simple/timing.hh" 373348Sbinkertn@umich.edu#include "mem/packet.hh" 383348Sbinkertn@umich.edu#include "mem/packet_access.hh" 394762Snate@binkert.org#include "params/TimingSimpleCPU.hh" 402901Ssaidi@eecs.umich.edu#include "sim/system.hh" 412623SN/A 422623SN/Ausing namespace std; 432623SN/Ausing namespace TheISA; 442623SN/A 452856Srdreslin@umich.eduPort * 462856Srdreslin@umich.eduTimingSimpleCPU::getPort(const std::string &if_name, int idx) 472856Srdreslin@umich.edu{ 482856Srdreslin@umich.edu if (if_name == "dcache_port") 492856Srdreslin@umich.edu return &dcachePort; 502856Srdreslin@umich.edu else if (if_name == "icache_port") 512856Srdreslin@umich.edu return &icachePort; 522856Srdreslin@umich.edu else 532856Srdreslin@umich.edu panic("No Such Port\n"); 542856Srdreslin@umich.edu} 552623SN/A 562623SN/Avoid 572623SN/ATimingSimpleCPU::init() 582623SN/A{ 592623SN/A BaseCPU::init(); 605310Ssaidi@eecs.umich.edu cpuId = tc->readCpuId(); 612623SN/A#if FULL_SYSTEM 622680Sktlim@umich.edu for (int i = 0; i < threadContexts.size(); ++i) { 632680Sktlim@umich.edu ThreadContext *tc = threadContexts[i]; 642623SN/A 652623SN/A // initialize CPU, including PC 665310Ssaidi@eecs.umich.edu TheISA::initCPU(tc, cpuId); 672623SN/A } 682623SN/A#endif 692623SN/A} 702623SN/A 712623SN/ATick 723349Sbinkertn@umich.eduTimingSimpleCPU::CpuPort::recvAtomic(PacketPtr pkt) 732623SN/A{ 742623SN/A panic("TimingSimpleCPU doesn't expect recvAtomic callback!"); 752623SN/A return curTick; 762623SN/A} 772623SN/A 782623SN/Avoid 793349Sbinkertn@umich.eduTimingSimpleCPU::CpuPort::recvFunctional(PacketPtr pkt) 802623SN/A{ 813184Srdreslin@umich.edu //No internal storage to update, jusst return 823184Srdreslin@umich.edu return; 832623SN/A} 842623SN/A 852623SN/Avoid 862623SN/ATimingSimpleCPU::CpuPort::recvStatusChange(Status status) 872623SN/A{ 883647Srdreslin@umich.edu if (status == RangeChange) { 893647Srdreslin@umich.edu if (!snoopRangeSent) { 903647Srdreslin@umich.edu snoopRangeSent = true; 913647Srdreslin@umich.edu sendStatusChange(Port::RangeChange); 923647Srdreslin@umich.edu } 932631SN/A return; 943647Srdreslin@umich.edu } 952631SN/A 962623SN/A panic("TimingSimpleCPU doesn't expect recvStatusChange callback!"); 972623SN/A} 982623SN/A 992948Ssaidi@eecs.umich.edu 1002948Ssaidi@eecs.umich.eduvoid 1013349Sbinkertn@umich.eduTimingSimpleCPU::CpuPort::TickEvent::schedule(PacketPtr _pkt, Tick t) 1022948Ssaidi@eecs.umich.edu{ 1032948Ssaidi@eecs.umich.edu pkt = _pkt; 1045606Snate@binkert.org cpu->schedule(this, t); 1052948Ssaidi@eecs.umich.edu} 1062948Ssaidi@eecs.umich.edu 1075529Snate@binkert.orgTimingSimpleCPU::TimingSimpleCPU(TimingSimpleCPUParams *p) 1085710Scws3k@cs.virginia.edu : BaseSimpleCPU(p), icachePort(this, p->clock), dcachePort(this, p->clock), fetchEvent(this) 1092623SN/A{ 1102623SN/A _status = Idle; 1113647Srdreslin@umich.edu 1123647Srdreslin@umich.edu icachePort.snoopRangeSent = false; 1133647Srdreslin@umich.edu dcachePort.snoopRangeSent = false; 1143647Srdreslin@umich.edu 1152623SN/A ifetch_pkt = dcache_pkt = NULL; 1162839Sktlim@umich.edu drainEvent = NULL; 1173222Sktlim@umich.edu previousTick = 0; 1182901Ssaidi@eecs.umich.edu changeState(SimObject::Running); 1192623SN/A} 1202623SN/A 1212623SN/A 1222623SN/ATimingSimpleCPU::~TimingSimpleCPU() 1232623SN/A{ 1242623SN/A} 1252623SN/A 1262623SN/Avoid 1272623SN/ATimingSimpleCPU::serialize(ostream &os) 1282623SN/A{ 1292915Sktlim@umich.edu SimObject::State so_state = SimObject::getState(); 1302915Sktlim@umich.edu SERIALIZE_ENUM(so_state); 1312623SN/A BaseSimpleCPU::serialize(os); 1322623SN/A} 1332623SN/A 1342623SN/Avoid 1352623SN/ATimingSimpleCPU::unserialize(Checkpoint *cp, const string §ion) 1362623SN/A{ 1372915Sktlim@umich.edu SimObject::State so_state; 1382915Sktlim@umich.edu UNSERIALIZE_ENUM(so_state); 1392623SN/A BaseSimpleCPU::unserialize(cp, section); 1402798Sktlim@umich.edu} 1412798Sktlim@umich.edu 1422901Ssaidi@eecs.umich.eduunsigned int 1432839Sktlim@umich.eduTimingSimpleCPU::drain(Event *drain_event) 1442798Sktlim@umich.edu{ 1452839Sktlim@umich.edu // TimingSimpleCPU is ready to drain if it's not waiting for 1462798Sktlim@umich.edu // an access to complete. 1475496Ssaidi@eecs.umich.edu if (_status == Idle || _status == Running || _status == SwitchedOut) { 1482901Ssaidi@eecs.umich.edu changeState(SimObject::Drained); 1492901Ssaidi@eecs.umich.edu return 0; 1502798Sktlim@umich.edu } else { 1512839Sktlim@umich.edu changeState(SimObject::Draining); 1522839Sktlim@umich.edu drainEvent = drain_event; 1532901Ssaidi@eecs.umich.edu return 1; 1542798Sktlim@umich.edu } 1552623SN/A} 1562623SN/A 1572623SN/Avoid 1582798Sktlim@umich.eduTimingSimpleCPU::resume() 1592623SN/A{ 1605221Ssaidi@eecs.umich.edu DPRINTF(SimpleCPU, "Resume\n"); 1612798Sktlim@umich.edu if (_status != SwitchedOut && _status != Idle) { 1624762Snate@binkert.org assert(system->getMemoryMode() == Enums::timing); 1633201Shsul@eecs.umich.edu 1645710Scws3k@cs.virginia.edu if (fetchEvent.scheduled()) 1655710Scws3k@cs.virginia.edu deschedule(fetchEvent); 1662915Sktlim@umich.edu 1675710Scws3k@cs.virginia.edu schedule(fetchEvent, nextCycle()); 1682623SN/A } 1692798Sktlim@umich.edu 1702901Ssaidi@eecs.umich.edu changeState(SimObject::Running); 1712798Sktlim@umich.edu} 1722798Sktlim@umich.edu 1732798Sktlim@umich.eduvoid 1742798Sktlim@umich.eduTimingSimpleCPU::switchOut() 1752798Sktlim@umich.edu{ 1765496Ssaidi@eecs.umich.edu assert(_status == Running || _status == Idle); 1772798Sktlim@umich.edu _status = SwitchedOut; 1785099Ssaidi@eecs.umich.edu numCycles += tickToCycles(curTick - previousTick); 1792867Sktlim@umich.edu 1802867Sktlim@umich.edu // If we've been scheduled to resume but are then told to switch out, 1812867Sktlim@umich.edu // we'll need to cancel it. 1825710Scws3k@cs.virginia.edu if (fetchEvent.scheduled()) 1835606Snate@binkert.org deschedule(fetchEvent); 1842623SN/A} 1852623SN/A 1862623SN/A 1872623SN/Avoid 1882623SN/ATimingSimpleCPU::takeOverFrom(BaseCPU *oldCPU) 1892623SN/A{ 1904192Sktlim@umich.edu BaseCPU::takeOverFrom(oldCPU, &icachePort, &dcachePort); 1912623SN/A 1922680Sktlim@umich.edu // if any of this CPU's ThreadContexts are active, mark the CPU as 1932623SN/A // running and schedule its tick event. 1942680Sktlim@umich.edu for (int i = 0; i < threadContexts.size(); ++i) { 1952680Sktlim@umich.edu ThreadContext *tc = threadContexts[i]; 1962680Sktlim@umich.edu if (tc->status() == ThreadContext::Active && _status != Running) { 1972623SN/A _status = Running; 1982623SN/A break; 1992623SN/A } 2002623SN/A } 2013201Shsul@eecs.umich.edu 2023201Shsul@eecs.umich.edu if (_status != Running) { 2033201Shsul@eecs.umich.edu _status = Idle; 2043201Shsul@eecs.umich.edu } 2055169Ssaidi@eecs.umich.edu assert(threadContexts.size() == 1); 2065169Ssaidi@eecs.umich.edu cpuId = tc->readCpuId(); 2075101Ssaidi@eecs.umich.edu previousTick = curTick; 2082623SN/A} 2092623SN/A 2102623SN/A 2112623SN/Avoid 2122623SN/ATimingSimpleCPU::activateContext(int thread_num, int delay) 2132623SN/A{ 2145221Ssaidi@eecs.umich.edu DPRINTF(SimpleCPU, "ActivateContext %d (%d cycles)\n", thread_num, delay); 2155221Ssaidi@eecs.umich.edu 2162623SN/A assert(thread_num == 0); 2172683Sktlim@umich.edu assert(thread); 2182623SN/A 2192623SN/A assert(_status == Idle); 2202623SN/A 2212623SN/A notIdleFraction++; 2222623SN/A _status = Running; 2233686Sktlim@umich.edu 2242623SN/A // kick things off by initiating the fetch of the next instruction 2255606Snate@binkert.org schedule(fetchEvent, nextCycle(curTick + ticks(delay))); 2262623SN/A} 2272623SN/A 2282623SN/A 2292623SN/Avoid 2302623SN/ATimingSimpleCPU::suspendContext(int thread_num) 2312623SN/A{ 2325221Ssaidi@eecs.umich.edu DPRINTF(SimpleCPU, "SuspendContext %d\n", thread_num); 2335221Ssaidi@eecs.umich.edu 2342623SN/A assert(thread_num == 0); 2352683Sktlim@umich.edu assert(thread); 2362623SN/A 2372644Sstever@eecs.umich.edu assert(_status == Running); 2382623SN/A 2392644Sstever@eecs.umich.edu // just change status to Idle... if status != Running, 2402644Sstever@eecs.umich.edu // completeInst() will not initiate fetch of next instruction. 2412623SN/A 2422623SN/A notIdleFraction--; 2432623SN/A _status = Idle; 2442623SN/A} 2452623SN/A 2462623SN/A 2472623SN/Atemplate <class T> 2482623SN/AFault 2492623SN/ATimingSimpleCPU::read(Addr addr, T &data, unsigned flags) 2502623SN/A{ 2513169Sstever@eecs.umich.edu Request *req = 2523169Sstever@eecs.umich.edu new Request(/* asid */ 0, addr, sizeof(T), flags, thread->readPC(), 2535169Ssaidi@eecs.umich.edu cpuId, /* thread ID */ 0); 2542623SN/A 2552623SN/A if (traceData) { 2563169Sstever@eecs.umich.edu traceData->setAddr(req->getVaddr()); 2572623SN/A } 2582623SN/A 2592623SN/A // translate to physical address 2603169Sstever@eecs.umich.edu Fault fault = thread->translateDataReadReq(req); 2612623SN/A 2622623SN/A // Now do the access. 2632623SN/A if (fault == NoFault) { 2643349Sbinkertn@umich.edu PacketPtr pkt = 2654878Sstever@eecs.umich.edu new Packet(req, 2664878Sstever@eecs.umich.edu (req->isLocked() ? 2674878Sstever@eecs.umich.edu MemCmd::LoadLockedReq : MemCmd::ReadReq), 2684878Sstever@eecs.umich.edu Packet::Broadcast); 2693169Sstever@eecs.umich.edu pkt->dataDynamic<T>(new T); 2702623SN/A 2715103Ssaidi@eecs.umich.edu if (req->isMmapedIpr()) { 2725103Ssaidi@eecs.umich.edu Tick delay; 2735103Ssaidi@eecs.umich.edu delay = TheISA::handleIprRead(thread->getTC(), pkt); 2745103Ssaidi@eecs.umich.edu new IprEvent(pkt, this, nextCycle(curTick + delay)); 2755103Ssaidi@eecs.umich.edu _status = DcacheWaitResponse; 2765103Ssaidi@eecs.umich.edu dcache_pkt = NULL; 2775103Ssaidi@eecs.umich.edu } else if (!dcachePort.sendTiming(pkt)) { 2782623SN/A _status = DcacheRetry; 2793169Sstever@eecs.umich.edu dcache_pkt = pkt; 2802623SN/A } else { 2812623SN/A _status = DcacheWaitResponse; 2823169Sstever@eecs.umich.edu // memory system takes ownership of packet 2832623SN/A dcache_pkt = NULL; 2842623SN/A } 2854200Ssaidi@eecs.umich.edu 2864200Ssaidi@eecs.umich.edu // This will need a new way to tell if it has a dcache attached. 2874200Ssaidi@eecs.umich.edu if (req->isUncacheable()) 2884200Ssaidi@eecs.umich.edu recordEvent("Uncached Read"); 2893658Sktlim@umich.edu } else { 2903658Sktlim@umich.edu delete req; 2912623SN/A } 2922623SN/A 2935408Sgblack@eecs.umich.edu if (traceData) { 2945408Sgblack@eecs.umich.edu traceData->setData(data); 2955408Sgblack@eecs.umich.edu } 2962623SN/A return fault; 2972623SN/A} 2982623SN/A 2995177Sgblack@eecs.umich.eduFault 3005177Sgblack@eecs.umich.eduTimingSimpleCPU::translateDataReadAddr(Addr vaddr, Addr &paddr, 3015177Sgblack@eecs.umich.edu int size, unsigned flags) 3025177Sgblack@eecs.umich.edu{ 3035177Sgblack@eecs.umich.edu Request *req = 3045177Sgblack@eecs.umich.edu new Request(0, vaddr, size, flags, thread->readPC(), cpuId, 0); 3055177Sgblack@eecs.umich.edu 3065177Sgblack@eecs.umich.edu if (traceData) { 3075177Sgblack@eecs.umich.edu traceData->setAddr(vaddr); 3085177Sgblack@eecs.umich.edu } 3095177Sgblack@eecs.umich.edu 3105177Sgblack@eecs.umich.edu Fault fault = thread->translateDataWriteReq(req); 3115177Sgblack@eecs.umich.edu 3125177Sgblack@eecs.umich.edu if (fault == NoFault) 3135177Sgblack@eecs.umich.edu paddr = req->getPaddr(); 3145177Sgblack@eecs.umich.edu 3155177Sgblack@eecs.umich.edu delete req; 3165177Sgblack@eecs.umich.edu return fault; 3175177Sgblack@eecs.umich.edu} 3185177Sgblack@eecs.umich.edu 3192623SN/A#ifndef DOXYGEN_SHOULD_SKIP_THIS 3202623SN/A 3212623SN/Atemplate 3222623SN/AFault 3234040Ssaidi@eecs.umich.eduTimingSimpleCPU::read(Addr addr, Twin64_t &data, unsigned flags); 3244040Ssaidi@eecs.umich.edu 3254040Ssaidi@eecs.umich.edutemplate 3264040Ssaidi@eecs.umich.eduFault 3274115Ssaidi@eecs.umich.eduTimingSimpleCPU::read(Addr addr, Twin32_t &data, unsigned flags); 3284115Ssaidi@eecs.umich.edu 3294115Ssaidi@eecs.umich.edutemplate 3304115Ssaidi@eecs.umich.eduFault 3312623SN/ATimingSimpleCPU::read(Addr addr, uint64_t &data, unsigned flags); 3322623SN/A 3332623SN/Atemplate 3342623SN/AFault 3352623SN/ATimingSimpleCPU::read(Addr addr, uint32_t &data, unsigned flags); 3362623SN/A 3372623SN/Atemplate 3382623SN/AFault 3392623SN/ATimingSimpleCPU::read(Addr addr, uint16_t &data, unsigned flags); 3402623SN/A 3412623SN/Atemplate 3422623SN/AFault 3432623SN/ATimingSimpleCPU::read(Addr addr, uint8_t &data, unsigned flags); 3442623SN/A 3452623SN/A#endif //DOXYGEN_SHOULD_SKIP_THIS 3462623SN/A 3472623SN/Atemplate<> 3482623SN/AFault 3492623SN/ATimingSimpleCPU::read(Addr addr, double &data, unsigned flags) 3502623SN/A{ 3512623SN/A return read(addr, *(uint64_t*)&data, flags); 3522623SN/A} 3532623SN/A 3542623SN/Atemplate<> 3552623SN/AFault 3562623SN/ATimingSimpleCPU::read(Addr addr, float &data, unsigned flags) 3572623SN/A{ 3582623SN/A return read(addr, *(uint32_t*)&data, flags); 3592623SN/A} 3602623SN/A 3612623SN/A 3622623SN/Atemplate<> 3632623SN/AFault 3642623SN/ATimingSimpleCPU::read(Addr addr, int32_t &data, unsigned flags) 3652623SN/A{ 3662623SN/A return read(addr, (uint32_t&)data, flags); 3672623SN/A} 3682623SN/A 3692623SN/A 3702623SN/Atemplate <class T> 3712623SN/AFault 3722623SN/ATimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res) 3732623SN/A{ 3743169Sstever@eecs.umich.edu Request *req = 3753169Sstever@eecs.umich.edu new Request(/* asid */ 0, addr, sizeof(T), flags, thread->readPC(), 3765169Ssaidi@eecs.umich.edu cpuId, /* thread ID */ 0); 3772623SN/A 3784040Ssaidi@eecs.umich.edu if (traceData) { 3794040Ssaidi@eecs.umich.edu traceData->setAddr(req->getVaddr()); 3804040Ssaidi@eecs.umich.edu } 3814040Ssaidi@eecs.umich.edu 3822623SN/A // translate to physical address 3833169Sstever@eecs.umich.edu Fault fault = thread->translateDataWriteReq(req); 3843169Sstever@eecs.umich.edu 3852623SN/A // Now do the access. 3862623SN/A if (fault == NoFault) { 3874878Sstever@eecs.umich.edu MemCmd cmd = MemCmd::WriteReq; // default 3883170Sstever@eecs.umich.edu bool do_access = true; // flag to suppress cache access 3893170Sstever@eecs.umich.edu 3903170Sstever@eecs.umich.edu if (req->isLocked()) { 3914878Sstever@eecs.umich.edu cmd = MemCmd::StoreCondReq; 3923170Sstever@eecs.umich.edu do_access = TheISA::handleLockedWrite(thread, req); 3934878Sstever@eecs.umich.edu } else if (req->isSwap()) { 3944878Sstever@eecs.umich.edu cmd = MemCmd::SwapReq; 3954878Sstever@eecs.umich.edu if (req->isCondSwap()) { 3964878Sstever@eecs.umich.edu assert(res); 3974878Sstever@eecs.umich.edu req->setExtraData(*res); 3984878Sstever@eecs.umich.edu } 3993170Sstever@eecs.umich.edu } 4004584Ssaidi@eecs.umich.edu 4014881Sstever@eecs.umich.edu // Note: need to allocate dcache_pkt even if do_access is 4024881Sstever@eecs.umich.edu // false, as it's used unconditionally to call completeAcc(). 4034881Sstever@eecs.umich.edu assert(dcache_pkt == NULL); 4044881Sstever@eecs.umich.edu dcache_pkt = new Packet(req, cmd, Packet::Broadcast); 4054881Sstever@eecs.umich.edu dcache_pkt->allocate(); 4064881Sstever@eecs.umich.edu dcache_pkt->set(data); 4073170Sstever@eecs.umich.edu 4083170Sstever@eecs.umich.edu if (do_access) { 4095103Ssaidi@eecs.umich.edu if (req->isMmapedIpr()) { 4105103Ssaidi@eecs.umich.edu Tick delay; 4115103Ssaidi@eecs.umich.edu dcache_pkt->set(htog(data)); 4125103Ssaidi@eecs.umich.edu delay = TheISA::handleIprWrite(thread->getTC(), dcache_pkt); 4135103Ssaidi@eecs.umich.edu new IprEvent(dcache_pkt, this, nextCycle(curTick + delay)); 4145103Ssaidi@eecs.umich.edu _status = DcacheWaitResponse; 4155103Ssaidi@eecs.umich.edu dcache_pkt = NULL; 4165103Ssaidi@eecs.umich.edu } else if (!dcachePort.sendTiming(dcache_pkt)) { 4173170Sstever@eecs.umich.edu _status = DcacheRetry; 4183170Sstever@eecs.umich.edu } else { 4193170Sstever@eecs.umich.edu _status = DcacheWaitResponse; 4203170Sstever@eecs.umich.edu // memory system takes ownership of packet 4213170Sstever@eecs.umich.edu dcache_pkt = NULL; 4223170Sstever@eecs.umich.edu } 4232623SN/A } 4244200Ssaidi@eecs.umich.edu // This will need a new way to tell if it's hooked up to a cache or not. 4254200Ssaidi@eecs.umich.edu if (req->isUncacheable()) 4264200Ssaidi@eecs.umich.edu recordEvent("Uncached Write"); 4273658Sktlim@umich.edu } else { 4283658Sktlim@umich.edu delete req; 4292623SN/A } 4302623SN/A 4315408Sgblack@eecs.umich.edu if (traceData) { 4325408Sgblack@eecs.umich.edu traceData->setData(data); 4335408Sgblack@eecs.umich.edu } 4342623SN/A 4352623SN/A // If the write needs to have a fault on the access, consider calling 4362623SN/A // changeStatus() and changing it to "bad addr write" or something. 4372623SN/A return fault; 4382623SN/A} 4392623SN/A 4405177Sgblack@eecs.umich.eduFault 4415177Sgblack@eecs.umich.eduTimingSimpleCPU::translateDataWriteAddr(Addr vaddr, Addr &paddr, 4425177Sgblack@eecs.umich.edu int size, unsigned flags) 4435177Sgblack@eecs.umich.edu{ 4445177Sgblack@eecs.umich.edu Request *req = 4455177Sgblack@eecs.umich.edu new Request(0, vaddr, size, flags, thread->readPC(), cpuId, 0); 4465177Sgblack@eecs.umich.edu 4475177Sgblack@eecs.umich.edu if (traceData) { 4485177Sgblack@eecs.umich.edu traceData->setAddr(vaddr); 4495177Sgblack@eecs.umich.edu } 4505177Sgblack@eecs.umich.edu 4515177Sgblack@eecs.umich.edu Fault fault = thread->translateDataWriteReq(req); 4525177Sgblack@eecs.umich.edu 4535177Sgblack@eecs.umich.edu if (fault == NoFault) 4545177Sgblack@eecs.umich.edu paddr = req->getPaddr(); 4555177Sgblack@eecs.umich.edu 4565177Sgblack@eecs.umich.edu delete req; 4575177Sgblack@eecs.umich.edu return fault; 4585177Sgblack@eecs.umich.edu} 4595177Sgblack@eecs.umich.edu 4602623SN/A 4612623SN/A#ifndef DOXYGEN_SHOULD_SKIP_THIS 4622623SN/Atemplate 4632623SN/AFault 4644224Sgblack@eecs.umich.eduTimingSimpleCPU::write(Twin32_t data, Addr addr, 4654224Sgblack@eecs.umich.edu unsigned flags, uint64_t *res); 4664224Sgblack@eecs.umich.edu 4674224Sgblack@eecs.umich.edutemplate 4684224Sgblack@eecs.umich.eduFault 4694224Sgblack@eecs.umich.eduTimingSimpleCPU::write(Twin64_t data, Addr addr, 4704224Sgblack@eecs.umich.edu unsigned flags, uint64_t *res); 4714224Sgblack@eecs.umich.edu 4724224Sgblack@eecs.umich.edutemplate 4734224Sgblack@eecs.umich.eduFault 4742623SN/ATimingSimpleCPU::write(uint64_t data, Addr addr, 4752623SN/A unsigned flags, uint64_t *res); 4762623SN/A 4772623SN/Atemplate 4782623SN/AFault 4792623SN/ATimingSimpleCPU::write(uint32_t data, Addr addr, 4802623SN/A unsigned flags, uint64_t *res); 4812623SN/A 4822623SN/Atemplate 4832623SN/AFault 4842623SN/ATimingSimpleCPU::write(uint16_t data, Addr addr, 4852623SN/A unsigned flags, uint64_t *res); 4862623SN/A 4872623SN/Atemplate 4882623SN/AFault 4892623SN/ATimingSimpleCPU::write(uint8_t data, Addr addr, 4902623SN/A unsigned flags, uint64_t *res); 4912623SN/A 4922623SN/A#endif //DOXYGEN_SHOULD_SKIP_THIS 4932623SN/A 4942623SN/Atemplate<> 4952623SN/AFault 4962623SN/ATimingSimpleCPU::write(double data, Addr addr, unsigned flags, uint64_t *res) 4972623SN/A{ 4982623SN/A return write(*(uint64_t*)&data, addr, flags, res); 4992623SN/A} 5002623SN/A 5012623SN/Atemplate<> 5022623SN/AFault 5032623SN/ATimingSimpleCPU::write(float data, Addr addr, unsigned flags, uint64_t *res) 5042623SN/A{ 5052623SN/A return write(*(uint32_t*)&data, addr, flags, res); 5062623SN/A} 5072623SN/A 5082623SN/A 5092623SN/Atemplate<> 5102623SN/AFault 5112623SN/ATimingSimpleCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res) 5122623SN/A{ 5132623SN/A return write((uint32_t)data, addr, flags, res); 5142623SN/A} 5152623SN/A 5162623SN/A 5172623SN/Avoid 5182623SN/ATimingSimpleCPU::fetch() 5192623SN/A{ 5205221Ssaidi@eecs.umich.edu DPRINTF(SimpleCPU, "Fetch\n"); 5215221Ssaidi@eecs.umich.edu 5223387Sgblack@eecs.umich.edu if (!curStaticInst || !curStaticInst->isDelayedCommit()) 5233387Sgblack@eecs.umich.edu checkForInterrupts(); 5242631SN/A 5255348Ssaidi@eecs.umich.edu checkPcEventQueue(); 5265348Ssaidi@eecs.umich.edu 5275669Sgblack@eecs.umich.edu bool fromRom = isRomMicroPC(thread->readMicroPC()); 5282623SN/A 5295669Sgblack@eecs.umich.edu if (!fromRom) { 5305669Sgblack@eecs.umich.edu Request *ifetch_req = new Request(); 5315669Sgblack@eecs.umich.edu ifetch_req->setThreadContext(cpuId, /* thread ID */ 0); 5325669Sgblack@eecs.umich.edu Fault fault = setupFetchRequest(ifetch_req); 5332623SN/A 5345669Sgblack@eecs.umich.edu ifetch_pkt = new Packet(ifetch_req, MemCmd::ReadReq, Packet::Broadcast); 5355669Sgblack@eecs.umich.edu ifetch_pkt->dataStatic(&inst); 5365669Sgblack@eecs.umich.edu 5375669Sgblack@eecs.umich.edu if (fault == NoFault) { 5385669Sgblack@eecs.umich.edu if (!icachePort.sendTiming(ifetch_pkt)) { 5395669Sgblack@eecs.umich.edu // Need to wait for retry 5405669Sgblack@eecs.umich.edu _status = IcacheRetry; 5415669Sgblack@eecs.umich.edu } else { 5425669Sgblack@eecs.umich.edu // Need to wait for cache to respond 5435669Sgblack@eecs.umich.edu _status = IcacheWaitResponse; 5445669Sgblack@eecs.umich.edu // ownership of packet transferred to memory system 5455669Sgblack@eecs.umich.edu ifetch_pkt = NULL; 5465669Sgblack@eecs.umich.edu } 5472623SN/A } else { 5485669Sgblack@eecs.umich.edu delete ifetch_req; 5495669Sgblack@eecs.umich.edu delete ifetch_pkt; 5505669Sgblack@eecs.umich.edu // fetch fault: advance directly to next instruction (fault handler) 5515669Sgblack@eecs.umich.edu advanceInst(fault); 5522623SN/A } 5532623SN/A } else { 5545669Sgblack@eecs.umich.edu _status = IcacheWaitResponse; 5555669Sgblack@eecs.umich.edu completeIfetch(NULL); 5562623SN/A } 5573222Sktlim@umich.edu 5585099Ssaidi@eecs.umich.edu numCycles += tickToCycles(curTick - previousTick); 5593222Sktlim@umich.edu previousTick = curTick; 5602623SN/A} 5612623SN/A 5622623SN/A 5632623SN/Avoid 5642644Sstever@eecs.umich.eduTimingSimpleCPU::advanceInst(Fault fault) 5652623SN/A{ 5662623SN/A advancePC(fault); 5672623SN/A 5682631SN/A if (_status == Running) { 5692631SN/A // kick off fetch of next instruction... callback from icache 5702631SN/A // response will cause that instruction to be executed, 5712631SN/A // keeping the CPU running. 5722631SN/A fetch(); 5732631SN/A } 5742623SN/A} 5752623SN/A 5762623SN/A 5772623SN/Avoid 5783349Sbinkertn@umich.eduTimingSimpleCPU::completeIfetch(PacketPtr pkt) 5792623SN/A{ 5805221Ssaidi@eecs.umich.edu DPRINTF(SimpleCPU, "Complete ICache Fetch\n"); 5815221Ssaidi@eecs.umich.edu 5822623SN/A // received a response from the icache: execute the received 5832623SN/A // instruction 5845669Sgblack@eecs.umich.edu 5855669Sgblack@eecs.umich.edu assert(!pkt || !pkt->isError()); 5862623SN/A assert(_status == IcacheWaitResponse); 5872798Sktlim@umich.edu 5882623SN/A _status = Running; 5892644Sstever@eecs.umich.edu 5905099Ssaidi@eecs.umich.edu numCycles += tickToCycles(curTick - previousTick); 5913222Sktlim@umich.edu previousTick = curTick; 5923222Sktlim@umich.edu 5932839Sktlim@umich.edu if (getState() == SimObject::Draining) { 5945669Sgblack@eecs.umich.edu if (pkt) { 5955669Sgblack@eecs.umich.edu delete pkt->req; 5965669Sgblack@eecs.umich.edu delete pkt; 5975669Sgblack@eecs.umich.edu } 5983658Sktlim@umich.edu 5992839Sktlim@umich.edu completeDrain(); 6002798Sktlim@umich.edu return; 6012798Sktlim@umich.edu } 6022798Sktlim@umich.edu 6032623SN/A preExecute(); 6042644Sstever@eecs.umich.edu if (curStaticInst->isMemRef() && !curStaticInst->isDataPrefetch()) { 6052623SN/A // load or store: just send to dcache 6062623SN/A Fault fault = curStaticInst->initiateAcc(this, traceData); 6073170Sstever@eecs.umich.edu if (_status != Running) { 6083170Sstever@eecs.umich.edu // instruction will complete in dcache response callback 6093170Sstever@eecs.umich.edu assert(_status == DcacheWaitResponse || _status == DcacheRetry); 6103170Sstever@eecs.umich.edu assert(fault == NoFault); 6112644Sstever@eecs.umich.edu } else { 6123170Sstever@eecs.umich.edu if (fault == NoFault) { 6135335Shines@cs.fsu.edu // Note that ARM can have NULL packets if the instruction gets 6145335Shines@cs.fsu.edu // squashed due to predication 6153170Sstever@eecs.umich.edu // early fail on store conditional: complete now 6165335Shines@cs.fsu.edu assert(dcache_pkt != NULL || THE_ISA == ARM_ISA); 6175335Shines@cs.fsu.edu 6183170Sstever@eecs.umich.edu fault = curStaticInst->completeAcc(dcache_pkt, this, 6193170Sstever@eecs.umich.edu traceData); 6205335Shines@cs.fsu.edu if (dcache_pkt != NULL) 6215335Shines@cs.fsu.edu { 6225335Shines@cs.fsu.edu delete dcache_pkt->req; 6235335Shines@cs.fsu.edu delete dcache_pkt; 6245335Shines@cs.fsu.edu dcache_pkt = NULL; 6255335Shines@cs.fsu.edu } 6264998Sgblack@eecs.umich.edu 6274998Sgblack@eecs.umich.edu // keep an instruction count 6284998Sgblack@eecs.umich.edu if (fault == NoFault) 6294998Sgblack@eecs.umich.edu countInst(); 6305001Sgblack@eecs.umich.edu } else if (traceData) { 6315001Sgblack@eecs.umich.edu // If there was a fault, we shouldn't trace this instruction. 6325001Sgblack@eecs.umich.edu delete traceData; 6335001Sgblack@eecs.umich.edu traceData = NULL; 6343170Sstever@eecs.umich.edu } 6354998Sgblack@eecs.umich.edu 6362644Sstever@eecs.umich.edu postExecute(); 6375103Ssaidi@eecs.umich.edu // @todo remove me after debugging with legion done 6385103Ssaidi@eecs.umich.edu if (curStaticInst && (!curStaticInst->isMicroop() || 6395103Ssaidi@eecs.umich.edu curStaticInst->isFirstMicroop())) 6405103Ssaidi@eecs.umich.edu instCnt++; 6412644Sstever@eecs.umich.edu advanceInst(fault); 6422644Sstever@eecs.umich.edu } 6432623SN/A } else { 6442623SN/A // non-memory instruction: execute completely now 6452623SN/A Fault fault = curStaticInst->execute(this, traceData); 6464998Sgblack@eecs.umich.edu 6474998Sgblack@eecs.umich.edu // keep an instruction count 6484998Sgblack@eecs.umich.edu if (fault == NoFault) 6494998Sgblack@eecs.umich.edu countInst(); 6505001Sgblack@eecs.umich.edu else if (traceData) { 6515001Sgblack@eecs.umich.edu // If there was a fault, we shouldn't trace this instruction. 6525001Sgblack@eecs.umich.edu delete traceData; 6535001Sgblack@eecs.umich.edu traceData = NULL; 6545001Sgblack@eecs.umich.edu } 6554998Sgblack@eecs.umich.edu 6562644Sstever@eecs.umich.edu postExecute(); 6575103Ssaidi@eecs.umich.edu // @todo remove me after debugging with legion done 6585103Ssaidi@eecs.umich.edu if (curStaticInst && (!curStaticInst->isMicroop() || 6595103Ssaidi@eecs.umich.edu curStaticInst->isFirstMicroop())) 6605103Ssaidi@eecs.umich.edu instCnt++; 6612644Sstever@eecs.umich.edu advanceInst(fault); 6622623SN/A } 6633658Sktlim@umich.edu 6645669Sgblack@eecs.umich.edu if (pkt) { 6655669Sgblack@eecs.umich.edu delete pkt->req; 6665669Sgblack@eecs.umich.edu delete pkt; 6675669Sgblack@eecs.umich.edu } 6682623SN/A} 6692623SN/A 6702948Ssaidi@eecs.umich.eduvoid 6712948Ssaidi@eecs.umich.eduTimingSimpleCPU::IcachePort::ITickEvent::process() 6722948Ssaidi@eecs.umich.edu{ 6732948Ssaidi@eecs.umich.edu cpu->completeIfetch(pkt); 6742948Ssaidi@eecs.umich.edu} 6752623SN/A 6762623SN/Abool 6773349Sbinkertn@umich.eduTimingSimpleCPU::IcachePort::recvTiming(PacketPtr pkt) 6782623SN/A{ 6794986Ssaidi@eecs.umich.edu if (pkt->isResponse() && !pkt->wasNacked()) { 6803310Srdreslin@umich.edu // delay processing of returned data until next CPU clock edge 6814584Ssaidi@eecs.umich.edu Tick next_tick = cpu->nextCycle(curTick); 6822948Ssaidi@eecs.umich.edu 6833495Sktlim@umich.edu if (next_tick == curTick) 6843310Srdreslin@umich.edu cpu->completeIfetch(pkt); 6853310Srdreslin@umich.edu else 6863495Sktlim@umich.edu tickEvent.schedule(pkt, next_tick); 6872948Ssaidi@eecs.umich.edu 6883310Srdreslin@umich.edu return true; 6893310Srdreslin@umich.edu } 6904870Sstever@eecs.umich.edu else if (pkt->wasNacked()) { 6914433Ssaidi@eecs.umich.edu assert(cpu->_status == IcacheWaitResponse); 6924433Ssaidi@eecs.umich.edu pkt->reinitNacked(); 6934433Ssaidi@eecs.umich.edu if (!sendTiming(pkt)) { 6944433Ssaidi@eecs.umich.edu cpu->_status = IcacheRetry; 6954433Ssaidi@eecs.umich.edu cpu->ifetch_pkt = pkt; 6964433Ssaidi@eecs.umich.edu } 6973310Srdreslin@umich.edu } 6984433Ssaidi@eecs.umich.edu //Snooping a Coherence Request, do nothing 6994433Ssaidi@eecs.umich.edu return true; 7002623SN/A} 7012623SN/A 7022657Ssaidi@eecs.umich.eduvoid 7032623SN/ATimingSimpleCPU::IcachePort::recvRetry() 7042623SN/A{ 7052623SN/A // we shouldn't get a retry unless we have a packet that we're 7062623SN/A // waiting to transmit 7072623SN/A assert(cpu->ifetch_pkt != NULL); 7082623SN/A assert(cpu->_status == IcacheRetry); 7093349Sbinkertn@umich.edu PacketPtr tmp = cpu->ifetch_pkt; 7102657Ssaidi@eecs.umich.edu if (sendTiming(tmp)) { 7112657Ssaidi@eecs.umich.edu cpu->_status = IcacheWaitResponse; 7122657Ssaidi@eecs.umich.edu cpu->ifetch_pkt = NULL; 7132657Ssaidi@eecs.umich.edu } 7142623SN/A} 7152623SN/A 7162623SN/Avoid 7173349Sbinkertn@umich.eduTimingSimpleCPU::completeDataAccess(PacketPtr pkt) 7182623SN/A{ 7192623SN/A // received a response from the dcache: complete the load or store 7202623SN/A // instruction 7214870Sstever@eecs.umich.edu assert(!pkt->isError()); 7222623SN/A assert(_status == DcacheWaitResponse); 7232623SN/A _status = Running; 7242623SN/A 7255099Ssaidi@eecs.umich.edu numCycles += tickToCycles(curTick - previousTick); 7263222Sktlim@umich.edu previousTick = curTick; 7273184Srdreslin@umich.edu 7282623SN/A Fault fault = curStaticInst->completeAcc(pkt, this, traceData); 7292623SN/A 7304998Sgblack@eecs.umich.edu // keep an instruction count 7314998Sgblack@eecs.umich.edu if (fault == NoFault) 7324998Sgblack@eecs.umich.edu countInst(); 7335001Sgblack@eecs.umich.edu else if (traceData) { 7345001Sgblack@eecs.umich.edu // If there was a fault, we shouldn't trace this instruction. 7355001Sgblack@eecs.umich.edu delete traceData; 7365001Sgblack@eecs.umich.edu traceData = NULL; 7375001Sgblack@eecs.umich.edu } 7384998Sgblack@eecs.umich.edu 7395507Sstever@gmail.com // the locked flag may be cleared on the response packet, so check 7405507Sstever@gmail.com // pkt->req and not pkt to see if it was a load-locked 7415507Sstever@gmail.com if (pkt->isRead() && pkt->req->isLocked()) { 7423170Sstever@eecs.umich.edu TheISA::handleLockedRead(thread, pkt->req); 7433170Sstever@eecs.umich.edu } 7443170Sstever@eecs.umich.edu 7452644Sstever@eecs.umich.edu delete pkt->req; 7462644Sstever@eecs.umich.edu delete pkt; 7472644Sstever@eecs.umich.edu 7483184Srdreslin@umich.edu postExecute(); 7493227Sktlim@umich.edu 7503201Shsul@eecs.umich.edu if (getState() == SimObject::Draining) { 7513201Shsul@eecs.umich.edu advancePC(fault); 7523201Shsul@eecs.umich.edu completeDrain(); 7533201Shsul@eecs.umich.edu 7543201Shsul@eecs.umich.edu return; 7553201Shsul@eecs.umich.edu } 7563201Shsul@eecs.umich.edu 7572644Sstever@eecs.umich.edu advanceInst(fault); 7582623SN/A} 7592623SN/A 7602623SN/A 7612798Sktlim@umich.eduvoid 7622839Sktlim@umich.eduTimingSimpleCPU::completeDrain() 7632798Sktlim@umich.edu{ 7642839Sktlim@umich.edu DPRINTF(Config, "Done draining\n"); 7652901Ssaidi@eecs.umich.edu changeState(SimObject::Drained); 7662839Sktlim@umich.edu drainEvent->process(); 7672798Sktlim@umich.edu} 7682623SN/A 7694192Sktlim@umich.eduvoid 7704192Sktlim@umich.eduTimingSimpleCPU::DcachePort::setPeer(Port *port) 7714192Sktlim@umich.edu{ 7724192Sktlim@umich.edu Port::setPeer(port); 7734192Sktlim@umich.edu 7744192Sktlim@umich.edu#if FULL_SYSTEM 7754192Sktlim@umich.edu // Update the ThreadContext's memory ports (Functional/Virtual 7764192Sktlim@umich.edu // Ports) 7775497Ssaidi@eecs.umich.edu cpu->tcBase()->connectMemPorts(cpu->tcBase()); 7784192Sktlim@umich.edu#endif 7794192Sktlim@umich.edu} 7804192Sktlim@umich.edu 7812623SN/Abool 7823349Sbinkertn@umich.eduTimingSimpleCPU::DcachePort::recvTiming(PacketPtr pkt) 7832623SN/A{ 7844986Ssaidi@eecs.umich.edu if (pkt->isResponse() && !pkt->wasNacked()) { 7853310Srdreslin@umich.edu // delay processing of returned data until next CPU clock edge 7864584Ssaidi@eecs.umich.edu Tick next_tick = cpu->nextCycle(curTick); 7872948Ssaidi@eecs.umich.edu 7883495Sktlim@umich.edu if (next_tick == curTick) 7893310Srdreslin@umich.edu cpu->completeDataAccess(pkt); 7903310Srdreslin@umich.edu else 7913495Sktlim@umich.edu tickEvent.schedule(pkt, next_tick); 7922948Ssaidi@eecs.umich.edu 7933310Srdreslin@umich.edu return true; 7943310Srdreslin@umich.edu } 7954870Sstever@eecs.umich.edu else if (pkt->wasNacked()) { 7964433Ssaidi@eecs.umich.edu assert(cpu->_status == DcacheWaitResponse); 7974433Ssaidi@eecs.umich.edu pkt->reinitNacked(); 7984433Ssaidi@eecs.umich.edu if (!sendTiming(pkt)) { 7994433Ssaidi@eecs.umich.edu cpu->_status = DcacheRetry; 8004433Ssaidi@eecs.umich.edu cpu->dcache_pkt = pkt; 8014433Ssaidi@eecs.umich.edu } 8023310Srdreslin@umich.edu } 8034433Ssaidi@eecs.umich.edu //Snooping a Coherence Request, do nothing 8044433Ssaidi@eecs.umich.edu return true; 8052948Ssaidi@eecs.umich.edu} 8062948Ssaidi@eecs.umich.edu 8072948Ssaidi@eecs.umich.eduvoid 8082948Ssaidi@eecs.umich.eduTimingSimpleCPU::DcachePort::DTickEvent::process() 8092948Ssaidi@eecs.umich.edu{ 8102630SN/A cpu->completeDataAccess(pkt); 8112623SN/A} 8122623SN/A 8132657Ssaidi@eecs.umich.eduvoid 8142623SN/ATimingSimpleCPU::DcachePort::recvRetry() 8152623SN/A{ 8162623SN/A // we shouldn't get a retry unless we have a packet that we're 8172623SN/A // waiting to transmit 8182623SN/A assert(cpu->dcache_pkt != NULL); 8192623SN/A assert(cpu->_status == DcacheRetry); 8203349Sbinkertn@umich.edu PacketPtr tmp = cpu->dcache_pkt; 8212657Ssaidi@eecs.umich.edu if (sendTiming(tmp)) { 8222657Ssaidi@eecs.umich.edu cpu->_status = DcacheWaitResponse; 8233170Sstever@eecs.umich.edu // memory system takes ownership of packet 8242657Ssaidi@eecs.umich.edu cpu->dcache_pkt = NULL; 8252657Ssaidi@eecs.umich.edu } 8262623SN/A} 8272623SN/A 8285606Snate@binkert.orgTimingSimpleCPU::IprEvent::IprEvent(Packet *_pkt, TimingSimpleCPU *_cpu, 8295606Snate@binkert.org Tick t) 8305606Snate@binkert.org : pkt(_pkt), cpu(_cpu) 8315103Ssaidi@eecs.umich.edu{ 8325606Snate@binkert.org cpu->schedule(this, t); 8335103Ssaidi@eecs.umich.edu} 8345103Ssaidi@eecs.umich.edu 8355103Ssaidi@eecs.umich.eduvoid 8365103Ssaidi@eecs.umich.eduTimingSimpleCPU::IprEvent::process() 8375103Ssaidi@eecs.umich.edu{ 8385103Ssaidi@eecs.umich.edu cpu->completeDataAccess(pkt); 8395103Ssaidi@eecs.umich.edu} 8405103Ssaidi@eecs.umich.edu 8415103Ssaidi@eecs.umich.educonst char * 8425336Shines@cs.fsu.eduTimingSimpleCPU::IprEvent::description() const 8435103Ssaidi@eecs.umich.edu{ 8445103Ssaidi@eecs.umich.edu return "Timing Simple CPU Delay IPR event"; 8455103Ssaidi@eecs.umich.edu} 8465103Ssaidi@eecs.umich.edu 8472623SN/A 8485315Sstever@gmail.comvoid 8495315Sstever@gmail.comTimingSimpleCPU::printAddr(Addr a) 8505315Sstever@gmail.com{ 8515315Sstever@gmail.com dcachePort.printAddr(a); 8525315Sstever@gmail.com} 8535315Sstever@gmail.com 8545315Sstever@gmail.com 8552623SN/A//////////////////////////////////////////////////////////////////////// 8562623SN/A// 8572623SN/A// TimingSimpleCPU Simulation Object 8582623SN/A// 8594762Snate@binkert.orgTimingSimpleCPU * 8604762Snate@binkert.orgTimingSimpleCPUParams::create() 8612623SN/A{ 8625529Snate@binkert.org numThreads = 1; 8635529Snate@binkert.org#if !FULL_SYSTEM 8644762Snate@binkert.org if (workload.size() != 1) 8654762Snate@binkert.org panic("only one workload allowed"); 8662623SN/A#endif 8675529Snate@binkert.org return new TimingSimpleCPU(this); 8682623SN/A} 869