timing.cc revision 5348
12623SN/A/* 22623SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 32623SN/A * All rights reserved. 42623SN/A * 52623SN/A * Redistribution and use in source and binary forms, with or without 62623SN/A * modification, are permitted provided that the following conditions are 72623SN/A * met: redistributions of source code must retain the above copyright 82623SN/A * notice, this list of conditions and the following disclaimer; 92623SN/A * redistributions in binary form must reproduce the above copyright 102623SN/A * notice, this list of conditions and the following disclaimer in the 112623SN/A * documentation and/or other materials provided with the distribution; 122623SN/A * neither the name of the copyright holders nor the names of its 132623SN/A * contributors may be used to endorse or promote products derived from 142623SN/A * this software without specific prior written permission. 152623SN/A * 162623SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172623SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182623SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192623SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202623SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212623SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222623SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232623SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242623SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252623SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262623SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 292623SN/A */ 302623SN/A 313170Sstever@eecs.umich.edu#include "arch/locked_mem.hh" 325103Ssaidi@eecs.umich.edu#include "arch/mmaped_ipr.hh" 332623SN/A#include "arch/utility.hh" 344040Ssaidi@eecs.umich.edu#include "base/bigint.hh" 352623SN/A#include "cpu/exetrace.hh" 362623SN/A#include "cpu/simple/timing.hh" 373348Sbinkertn@umich.edu#include "mem/packet.hh" 383348Sbinkertn@umich.edu#include "mem/packet_access.hh" 394762Snate@binkert.org#include "params/TimingSimpleCPU.hh" 402901Ssaidi@eecs.umich.edu#include "sim/system.hh" 412623SN/A 422623SN/Ausing namespace std; 432623SN/Ausing namespace TheISA; 442623SN/A 452856Srdreslin@umich.eduPort * 462856Srdreslin@umich.eduTimingSimpleCPU::getPort(const std::string &if_name, int idx) 472856Srdreslin@umich.edu{ 482856Srdreslin@umich.edu if (if_name == "dcache_port") 492856Srdreslin@umich.edu return &dcachePort; 502856Srdreslin@umich.edu else if (if_name == "icache_port") 512856Srdreslin@umich.edu return &icachePort; 522856Srdreslin@umich.edu else 532856Srdreslin@umich.edu panic("No Such Port\n"); 542856Srdreslin@umich.edu} 552623SN/A 562623SN/Avoid 572623SN/ATimingSimpleCPU::init() 582623SN/A{ 592623SN/A BaseCPU::init(); 605310Ssaidi@eecs.umich.edu cpuId = tc->readCpuId(); 612623SN/A#if FULL_SYSTEM 622680Sktlim@umich.edu for (int i = 0; i < threadContexts.size(); ++i) { 632680Sktlim@umich.edu ThreadContext *tc = threadContexts[i]; 642623SN/A 652623SN/A // initialize CPU, including PC 665310Ssaidi@eecs.umich.edu TheISA::initCPU(tc, cpuId); 672623SN/A } 682623SN/A#endif 692623SN/A} 702623SN/A 712623SN/ATick 723349Sbinkertn@umich.eduTimingSimpleCPU::CpuPort::recvAtomic(PacketPtr pkt) 732623SN/A{ 742623SN/A panic("TimingSimpleCPU doesn't expect recvAtomic callback!"); 752623SN/A return curTick; 762623SN/A} 772623SN/A 782623SN/Avoid 793349Sbinkertn@umich.eduTimingSimpleCPU::CpuPort::recvFunctional(PacketPtr pkt) 802623SN/A{ 813184Srdreslin@umich.edu //No internal storage to update, jusst return 823184Srdreslin@umich.edu return; 832623SN/A} 842623SN/A 852623SN/Avoid 862623SN/ATimingSimpleCPU::CpuPort::recvStatusChange(Status status) 872623SN/A{ 883647Srdreslin@umich.edu if (status == RangeChange) { 893647Srdreslin@umich.edu if (!snoopRangeSent) { 903647Srdreslin@umich.edu snoopRangeSent = true; 913647Srdreslin@umich.edu sendStatusChange(Port::RangeChange); 923647Srdreslin@umich.edu } 932631SN/A return; 943647Srdreslin@umich.edu } 952631SN/A 962623SN/A panic("TimingSimpleCPU doesn't expect recvStatusChange callback!"); 972623SN/A} 982623SN/A 992948Ssaidi@eecs.umich.edu 1002948Ssaidi@eecs.umich.eduvoid 1013349Sbinkertn@umich.eduTimingSimpleCPU::CpuPort::TickEvent::schedule(PacketPtr _pkt, Tick t) 1022948Ssaidi@eecs.umich.edu{ 1032948Ssaidi@eecs.umich.edu pkt = _pkt; 1042948Ssaidi@eecs.umich.edu Event::schedule(t); 1052948Ssaidi@eecs.umich.edu} 1062948Ssaidi@eecs.umich.edu 1072623SN/ATimingSimpleCPU::TimingSimpleCPU(Params *p) 1085169Ssaidi@eecs.umich.edu : BaseSimpleCPU(p), icachePort(this, p->clock), dcachePort(this, p->clock) 1092623SN/A{ 1102623SN/A _status = Idle; 1113647Srdreslin@umich.edu 1123647Srdreslin@umich.edu icachePort.snoopRangeSent = false; 1133647Srdreslin@umich.edu dcachePort.snoopRangeSent = false; 1143647Srdreslin@umich.edu 1152623SN/A ifetch_pkt = dcache_pkt = NULL; 1162839Sktlim@umich.edu drainEvent = NULL; 1172867Sktlim@umich.edu fetchEvent = NULL; 1183222Sktlim@umich.edu previousTick = 0; 1192901Ssaidi@eecs.umich.edu changeState(SimObject::Running); 1202623SN/A} 1212623SN/A 1222623SN/A 1232623SN/ATimingSimpleCPU::~TimingSimpleCPU() 1242623SN/A{ 1252623SN/A} 1262623SN/A 1272623SN/Avoid 1282623SN/ATimingSimpleCPU::serialize(ostream &os) 1292623SN/A{ 1302915Sktlim@umich.edu SimObject::State so_state = SimObject::getState(); 1312915Sktlim@umich.edu SERIALIZE_ENUM(so_state); 1322623SN/A BaseSimpleCPU::serialize(os); 1332623SN/A} 1342623SN/A 1352623SN/Avoid 1362623SN/ATimingSimpleCPU::unserialize(Checkpoint *cp, const string §ion) 1372623SN/A{ 1382915Sktlim@umich.edu SimObject::State so_state; 1392915Sktlim@umich.edu UNSERIALIZE_ENUM(so_state); 1402623SN/A BaseSimpleCPU::unserialize(cp, section); 1412798Sktlim@umich.edu} 1422798Sktlim@umich.edu 1432901Ssaidi@eecs.umich.eduunsigned int 1442839Sktlim@umich.eduTimingSimpleCPU::drain(Event *drain_event) 1452798Sktlim@umich.edu{ 1462839Sktlim@umich.edu // TimingSimpleCPU is ready to drain if it's not waiting for 1472798Sktlim@umich.edu // an access to complete. 1482798Sktlim@umich.edu if (status() == Idle || status() == Running || status() == SwitchedOut) { 1492901Ssaidi@eecs.umich.edu changeState(SimObject::Drained); 1502901Ssaidi@eecs.umich.edu return 0; 1512798Sktlim@umich.edu } else { 1522839Sktlim@umich.edu changeState(SimObject::Draining); 1532839Sktlim@umich.edu drainEvent = drain_event; 1542901Ssaidi@eecs.umich.edu return 1; 1552798Sktlim@umich.edu } 1562623SN/A} 1572623SN/A 1582623SN/Avoid 1592798Sktlim@umich.eduTimingSimpleCPU::resume() 1602623SN/A{ 1615221Ssaidi@eecs.umich.edu DPRINTF(SimpleCPU, "Resume\n"); 1622798Sktlim@umich.edu if (_status != SwitchedOut && _status != Idle) { 1634762Snate@binkert.org assert(system->getMemoryMode() == Enums::timing); 1643201Shsul@eecs.umich.edu 1652867Sktlim@umich.edu // Delete the old event if it existed. 1662867Sktlim@umich.edu if (fetchEvent) { 1672915Sktlim@umich.edu if (fetchEvent->scheduled()) 1682915Sktlim@umich.edu fetchEvent->deschedule(); 1692915Sktlim@umich.edu 1702867Sktlim@umich.edu delete fetchEvent; 1712867Sktlim@umich.edu } 1722867Sktlim@umich.edu 1734471Sstever@eecs.umich.edu fetchEvent = new FetchEvent(this, nextCycle()); 1742623SN/A } 1752798Sktlim@umich.edu 1762901Ssaidi@eecs.umich.edu changeState(SimObject::Running); 1772798Sktlim@umich.edu} 1782798Sktlim@umich.edu 1792798Sktlim@umich.eduvoid 1802798Sktlim@umich.eduTimingSimpleCPU::switchOut() 1812798Sktlim@umich.edu{ 1822798Sktlim@umich.edu assert(status() == Running || status() == Idle); 1832798Sktlim@umich.edu _status = SwitchedOut; 1845099Ssaidi@eecs.umich.edu numCycles += tickToCycles(curTick - previousTick); 1852867Sktlim@umich.edu 1862867Sktlim@umich.edu // If we've been scheduled to resume but are then told to switch out, 1872867Sktlim@umich.edu // we'll need to cancel it. 1882867Sktlim@umich.edu if (fetchEvent && fetchEvent->scheduled()) 1892867Sktlim@umich.edu fetchEvent->deschedule(); 1902623SN/A} 1912623SN/A 1922623SN/A 1932623SN/Avoid 1942623SN/ATimingSimpleCPU::takeOverFrom(BaseCPU *oldCPU) 1952623SN/A{ 1964192Sktlim@umich.edu BaseCPU::takeOverFrom(oldCPU, &icachePort, &dcachePort); 1972623SN/A 1982680Sktlim@umich.edu // if any of this CPU's ThreadContexts are active, mark the CPU as 1992623SN/A // running and schedule its tick event. 2002680Sktlim@umich.edu for (int i = 0; i < threadContexts.size(); ++i) { 2012680Sktlim@umich.edu ThreadContext *tc = threadContexts[i]; 2022680Sktlim@umich.edu if (tc->status() == ThreadContext::Active && _status != Running) { 2032623SN/A _status = Running; 2042623SN/A break; 2052623SN/A } 2062623SN/A } 2073201Shsul@eecs.umich.edu 2083201Shsul@eecs.umich.edu if (_status != Running) { 2093201Shsul@eecs.umich.edu _status = Idle; 2103201Shsul@eecs.umich.edu } 2115169Ssaidi@eecs.umich.edu assert(threadContexts.size() == 1); 2125169Ssaidi@eecs.umich.edu cpuId = tc->readCpuId(); 2135101Ssaidi@eecs.umich.edu previousTick = curTick; 2142623SN/A} 2152623SN/A 2162623SN/A 2172623SN/Avoid 2182623SN/ATimingSimpleCPU::activateContext(int thread_num, int delay) 2192623SN/A{ 2205221Ssaidi@eecs.umich.edu DPRINTF(SimpleCPU, "ActivateContext %d (%d cycles)\n", thread_num, delay); 2215221Ssaidi@eecs.umich.edu 2222623SN/A assert(thread_num == 0); 2232683Sktlim@umich.edu assert(thread); 2242623SN/A 2252623SN/A assert(_status == Idle); 2262623SN/A 2272623SN/A notIdleFraction++; 2282623SN/A _status = Running; 2293686Sktlim@umich.edu 2302623SN/A // kick things off by initiating the fetch of the next instruction 2315100Ssaidi@eecs.umich.edu fetchEvent = new FetchEvent(this, nextCycle(curTick + ticks(delay))); 2322623SN/A} 2332623SN/A 2342623SN/A 2352623SN/Avoid 2362623SN/ATimingSimpleCPU::suspendContext(int thread_num) 2372623SN/A{ 2385221Ssaidi@eecs.umich.edu DPRINTF(SimpleCPU, "SuspendContext %d\n", thread_num); 2395221Ssaidi@eecs.umich.edu 2402623SN/A assert(thread_num == 0); 2412683Sktlim@umich.edu assert(thread); 2422623SN/A 2432644Sstever@eecs.umich.edu assert(_status == Running); 2442623SN/A 2452644Sstever@eecs.umich.edu // just change status to Idle... if status != Running, 2462644Sstever@eecs.umich.edu // completeInst() will not initiate fetch of next instruction. 2472623SN/A 2482623SN/A notIdleFraction--; 2492623SN/A _status = Idle; 2502623SN/A} 2512623SN/A 2522623SN/A 2532623SN/Atemplate <class T> 2542623SN/AFault 2552623SN/ATimingSimpleCPU::read(Addr addr, T &data, unsigned flags) 2562623SN/A{ 2573169Sstever@eecs.umich.edu Request *req = 2583169Sstever@eecs.umich.edu new Request(/* asid */ 0, addr, sizeof(T), flags, thread->readPC(), 2595169Ssaidi@eecs.umich.edu cpuId, /* thread ID */ 0); 2602623SN/A 2612623SN/A if (traceData) { 2623169Sstever@eecs.umich.edu traceData->setAddr(req->getVaddr()); 2632623SN/A } 2642623SN/A 2652623SN/A // translate to physical address 2663169Sstever@eecs.umich.edu Fault fault = thread->translateDataReadReq(req); 2672623SN/A 2682623SN/A // Now do the access. 2692623SN/A if (fault == NoFault) { 2703349Sbinkertn@umich.edu PacketPtr pkt = 2714878Sstever@eecs.umich.edu new Packet(req, 2724878Sstever@eecs.umich.edu (req->isLocked() ? 2734878Sstever@eecs.umich.edu MemCmd::LoadLockedReq : MemCmd::ReadReq), 2744878Sstever@eecs.umich.edu Packet::Broadcast); 2753169Sstever@eecs.umich.edu pkt->dataDynamic<T>(new T); 2762623SN/A 2775103Ssaidi@eecs.umich.edu if (req->isMmapedIpr()) { 2785103Ssaidi@eecs.umich.edu Tick delay; 2795103Ssaidi@eecs.umich.edu delay = TheISA::handleIprRead(thread->getTC(), pkt); 2805103Ssaidi@eecs.umich.edu new IprEvent(pkt, this, nextCycle(curTick + delay)); 2815103Ssaidi@eecs.umich.edu _status = DcacheWaitResponse; 2825103Ssaidi@eecs.umich.edu dcache_pkt = NULL; 2835103Ssaidi@eecs.umich.edu } else if (!dcachePort.sendTiming(pkt)) { 2842623SN/A _status = DcacheRetry; 2853169Sstever@eecs.umich.edu dcache_pkt = pkt; 2862623SN/A } else { 2872623SN/A _status = DcacheWaitResponse; 2883169Sstever@eecs.umich.edu // memory system takes ownership of packet 2892623SN/A dcache_pkt = NULL; 2902623SN/A } 2914200Ssaidi@eecs.umich.edu 2924200Ssaidi@eecs.umich.edu // This will need a new way to tell if it has a dcache attached. 2934200Ssaidi@eecs.umich.edu if (req->isUncacheable()) 2944200Ssaidi@eecs.umich.edu recordEvent("Uncached Read"); 2953658Sktlim@umich.edu } else { 2963658Sktlim@umich.edu delete req; 2972623SN/A } 2982623SN/A 2992623SN/A return fault; 3002623SN/A} 3012623SN/A 3025177Sgblack@eecs.umich.eduFault 3035177Sgblack@eecs.umich.eduTimingSimpleCPU::translateDataReadAddr(Addr vaddr, Addr &paddr, 3045177Sgblack@eecs.umich.edu int size, unsigned flags) 3055177Sgblack@eecs.umich.edu{ 3065177Sgblack@eecs.umich.edu Request *req = 3075177Sgblack@eecs.umich.edu new Request(0, vaddr, size, flags, thread->readPC(), cpuId, 0); 3085177Sgblack@eecs.umich.edu 3095177Sgblack@eecs.umich.edu if (traceData) { 3105177Sgblack@eecs.umich.edu traceData->setAddr(vaddr); 3115177Sgblack@eecs.umich.edu } 3125177Sgblack@eecs.umich.edu 3135177Sgblack@eecs.umich.edu Fault fault = thread->translateDataWriteReq(req); 3145177Sgblack@eecs.umich.edu 3155177Sgblack@eecs.umich.edu if (fault == NoFault) 3165177Sgblack@eecs.umich.edu paddr = req->getPaddr(); 3175177Sgblack@eecs.umich.edu 3185177Sgblack@eecs.umich.edu delete req; 3195177Sgblack@eecs.umich.edu return fault; 3205177Sgblack@eecs.umich.edu} 3215177Sgblack@eecs.umich.edu 3222623SN/A#ifndef DOXYGEN_SHOULD_SKIP_THIS 3232623SN/A 3242623SN/Atemplate 3252623SN/AFault 3264040Ssaidi@eecs.umich.eduTimingSimpleCPU::read(Addr addr, Twin64_t &data, unsigned flags); 3274040Ssaidi@eecs.umich.edu 3284040Ssaidi@eecs.umich.edutemplate 3294040Ssaidi@eecs.umich.eduFault 3304115Ssaidi@eecs.umich.eduTimingSimpleCPU::read(Addr addr, Twin32_t &data, unsigned flags); 3314115Ssaidi@eecs.umich.edu 3324115Ssaidi@eecs.umich.edutemplate 3334115Ssaidi@eecs.umich.eduFault 3342623SN/ATimingSimpleCPU::read(Addr addr, uint64_t &data, unsigned flags); 3352623SN/A 3362623SN/Atemplate 3372623SN/AFault 3382623SN/ATimingSimpleCPU::read(Addr addr, uint32_t &data, unsigned flags); 3392623SN/A 3402623SN/Atemplate 3412623SN/AFault 3422623SN/ATimingSimpleCPU::read(Addr addr, uint16_t &data, unsigned flags); 3432623SN/A 3442623SN/Atemplate 3452623SN/AFault 3462623SN/ATimingSimpleCPU::read(Addr addr, uint8_t &data, unsigned flags); 3472623SN/A 3482623SN/A#endif //DOXYGEN_SHOULD_SKIP_THIS 3492623SN/A 3502623SN/Atemplate<> 3512623SN/AFault 3522623SN/ATimingSimpleCPU::read(Addr addr, double &data, unsigned flags) 3532623SN/A{ 3542623SN/A return read(addr, *(uint64_t*)&data, flags); 3552623SN/A} 3562623SN/A 3572623SN/Atemplate<> 3582623SN/AFault 3592623SN/ATimingSimpleCPU::read(Addr addr, float &data, unsigned flags) 3602623SN/A{ 3612623SN/A return read(addr, *(uint32_t*)&data, flags); 3622623SN/A} 3632623SN/A 3642623SN/A 3652623SN/Atemplate<> 3662623SN/AFault 3672623SN/ATimingSimpleCPU::read(Addr addr, int32_t &data, unsigned flags) 3682623SN/A{ 3692623SN/A return read(addr, (uint32_t&)data, flags); 3702623SN/A} 3712623SN/A 3722623SN/A 3732623SN/Atemplate <class T> 3742623SN/AFault 3752623SN/ATimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res) 3762623SN/A{ 3773169Sstever@eecs.umich.edu Request *req = 3783169Sstever@eecs.umich.edu new Request(/* asid */ 0, addr, sizeof(T), flags, thread->readPC(), 3795169Ssaidi@eecs.umich.edu cpuId, /* thread ID */ 0); 3802623SN/A 3814040Ssaidi@eecs.umich.edu if (traceData) { 3824040Ssaidi@eecs.umich.edu traceData->setAddr(req->getVaddr()); 3834040Ssaidi@eecs.umich.edu } 3844040Ssaidi@eecs.umich.edu 3852623SN/A // translate to physical address 3863169Sstever@eecs.umich.edu Fault fault = thread->translateDataWriteReq(req); 3873169Sstever@eecs.umich.edu 3882623SN/A // Now do the access. 3892623SN/A if (fault == NoFault) { 3904878Sstever@eecs.umich.edu MemCmd cmd = MemCmd::WriteReq; // default 3913170Sstever@eecs.umich.edu bool do_access = true; // flag to suppress cache access 3923170Sstever@eecs.umich.edu 3933170Sstever@eecs.umich.edu if (req->isLocked()) { 3944878Sstever@eecs.umich.edu cmd = MemCmd::StoreCondReq; 3953170Sstever@eecs.umich.edu do_access = TheISA::handleLockedWrite(thread, req); 3964878Sstever@eecs.umich.edu } else if (req->isSwap()) { 3974878Sstever@eecs.umich.edu cmd = MemCmd::SwapReq; 3984878Sstever@eecs.umich.edu if (req->isCondSwap()) { 3994878Sstever@eecs.umich.edu assert(res); 4004878Sstever@eecs.umich.edu req->setExtraData(*res); 4014878Sstever@eecs.umich.edu } 4023170Sstever@eecs.umich.edu } 4034584Ssaidi@eecs.umich.edu 4044881Sstever@eecs.umich.edu // Note: need to allocate dcache_pkt even if do_access is 4054881Sstever@eecs.umich.edu // false, as it's used unconditionally to call completeAcc(). 4064881Sstever@eecs.umich.edu assert(dcache_pkt == NULL); 4074881Sstever@eecs.umich.edu dcache_pkt = new Packet(req, cmd, Packet::Broadcast); 4084881Sstever@eecs.umich.edu dcache_pkt->allocate(); 4094881Sstever@eecs.umich.edu dcache_pkt->set(data); 4103170Sstever@eecs.umich.edu 4113170Sstever@eecs.umich.edu if (do_access) { 4125103Ssaidi@eecs.umich.edu if (req->isMmapedIpr()) { 4135103Ssaidi@eecs.umich.edu Tick delay; 4145103Ssaidi@eecs.umich.edu dcache_pkt->set(htog(data)); 4155103Ssaidi@eecs.umich.edu delay = TheISA::handleIprWrite(thread->getTC(), dcache_pkt); 4165103Ssaidi@eecs.umich.edu new IprEvent(dcache_pkt, this, nextCycle(curTick + delay)); 4175103Ssaidi@eecs.umich.edu _status = DcacheWaitResponse; 4185103Ssaidi@eecs.umich.edu dcache_pkt = NULL; 4195103Ssaidi@eecs.umich.edu } else if (!dcachePort.sendTiming(dcache_pkt)) { 4203170Sstever@eecs.umich.edu _status = DcacheRetry; 4213170Sstever@eecs.umich.edu } else { 4223170Sstever@eecs.umich.edu _status = DcacheWaitResponse; 4233170Sstever@eecs.umich.edu // memory system takes ownership of packet 4243170Sstever@eecs.umich.edu dcache_pkt = NULL; 4253170Sstever@eecs.umich.edu } 4262623SN/A } 4274200Ssaidi@eecs.umich.edu // This will need a new way to tell if it's hooked up to a cache or not. 4284200Ssaidi@eecs.umich.edu if (req->isUncacheable()) 4294200Ssaidi@eecs.umich.edu recordEvent("Uncached Write"); 4303658Sktlim@umich.edu } else { 4313658Sktlim@umich.edu delete req; 4322623SN/A } 4332623SN/A 4342623SN/A 4352623SN/A // If the write needs to have a fault on the access, consider calling 4362623SN/A // changeStatus() and changing it to "bad addr write" or something. 4372623SN/A return fault; 4382623SN/A} 4392623SN/A 4405177Sgblack@eecs.umich.eduFault 4415177Sgblack@eecs.umich.eduTimingSimpleCPU::translateDataWriteAddr(Addr vaddr, Addr &paddr, 4425177Sgblack@eecs.umich.edu int size, unsigned flags) 4435177Sgblack@eecs.umich.edu{ 4445177Sgblack@eecs.umich.edu Request *req = 4455177Sgblack@eecs.umich.edu new Request(0, vaddr, size, flags, thread->readPC(), cpuId, 0); 4465177Sgblack@eecs.umich.edu 4475177Sgblack@eecs.umich.edu if (traceData) { 4485177Sgblack@eecs.umich.edu traceData->setAddr(vaddr); 4495177Sgblack@eecs.umich.edu } 4505177Sgblack@eecs.umich.edu 4515177Sgblack@eecs.umich.edu Fault fault = thread->translateDataWriteReq(req); 4525177Sgblack@eecs.umich.edu 4535177Sgblack@eecs.umich.edu if (fault == NoFault) 4545177Sgblack@eecs.umich.edu paddr = req->getPaddr(); 4555177Sgblack@eecs.umich.edu 4565177Sgblack@eecs.umich.edu delete req; 4575177Sgblack@eecs.umich.edu return fault; 4585177Sgblack@eecs.umich.edu} 4595177Sgblack@eecs.umich.edu 4602623SN/A 4612623SN/A#ifndef DOXYGEN_SHOULD_SKIP_THIS 4622623SN/Atemplate 4632623SN/AFault 4644224Sgblack@eecs.umich.eduTimingSimpleCPU::write(Twin32_t data, Addr addr, 4654224Sgblack@eecs.umich.edu unsigned flags, uint64_t *res); 4664224Sgblack@eecs.umich.edu 4674224Sgblack@eecs.umich.edutemplate 4684224Sgblack@eecs.umich.eduFault 4694224Sgblack@eecs.umich.eduTimingSimpleCPU::write(Twin64_t data, Addr addr, 4704224Sgblack@eecs.umich.edu unsigned flags, uint64_t *res); 4714224Sgblack@eecs.umich.edu 4724224Sgblack@eecs.umich.edutemplate 4734224Sgblack@eecs.umich.eduFault 4742623SN/ATimingSimpleCPU::write(uint64_t data, Addr addr, 4752623SN/A unsigned flags, uint64_t *res); 4762623SN/A 4772623SN/Atemplate 4782623SN/AFault 4792623SN/ATimingSimpleCPU::write(uint32_t data, Addr addr, 4802623SN/A unsigned flags, uint64_t *res); 4812623SN/A 4822623SN/Atemplate 4832623SN/AFault 4842623SN/ATimingSimpleCPU::write(uint16_t data, Addr addr, 4852623SN/A unsigned flags, uint64_t *res); 4862623SN/A 4872623SN/Atemplate 4882623SN/AFault 4892623SN/ATimingSimpleCPU::write(uint8_t data, Addr addr, 4902623SN/A unsigned flags, uint64_t *res); 4912623SN/A 4922623SN/A#endif //DOXYGEN_SHOULD_SKIP_THIS 4932623SN/A 4942623SN/Atemplate<> 4952623SN/AFault 4962623SN/ATimingSimpleCPU::write(double data, Addr addr, unsigned flags, uint64_t *res) 4972623SN/A{ 4982623SN/A return write(*(uint64_t*)&data, addr, flags, res); 4992623SN/A} 5002623SN/A 5012623SN/Atemplate<> 5022623SN/AFault 5032623SN/ATimingSimpleCPU::write(float data, Addr addr, unsigned flags, uint64_t *res) 5042623SN/A{ 5052623SN/A return write(*(uint32_t*)&data, addr, flags, res); 5062623SN/A} 5072623SN/A 5082623SN/A 5092623SN/Atemplate<> 5102623SN/AFault 5112623SN/ATimingSimpleCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res) 5122623SN/A{ 5132623SN/A return write((uint32_t)data, addr, flags, res); 5142623SN/A} 5152623SN/A 5162623SN/A 5172623SN/Avoid 5182623SN/ATimingSimpleCPU::fetch() 5192623SN/A{ 5205221Ssaidi@eecs.umich.edu DPRINTF(SimpleCPU, "Fetch\n"); 5215221Ssaidi@eecs.umich.edu 5223387Sgblack@eecs.umich.edu if (!curStaticInst || !curStaticInst->isDelayedCommit()) 5233387Sgblack@eecs.umich.edu checkForInterrupts(); 5242631SN/A 5255348Ssaidi@eecs.umich.edu checkPcEventQueue(); 5265348Ssaidi@eecs.umich.edu 5272663Sstever@eecs.umich.edu Request *ifetch_req = new Request(); 5285169Ssaidi@eecs.umich.edu ifetch_req->setThreadContext(cpuId, /* thread ID */ 0); 5292662Sstever@eecs.umich.edu Fault fault = setupFetchRequest(ifetch_req); 5302623SN/A 5314022Sstever@eecs.umich.edu ifetch_pkt = new Packet(ifetch_req, MemCmd::ReadReq, Packet::Broadcast); 5322623SN/A ifetch_pkt->dataStatic(&inst); 5332623SN/A 5342623SN/A if (fault == NoFault) { 5352630SN/A if (!icachePort.sendTiming(ifetch_pkt)) { 5362623SN/A // Need to wait for retry 5372623SN/A _status = IcacheRetry; 5382623SN/A } else { 5392623SN/A // Need to wait for cache to respond 5402623SN/A _status = IcacheWaitResponse; 5412623SN/A // ownership of packet transferred to memory system 5422623SN/A ifetch_pkt = NULL; 5432623SN/A } 5442623SN/A } else { 5453658Sktlim@umich.edu delete ifetch_req; 5463658Sktlim@umich.edu delete ifetch_pkt; 5472644Sstever@eecs.umich.edu // fetch fault: advance directly to next instruction (fault handler) 5482644Sstever@eecs.umich.edu advanceInst(fault); 5492623SN/A } 5503222Sktlim@umich.edu 5515099Ssaidi@eecs.umich.edu numCycles += tickToCycles(curTick - previousTick); 5523222Sktlim@umich.edu previousTick = curTick; 5532623SN/A} 5542623SN/A 5552623SN/A 5562623SN/Avoid 5572644Sstever@eecs.umich.eduTimingSimpleCPU::advanceInst(Fault fault) 5582623SN/A{ 5592623SN/A advancePC(fault); 5602623SN/A 5612631SN/A if (_status == Running) { 5622631SN/A // kick off fetch of next instruction... callback from icache 5632631SN/A // response will cause that instruction to be executed, 5642631SN/A // keeping the CPU running. 5652631SN/A fetch(); 5662631SN/A } 5672623SN/A} 5682623SN/A 5692623SN/A 5702623SN/Avoid 5713349Sbinkertn@umich.eduTimingSimpleCPU::completeIfetch(PacketPtr pkt) 5722623SN/A{ 5735221Ssaidi@eecs.umich.edu DPRINTF(SimpleCPU, "Complete ICache Fetch\n"); 5745221Ssaidi@eecs.umich.edu 5752623SN/A // received a response from the icache: execute the received 5762623SN/A // instruction 5774870Sstever@eecs.umich.edu assert(!pkt->isError()); 5782623SN/A assert(_status == IcacheWaitResponse); 5792798Sktlim@umich.edu 5802623SN/A _status = Running; 5812644Sstever@eecs.umich.edu 5825099Ssaidi@eecs.umich.edu numCycles += tickToCycles(curTick - previousTick); 5833222Sktlim@umich.edu previousTick = curTick; 5843222Sktlim@umich.edu 5852839Sktlim@umich.edu if (getState() == SimObject::Draining) { 5863658Sktlim@umich.edu delete pkt->req; 5873658Sktlim@umich.edu delete pkt; 5883658Sktlim@umich.edu 5892839Sktlim@umich.edu completeDrain(); 5902798Sktlim@umich.edu return; 5912798Sktlim@umich.edu } 5922798Sktlim@umich.edu 5932623SN/A preExecute(); 5942644Sstever@eecs.umich.edu if (curStaticInst->isMemRef() && !curStaticInst->isDataPrefetch()) { 5952623SN/A // load or store: just send to dcache 5962623SN/A Fault fault = curStaticInst->initiateAcc(this, traceData); 5973170Sstever@eecs.umich.edu if (_status != Running) { 5983170Sstever@eecs.umich.edu // instruction will complete in dcache response callback 5993170Sstever@eecs.umich.edu assert(_status == DcacheWaitResponse || _status == DcacheRetry); 6003170Sstever@eecs.umich.edu assert(fault == NoFault); 6012644Sstever@eecs.umich.edu } else { 6023170Sstever@eecs.umich.edu if (fault == NoFault) { 6035335Shines@cs.fsu.edu // Note that ARM can have NULL packets if the instruction gets 6045335Shines@cs.fsu.edu // squashed due to predication 6053170Sstever@eecs.umich.edu // early fail on store conditional: complete now 6065335Shines@cs.fsu.edu assert(dcache_pkt != NULL || THE_ISA == ARM_ISA); 6075335Shines@cs.fsu.edu 6083170Sstever@eecs.umich.edu fault = curStaticInst->completeAcc(dcache_pkt, this, 6093170Sstever@eecs.umich.edu traceData); 6105335Shines@cs.fsu.edu if (dcache_pkt != NULL) 6115335Shines@cs.fsu.edu { 6125335Shines@cs.fsu.edu delete dcache_pkt->req; 6135335Shines@cs.fsu.edu delete dcache_pkt; 6145335Shines@cs.fsu.edu dcache_pkt = NULL; 6155335Shines@cs.fsu.edu } 6164998Sgblack@eecs.umich.edu 6174998Sgblack@eecs.umich.edu // keep an instruction count 6184998Sgblack@eecs.umich.edu if (fault == NoFault) 6194998Sgblack@eecs.umich.edu countInst(); 6205001Sgblack@eecs.umich.edu } else if (traceData) { 6215001Sgblack@eecs.umich.edu // If there was a fault, we shouldn't trace this instruction. 6225001Sgblack@eecs.umich.edu delete traceData; 6235001Sgblack@eecs.umich.edu traceData = NULL; 6243170Sstever@eecs.umich.edu } 6254998Sgblack@eecs.umich.edu 6262644Sstever@eecs.umich.edu postExecute(); 6275103Ssaidi@eecs.umich.edu // @todo remove me after debugging with legion done 6285103Ssaidi@eecs.umich.edu if (curStaticInst && (!curStaticInst->isMicroop() || 6295103Ssaidi@eecs.umich.edu curStaticInst->isFirstMicroop())) 6305103Ssaidi@eecs.umich.edu instCnt++; 6312644Sstever@eecs.umich.edu advanceInst(fault); 6322644Sstever@eecs.umich.edu } 6332623SN/A } else { 6342623SN/A // non-memory instruction: execute completely now 6352623SN/A Fault fault = curStaticInst->execute(this, traceData); 6364998Sgblack@eecs.umich.edu 6374998Sgblack@eecs.umich.edu // keep an instruction count 6384998Sgblack@eecs.umich.edu if (fault == NoFault) 6394998Sgblack@eecs.umich.edu countInst(); 6405001Sgblack@eecs.umich.edu else if (traceData) { 6415001Sgblack@eecs.umich.edu // If there was a fault, we shouldn't trace this instruction. 6425001Sgblack@eecs.umich.edu delete traceData; 6435001Sgblack@eecs.umich.edu traceData = NULL; 6445001Sgblack@eecs.umich.edu } 6454998Sgblack@eecs.umich.edu 6462644Sstever@eecs.umich.edu postExecute(); 6475103Ssaidi@eecs.umich.edu // @todo remove me after debugging with legion done 6485103Ssaidi@eecs.umich.edu if (curStaticInst && (!curStaticInst->isMicroop() || 6495103Ssaidi@eecs.umich.edu curStaticInst->isFirstMicroop())) 6505103Ssaidi@eecs.umich.edu instCnt++; 6512644Sstever@eecs.umich.edu advanceInst(fault); 6522623SN/A } 6533658Sktlim@umich.edu 6543658Sktlim@umich.edu delete pkt->req; 6553658Sktlim@umich.edu delete pkt; 6562623SN/A} 6572623SN/A 6582948Ssaidi@eecs.umich.eduvoid 6592948Ssaidi@eecs.umich.eduTimingSimpleCPU::IcachePort::ITickEvent::process() 6602948Ssaidi@eecs.umich.edu{ 6612948Ssaidi@eecs.umich.edu cpu->completeIfetch(pkt); 6622948Ssaidi@eecs.umich.edu} 6632623SN/A 6642623SN/Abool 6653349Sbinkertn@umich.eduTimingSimpleCPU::IcachePort::recvTiming(PacketPtr pkt) 6662623SN/A{ 6674986Ssaidi@eecs.umich.edu if (pkt->isResponse() && !pkt->wasNacked()) { 6683310Srdreslin@umich.edu // delay processing of returned data until next CPU clock edge 6694584Ssaidi@eecs.umich.edu Tick next_tick = cpu->nextCycle(curTick); 6702948Ssaidi@eecs.umich.edu 6713495Sktlim@umich.edu if (next_tick == curTick) 6723310Srdreslin@umich.edu cpu->completeIfetch(pkt); 6733310Srdreslin@umich.edu else 6743495Sktlim@umich.edu tickEvent.schedule(pkt, next_tick); 6752948Ssaidi@eecs.umich.edu 6763310Srdreslin@umich.edu return true; 6773310Srdreslin@umich.edu } 6784870Sstever@eecs.umich.edu else if (pkt->wasNacked()) { 6794433Ssaidi@eecs.umich.edu assert(cpu->_status == IcacheWaitResponse); 6804433Ssaidi@eecs.umich.edu pkt->reinitNacked(); 6814433Ssaidi@eecs.umich.edu if (!sendTiming(pkt)) { 6824433Ssaidi@eecs.umich.edu cpu->_status = IcacheRetry; 6834433Ssaidi@eecs.umich.edu cpu->ifetch_pkt = pkt; 6844433Ssaidi@eecs.umich.edu } 6853310Srdreslin@umich.edu } 6864433Ssaidi@eecs.umich.edu //Snooping a Coherence Request, do nothing 6874433Ssaidi@eecs.umich.edu return true; 6882623SN/A} 6892623SN/A 6902657Ssaidi@eecs.umich.eduvoid 6912623SN/ATimingSimpleCPU::IcachePort::recvRetry() 6922623SN/A{ 6932623SN/A // we shouldn't get a retry unless we have a packet that we're 6942623SN/A // waiting to transmit 6952623SN/A assert(cpu->ifetch_pkt != NULL); 6962623SN/A assert(cpu->_status == IcacheRetry); 6973349Sbinkertn@umich.edu PacketPtr tmp = cpu->ifetch_pkt; 6982657Ssaidi@eecs.umich.edu if (sendTiming(tmp)) { 6992657Ssaidi@eecs.umich.edu cpu->_status = IcacheWaitResponse; 7002657Ssaidi@eecs.umich.edu cpu->ifetch_pkt = NULL; 7012657Ssaidi@eecs.umich.edu } 7022623SN/A} 7032623SN/A 7042623SN/Avoid 7053349Sbinkertn@umich.eduTimingSimpleCPU::completeDataAccess(PacketPtr pkt) 7062623SN/A{ 7072623SN/A // received a response from the dcache: complete the load or store 7082623SN/A // instruction 7094870Sstever@eecs.umich.edu assert(!pkt->isError()); 7102623SN/A assert(_status == DcacheWaitResponse); 7112623SN/A _status = Running; 7122623SN/A 7135099Ssaidi@eecs.umich.edu numCycles += tickToCycles(curTick - previousTick); 7143222Sktlim@umich.edu previousTick = curTick; 7153184Srdreslin@umich.edu 7162623SN/A Fault fault = curStaticInst->completeAcc(pkt, this, traceData); 7172623SN/A 7184998Sgblack@eecs.umich.edu // keep an instruction count 7194998Sgblack@eecs.umich.edu if (fault == NoFault) 7204998Sgblack@eecs.umich.edu countInst(); 7215001Sgblack@eecs.umich.edu else if (traceData) { 7225001Sgblack@eecs.umich.edu // If there was a fault, we shouldn't trace this instruction. 7235001Sgblack@eecs.umich.edu delete traceData; 7245001Sgblack@eecs.umich.edu traceData = NULL; 7255001Sgblack@eecs.umich.edu } 7264998Sgblack@eecs.umich.edu 7274878Sstever@eecs.umich.edu if (pkt->isRead() && pkt->isLocked()) { 7283170Sstever@eecs.umich.edu TheISA::handleLockedRead(thread, pkt->req); 7293170Sstever@eecs.umich.edu } 7303170Sstever@eecs.umich.edu 7312644Sstever@eecs.umich.edu delete pkt->req; 7322644Sstever@eecs.umich.edu delete pkt; 7332644Sstever@eecs.umich.edu 7343184Srdreslin@umich.edu postExecute(); 7353227Sktlim@umich.edu 7363201Shsul@eecs.umich.edu if (getState() == SimObject::Draining) { 7373201Shsul@eecs.umich.edu advancePC(fault); 7383201Shsul@eecs.umich.edu completeDrain(); 7393201Shsul@eecs.umich.edu 7403201Shsul@eecs.umich.edu return; 7413201Shsul@eecs.umich.edu } 7423201Shsul@eecs.umich.edu 7432644Sstever@eecs.umich.edu advanceInst(fault); 7442623SN/A} 7452623SN/A 7462623SN/A 7472798Sktlim@umich.eduvoid 7482839Sktlim@umich.eduTimingSimpleCPU::completeDrain() 7492798Sktlim@umich.edu{ 7502839Sktlim@umich.edu DPRINTF(Config, "Done draining\n"); 7512901Ssaidi@eecs.umich.edu changeState(SimObject::Drained); 7522839Sktlim@umich.edu drainEvent->process(); 7532798Sktlim@umich.edu} 7542623SN/A 7554192Sktlim@umich.eduvoid 7564192Sktlim@umich.eduTimingSimpleCPU::DcachePort::setPeer(Port *port) 7574192Sktlim@umich.edu{ 7584192Sktlim@umich.edu Port::setPeer(port); 7594192Sktlim@umich.edu 7604192Sktlim@umich.edu#if FULL_SYSTEM 7614192Sktlim@umich.edu // Update the ThreadContext's memory ports (Functional/Virtual 7624192Sktlim@umich.edu // Ports) 7634192Sktlim@umich.edu cpu->tcBase()->connectMemPorts(); 7644192Sktlim@umich.edu#endif 7654192Sktlim@umich.edu} 7664192Sktlim@umich.edu 7672623SN/Abool 7683349Sbinkertn@umich.eduTimingSimpleCPU::DcachePort::recvTiming(PacketPtr pkt) 7692623SN/A{ 7704986Ssaidi@eecs.umich.edu if (pkt->isResponse() && !pkt->wasNacked()) { 7713310Srdreslin@umich.edu // delay processing of returned data until next CPU clock edge 7724584Ssaidi@eecs.umich.edu Tick next_tick = cpu->nextCycle(curTick); 7732948Ssaidi@eecs.umich.edu 7743495Sktlim@umich.edu if (next_tick == curTick) 7753310Srdreslin@umich.edu cpu->completeDataAccess(pkt); 7763310Srdreslin@umich.edu else 7773495Sktlim@umich.edu tickEvent.schedule(pkt, next_tick); 7782948Ssaidi@eecs.umich.edu 7793310Srdreslin@umich.edu return true; 7803310Srdreslin@umich.edu } 7814870Sstever@eecs.umich.edu else if (pkt->wasNacked()) { 7824433Ssaidi@eecs.umich.edu assert(cpu->_status == DcacheWaitResponse); 7834433Ssaidi@eecs.umich.edu pkt->reinitNacked(); 7844433Ssaidi@eecs.umich.edu if (!sendTiming(pkt)) { 7854433Ssaidi@eecs.umich.edu cpu->_status = DcacheRetry; 7864433Ssaidi@eecs.umich.edu cpu->dcache_pkt = pkt; 7874433Ssaidi@eecs.umich.edu } 7883310Srdreslin@umich.edu } 7894433Ssaidi@eecs.umich.edu //Snooping a Coherence Request, do nothing 7904433Ssaidi@eecs.umich.edu return true; 7912948Ssaidi@eecs.umich.edu} 7922948Ssaidi@eecs.umich.edu 7932948Ssaidi@eecs.umich.eduvoid 7942948Ssaidi@eecs.umich.eduTimingSimpleCPU::DcachePort::DTickEvent::process() 7952948Ssaidi@eecs.umich.edu{ 7962630SN/A cpu->completeDataAccess(pkt); 7972623SN/A} 7982623SN/A 7992657Ssaidi@eecs.umich.eduvoid 8002623SN/ATimingSimpleCPU::DcachePort::recvRetry() 8012623SN/A{ 8022623SN/A // we shouldn't get a retry unless we have a packet that we're 8032623SN/A // waiting to transmit 8042623SN/A assert(cpu->dcache_pkt != NULL); 8052623SN/A assert(cpu->_status == DcacheRetry); 8063349Sbinkertn@umich.edu PacketPtr tmp = cpu->dcache_pkt; 8072657Ssaidi@eecs.umich.edu if (sendTiming(tmp)) { 8082657Ssaidi@eecs.umich.edu cpu->_status = DcacheWaitResponse; 8093170Sstever@eecs.umich.edu // memory system takes ownership of packet 8102657Ssaidi@eecs.umich.edu cpu->dcache_pkt = NULL; 8112657Ssaidi@eecs.umich.edu } 8122623SN/A} 8132623SN/A 8145103Ssaidi@eecs.umich.eduTimingSimpleCPU::IprEvent::IprEvent(Packet *_pkt, TimingSimpleCPU *_cpu, Tick t) 8155103Ssaidi@eecs.umich.edu : Event(&mainEventQueue), pkt(_pkt), cpu(_cpu) 8165103Ssaidi@eecs.umich.edu{ 8175103Ssaidi@eecs.umich.edu schedule(t); 8185103Ssaidi@eecs.umich.edu} 8195103Ssaidi@eecs.umich.edu 8205103Ssaidi@eecs.umich.eduvoid 8215103Ssaidi@eecs.umich.eduTimingSimpleCPU::IprEvent::process() 8225103Ssaidi@eecs.umich.edu{ 8235103Ssaidi@eecs.umich.edu cpu->completeDataAccess(pkt); 8245103Ssaidi@eecs.umich.edu} 8255103Ssaidi@eecs.umich.edu 8265103Ssaidi@eecs.umich.educonst char * 8275336Shines@cs.fsu.eduTimingSimpleCPU::IprEvent::description() const 8285103Ssaidi@eecs.umich.edu{ 8295103Ssaidi@eecs.umich.edu return "Timing Simple CPU Delay IPR event"; 8305103Ssaidi@eecs.umich.edu} 8315103Ssaidi@eecs.umich.edu 8322623SN/A 8335315Sstever@gmail.comvoid 8345315Sstever@gmail.comTimingSimpleCPU::printAddr(Addr a) 8355315Sstever@gmail.com{ 8365315Sstever@gmail.com dcachePort.printAddr(a); 8375315Sstever@gmail.com} 8385315Sstever@gmail.com 8395315Sstever@gmail.com 8402623SN/A//////////////////////////////////////////////////////////////////////// 8412623SN/A// 8422623SN/A// TimingSimpleCPU Simulation Object 8432623SN/A// 8444762Snate@binkert.orgTimingSimpleCPU * 8454762Snate@binkert.orgTimingSimpleCPUParams::create() 8462623SN/A{ 8472623SN/A TimingSimpleCPU::Params *params = new TimingSimpleCPU::Params(); 8484762Snate@binkert.org params->name = name; 8492623SN/A params->numberOfThreads = 1; 8502623SN/A params->max_insts_any_thread = max_insts_any_thread; 8512623SN/A params->max_insts_all_threads = max_insts_all_threads; 8522623SN/A params->max_loads_any_thread = max_loads_any_thread; 8532623SN/A params->max_loads_all_threads = max_loads_all_threads; 8543119Sktlim@umich.edu params->progress_interval = progress_interval; 8552623SN/A params->deferRegistration = defer_registration; 8562623SN/A params->clock = clock; 8573661Srdreslin@umich.edu params->phase = phase; 8582623SN/A params->functionTrace = function_trace; 8592623SN/A params->functionTraceStart = function_trace_start; 8602901Ssaidi@eecs.umich.edu params->system = system; 8613170Sstever@eecs.umich.edu params->cpu_id = cpu_id; 8624776Sgblack@eecs.umich.edu params->tracer = tracer; 8632623SN/A 8642623SN/A params->itb = itb; 8652623SN/A params->dtb = dtb; 8664997Sgblack@eecs.umich.edu#if FULL_SYSTEM 8672623SN/A params->profile = profile; 8683617Sbinkertn@umich.edu params->do_quiesce = do_quiesce; 8693617Sbinkertn@umich.edu params->do_checkpoint_insts = do_checkpoint_insts; 8703617Sbinkertn@umich.edu params->do_statistics_insts = do_statistics_insts; 8712623SN/A#else 8724762Snate@binkert.org if (workload.size() != 1) 8734762Snate@binkert.org panic("only one workload allowed"); 8744762Snate@binkert.org params->process = workload[0]; 8752623SN/A#endif 8762623SN/A 8772623SN/A TimingSimpleCPU *cpu = new TimingSimpleCPU(params); 8782623SN/A return cpu; 8792623SN/A} 880