timing.cc revision 4878
12623SN/A/* 22623SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 32623SN/A * All rights reserved. 42623SN/A * 52623SN/A * Redistribution and use in source and binary forms, with or without 62623SN/A * modification, are permitted provided that the following conditions are 72623SN/A * met: redistributions of source code must retain the above copyright 82623SN/A * notice, this list of conditions and the following disclaimer; 92623SN/A * redistributions in binary form must reproduce the above copyright 102623SN/A * notice, this list of conditions and the following disclaimer in the 112623SN/A * documentation and/or other materials provided with the distribution; 122623SN/A * neither the name of the copyright holders nor the names of its 132623SN/A * contributors may be used to endorse or promote products derived from 142623SN/A * this software without specific prior written permission. 152623SN/A * 162623SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172623SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182623SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192623SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202623SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212623SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222623SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232623SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242623SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252623SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262623SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 292623SN/A */ 302623SN/A 313170Sstever@eecs.umich.edu#include "arch/locked_mem.hh" 322623SN/A#include "arch/utility.hh" 334040Ssaidi@eecs.umich.edu#include "base/bigint.hh" 342623SN/A#include "cpu/exetrace.hh" 352623SN/A#include "cpu/simple/timing.hh" 363348Sbinkertn@umich.edu#include "mem/packet.hh" 373348Sbinkertn@umich.edu#include "mem/packet_access.hh" 382623SN/A#include "sim/builder.hh" 392901Ssaidi@eecs.umich.edu#include "sim/system.hh" 402623SN/A 412623SN/Ausing namespace std; 422623SN/Ausing namespace TheISA; 432623SN/A 442856Srdreslin@umich.eduPort * 452856Srdreslin@umich.eduTimingSimpleCPU::getPort(const std::string &if_name, int idx) 462856Srdreslin@umich.edu{ 472856Srdreslin@umich.edu if (if_name == "dcache_port") 482856Srdreslin@umich.edu return &dcachePort; 492856Srdreslin@umich.edu else if (if_name == "icache_port") 502856Srdreslin@umich.edu return &icachePort; 512856Srdreslin@umich.edu else 522856Srdreslin@umich.edu panic("No Such Port\n"); 532856Srdreslin@umich.edu} 542623SN/A 552623SN/Avoid 562623SN/ATimingSimpleCPU::init() 572623SN/A{ 582623SN/A BaseCPU::init(); 592623SN/A#if FULL_SYSTEM 602680Sktlim@umich.edu for (int i = 0; i < threadContexts.size(); ++i) { 612680Sktlim@umich.edu ThreadContext *tc = threadContexts[i]; 622623SN/A 632623SN/A // initialize CPU, including PC 642680Sktlim@umich.edu TheISA::initCPU(tc, tc->readCpuId()); 652623SN/A } 662623SN/A#endif 672623SN/A} 682623SN/A 692623SN/ATick 703349Sbinkertn@umich.eduTimingSimpleCPU::CpuPort::recvAtomic(PacketPtr pkt) 712623SN/A{ 722623SN/A panic("TimingSimpleCPU doesn't expect recvAtomic callback!"); 732623SN/A return curTick; 742623SN/A} 752623SN/A 762623SN/Avoid 773349Sbinkertn@umich.eduTimingSimpleCPU::CpuPort::recvFunctional(PacketPtr pkt) 782623SN/A{ 793184Srdreslin@umich.edu //No internal storage to update, jusst return 803184Srdreslin@umich.edu return; 812623SN/A} 822623SN/A 832623SN/Avoid 842623SN/ATimingSimpleCPU::CpuPort::recvStatusChange(Status status) 852623SN/A{ 863647Srdreslin@umich.edu if (status == RangeChange) { 873647Srdreslin@umich.edu if (!snoopRangeSent) { 883647Srdreslin@umich.edu snoopRangeSent = true; 893647Srdreslin@umich.edu sendStatusChange(Port::RangeChange); 903647Srdreslin@umich.edu } 912631SN/A return; 923647Srdreslin@umich.edu } 932631SN/A 942623SN/A panic("TimingSimpleCPU doesn't expect recvStatusChange callback!"); 952623SN/A} 962623SN/A 972948Ssaidi@eecs.umich.edu 982948Ssaidi@eecs.umich.eduvoid 993349Sbinkertn@umich.eduTimingSimpleCPU::CpuPort::TickEvent::schedule(PacketPtr _pkt, Tick t) 1002948Ssaidi@eecs.umich.edu{ 1012948Ssaidi@eecs.umich.edu pkt = _pkt; 1022948Ssaidi@eecs.umich.edu Event::schedule(t); 1032948Ssaidi@eecs.umich.edu} 1042948Ssaidi@eecs.umich.edu 1052623SN/ATimingSimpleCPU::TimingSimpleCPU(Params *p) 1063170Sstever@eecs.umich.edu : BaseSimpleCPU(p), icachePort(this, p->clock), dcachePort(this, p->clock), 1073170Sstever@eecs.umich.edu cpu_id(p->cpu_id) 1082623SN/A{ 1092623SN/A _status = Idle; 1103647Srdreslin@umich.edu 1113647Srdreslin@umich.edu icachePort.snoopRangeSent = false; 1123647Srdreslin@umich.edu dcachePort.snoopRangeSent = false; 1133647Srdreslin@umich.edu 1142623SN/A ifetch_pkt = dcache_pkt = NULL; 1152839Sktlim@umich.edu drainEvent = NULL; 1162867Sktlim@umich.edu fetchEvent = NULL; 1173222Sktlim@umich.edu previousTick = 0; 1182901Ssaidi@eecs.umich.edu changeState(SimObject::Running); 1192623SN/A} 1202623SN/A 1212623SN/A 1222623SN/ATimingSimpleCPU::~TimingSimpleCPU() 1232623SN/A{ 1242623SN/A} 1252623SN/A 1262623SN/Avoid 1272623SN/ATimingSimpleCPU::serialize(ostream &os) 1282623SN/A{ 1292915Sktlim@umich.edu SimObject::State so_state = SimObject::getState(); 1302915Sktlim@umich.edu SERIALIZE_ENUM(so_state); 1312623SN/A BaseSimpleCPU::serialize(os); 1322623SN/A} 1332623SN/A 1342623SN/Avoid 1352623SN/ATimingSimpleCPU::unserialize(Checkpoint *cp, const string §ion) 1362623SN/A{ 1372915Sktlim@umich.edu SimObject::State so_state; 1382915Sktlim@umich.edu UNSERIALIZE_ENUM(so_state); 1392623SN/A BaseSimpleCPU::unserialize(cp, section); 1402798Sktlim@umich.edu} 1412798Sktlim@umich.edu 1422901Ssaidi@eecs.umich.eduunsigned int 1432839Sktlim@umich.eduTimingSimpleCPU::drain(Event *drain_event) 1442798Sktlim@umich.edu{ 1452839Sktlim@umich.edu // TimingSimpleCPU is ready to drain if it's not waiting for 1462798Sktlim@umich.edu // an access to complete. 1472798Sktlim@umich.edu if (status() == Idle || status() == Running || status() == SwitchedOut) { 1482901Ssaidi@eecs.umich.edu changeState(SimObject::Drained); 1492901Ssaidi@eecs.umich.edu return 0; 1502798Sktlim@umich.edu } else { 1512839Sktlim@umich.edu changeState(SimObject::Draining); 1522839Sktlim@umich.edu drainEvent = drain_event; 1532901Ssaidi@eecs.umich.edu return 1; 1542798Sktlim@umich.edu } 1552623SN/A} 1562623SN/A 1572623SN/Avoid 1582798Sktlim@umich.eduTimingSimpleCPU::resume() 1592623SN/A{ 1602798Sktlim@umich.edu if (_status != SwitchedOut && _status != Idle) { 1613201Shsul@eecs.umich.edu assert(system->getMemoryMode() == System::Timing); 1623201Shsul@eecs.umich.edu 1632867Sktlim@umich.edu // Delete the old event if it existed. 1642867Sktlim@umich.edu if (fetchEvent) { 1652915Sktlim@umich.edu if (fetchEvent->scheduled()) 1662915Sktlim@umich.edu fetchEvent->deschedule(); 1672915Sktlim@umich.edu 1682867Sktlim@umich.edu delete fetchEvent; 1692867Sktlim@umich.edu } 1702867Sktlim@umich.edu 1714471Sstever@eecs.umich.edu fetchEvent = new FetchEvent(this, nextCycle()); 1722623SN/A } 1732798Sktlim@umich.edu 1742901Ssaidi@eecs.umich.edu changeState(SimObject::Running); 1753222Sktlim@umich.edu previousTick = curTick; 1762798Sktlim@umich.edu} 1772798Sktlim@umich.edu 1782798Sktlim@umich.eduvoid 1792798Sktlim@umich.eduTimingSimpleCPU::switchOut() 1802798Sktlim@umich.edu{ 1812798Sktlim@umich.edu assert(status() == Running || status() == Idle); 1822798Sktlim@umich.edu _status = SwitchedOut; 1833222Sktlim@umich.edu numCycles += curTick - previousTick; 1842867Sktlim@umich.edu 1852867Sktlim@umich.edu // If we've been scheduled to resume but are then told to switch out, 1862867Sktlim@umich.edu // we'll need to cancel it. 1872867Sktlim@umich.edu if (fetchEvent && fetchEvent->scheduled()) 1882867Sktlim@umich.edu fetchEvent->deschedule(); 1892623SN/A} 1902623SN/A 1912623SN/A 1922623SN/Avoid 1932623SN/ATimingSimpleCPU::takeOverFrom(BaseCPU *oldCPU) 1942623SN/A{ 1954192Sktlim@umich.edu BaseCPU::takeOverFrom(oldCPU, &icachePort, &dcachePort); 1962623SN/A 1972680Sktlim@umich.edu // if any of this CPU's ThreadContexts are active, mark the CPU as 1982623SN/A // running and schedule its tick event. 1992680Sktlim@umich.edu for (int i = 0; i < threadContexts.size(); ++i) { 2002680Sktlim@umich.edu ThreadContext *tc = threadContexts[i]; 2012680Sktlim@umich.edu if (tc->status() == ThreadContext::Active && _status != Running) { 2022623SN/A _status = Running; 2032623SN/A break; 2042623SN/A } 2052623SN/A } 2063201Shsul@eecs.umich.edu 2073201Shsul@eecs.umich.edu if (_status != Running) { 2083201Shsul@eecs.umich.edu _status = Idle; 2093201Shsul@eecs.umich.edu } 2102623SN/A} 2112623SN/A 2122623SN/A 2132623SN/Avoid 2142623SN/ATimingSimpleCPU::activateContext(int thread_num, int delay) 2152623SN/A{ 2162623SN/A assert(thread_num == 0); 2172683Sktlim@umich.edu assert(thread); 2182623SN/A 2192623SN/A assert(_status == Idle); 2202623SN/A 2212623SN/A notIdleFraction++; 2222623SN/A _status = Running; 2233686Sktlim@umich.edu 2242623SN/A // kick things off by initiating the fetch of the next instruction 2254471Sstever@eecs.umich.edu fetchEvent = new FetchEvent(this, nextCycle(curTick + cycles(delay))); 2262623SN/A} 2272623SN/A 2282623SN/A 2292623SN/Avoid 2302623SN/ATimingSimpleCPU::suspendContext(int thread_num) 2312623SN/A{ 2322623SN/A assert(thread_num == 0); 2332683Sktlim@umich.edu assert(thread); 2342623SN/A 2352644Sstever@eecs.umich.edu assert(_status == Running); 2362623SN/A 2372644Sstever@eecs.umich.edu // just change status to Idle... if status != Running, 2382644Sstever@eecs.umich.edu // completeInst() will not initiate fetch of next instruction. 2392623SN/A 2402623SN/A notIdleFraction--; 2412623SN/A _status = Idle; 2422623SN/A} 2432623SN/A 2442623SN/A 2452623SN/Atemplate <class T> 2462623SN/AFault 2472623SN/ATimingSimpleCPU::read(Addr addr, T &data, unsigned flags) 2482623SN/A{ 2493169Sstever@eecs.umich.edu Request *req = 2503169Sstever@eecs.umich.edu new Request(/* asid */ 0, addr, sizeof(T), flags, thread->readPC(), 2513170Sstever@eecs.umich.edu cpu_id, /* thread ID */ 0); 2522623SN/A 2532623SN/A if (traceData) { 2543169Sstever@eecs.umich.edu traceData->setAddr(req->getVaddr()); 2552623SN/A } 2562623SN/A 2572623SN/A // translate to physical address 2583169Sstever@eecs.umich.edu Fault fault = thread->translateDataReadReq(req); 2592623SN/A 2602623SN/A // Now do the access. 2612623SN/A if (fault == NoFault) { 2623349Sbinkertn@umich.edu PacketPtr pkt = 2634878Sstever@eecs.umich.edu new Packet(req, 2644878Sstever@eecs.umich.edu (req->isLocked() ? 2654878Sstever@eecs.umich.edu MemCmd::LoadLockedReq : MemCmd::ReadReq), 2664878Sstever@eecs.umich.edu Packet::Broadcast); 2673169Sstever@eecs.umich.edu pkt->dataDynamic<T>(new T); 2682623SN/A 2693169Sstever@eecs.umich.edu if (!dcachePort.sendTiming(pkt)) { 2702623SN/A _status = DcacheRetry; 2713169Sstever@eecs.umich.edu dcache_pkt = pkt; 2722623SN/A } else { 2732623SN/A _status = DcacheWaitResponse; 2743169Sstever@eecs.umich.edu // memory system takes ownership of packet 2752623SN/A dcache_pkt = NULL; 2762623SN/A } 2774200Ssaidi@eecs.umich.edu 2784200Ssaidi@eecs.umich.edu // This will need a new way to tell if it has a dcache attached. 2794200Ssaidi@eecs.umich.edu if (req->isUncacheable()) 2804200Ssaidi@eecs.umich.edu recordEvent("Uncached Read"); 2813658Sktlim@umich.edu } else { 2823658Sktlim@umich.edu delete req; 2832623SN/A } 2842623SN/A 2852623SN/A return fault; 2862623SN/A} 2872623SN/A 2882623SN/A#ifndef DOXYGEN_SHOULD_SKIP_THIS 2892623SN/A 2902623SN/Atemplate 2912623SN/AFault 2924040Ssaidi@eecs.umich.eduTimingSimpleCPU::read(Addr addr, Twin64_t &data, unsigned flags); 2934040Ssaidi@eecs.umich.edu 2944040Ssaidi@eecs.umich.edutemplate 2954040Ssaidi@eecs.umich.eduFault 2964115Ssaidi@eecs.umich.eduTimingSimpleCPU::read(Addr addr, Twin32_t &data, unsigned flags); 2974115Ssaidi@eecs.umich.edu 2984115Ssaidi@eecs.umich.edutemplate 2994115Ssaidi@eecs.umich.eduFault 3002623SN/ATimingSimpleCPU::read(Addr addr, uint64_t &data, unsigned flags); 3012623SN/A 3022623SN/Atemplate 3032623SN/AFault 3042623SN/ATimingSimpleCPU::read(Addr addr, uint32_t &data, unsigned flags); 3052623SN/A 3062623SN/Atemplate 3072623SN/AFault 3082623SN/ATimingSimpleCPU::read(Addr addr, uint16_t &data, unsigned flags); 3092623SN/A 3102623SN/Atemplate 3112623SN/AFault 3122623SN/ATimingSimpleCPU::read(Addr addr, uint8_t &data, unsigned flags); 3132623SN/A 3142623SN/A#endif //DOXYGEN_SHOULD_SKIP_THIS 3152623SN/A 3162623SN/Atemplate<> 3172623SN/AFault 3182623SN/ATimingSimpleCPU::read(Addr addr, double &data, unsigned flags) 3192623SN/A{ 3202623SN/A return read(addr, *(uint64_t*)&data, flags); 3212623SN/A} 3222623SN/A 3232623SN/Atemplate<> 3242623SN/AFault 3252623SN/ATimingSimpleCPU::read(Addr addr, float &data, unsigned flags) 3262623SN/A{ 3272623SN/A return read(addr, *(uint32_t*)&data, flags); 3282623SN/A} 3292623SN/A 3302623SN/A 3312623SN/Atemplate<> 3322623SN/AFault 3332623SN/ATimingSimpleCPU::read(Addr addr, int32_t &data, unsigned flags) 3342623SN/A{ 3352623SN/A return read(addr, (uint32_t&)data, flags); 3362623SN/A} 3372623SN/A 3382623SN/A 3392623SN/Atemplate <class T> 3402623SN/AFault 3412623SN/ATimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res) 3422623SN/A{ 3433169Sstever@eecs.umich.edu Request *req = 3443169Sstever@eecs.umich.edu new Request(/* asid */ 0, addr, sizeof(T), flags, thread->readPC(), 3453170Sstever@eecs.umich.edu cpu_id, /* thread ID */ 0); 3462623SN/A 3474040Ssaidi@eecs.umich.edu if (traceData) { 3484040Ssaidi@eecs.umich.edu traceData->setAddr(req->getVaddr()); 3494040Ssaidi@eecs.umich.edu } 3504040Ssaidi@eecs.umich.edu 3512623SN/A // translate to physical address 3523169Sstever@eecs.umich.edu Fault fault = thread->translateDataWriteReq(req); 3533169Sstever@eecs.umich.edu 3542623SN/A // Now do the access. 3552623SN/A if (fault == NoFault) { 3564878Sstever@eecs.umich.edu MemCmd cmd = MemCmd::WriteReq; // default 3573170Sstever@eecs.umich.edu bool do_access = true; // flag to suppress cache access 3583170Sstever@eecs.umich.edu 3594878Sstever@eecs.umich.edu assert(dcache_pkt == NULL); 3604878Sstever@eecs.umich.edu 3613170Sstever@eecs.umich.edu if (req->isLocked()) { 3624878Sstever@eecs.umich.edu cmd = MemCmd::StoreCondReq; 3633170Sstever@eecs.umich.edu do_access = TheISA::handleLockedWrite(thread, req); 3644878Sstever@eecs.umich.edu } else if (req->isSwap()) { 3654878Sstever@eecs.umich.edu cmd = MemCmd::SwapReq; 3664878Sstever@eecs.umich.edu if (req->isCondSwap()) { 3674878Sstever@eecs.umich.edu assert(res); 3684878Sstever@eecs.umich.edu req->setExtraData(*res); 3694878Sstever@eecs.umich.edu } 3704040Ssaidi@eecs.umich.edu } 3713170Sstever@eecs.umich.edu 3723170Sstever@eecs.umich.edu if (do_access) { 3734878Sstever@eecs.umich.edu dcache_pkt = new Packet(req, MemCmd::WriteReq, Packet::Broadcast); 3744878Sstever@eecs.umich.edu dcache_pkt->allocate(); 3754878Sstever@eecs.umich.edu dcache_pkt->set(data); 3764878Sstever@eecs.umich.edu 3773170Sstever@eecs.umich.edu if (!dcachePort.sendTiming(dcache_pkt)) { 3783170Sstever@eecs.umich.edu _status = DcacheRetry; 3793170Sstever@eecs.umich.edu } else { 3803170Sstever@eecs.umich.edu _status = DcacheWaitResponse; 3813170Sstever@eecs.umich.edu // memory system takes ownership of packet 3823170Sstever@eecs.umich.edu dcache_pkt = NULL; 3833170Sstever@eecs.umich.edu } 3842623SN/A } 3854200Ssaidi@eecs.umich.edu // This will need a new way to tell if it's hooked up to a cache or not. 3864200Ssaidi@eecs.umich.edu if (req->isUncacheable()) 3874200Ssaidi@eecs.umich.edu recordEvent("Uncached Write"); 3883658Sktlim@umich.edu } else { 3893658Sktlim@umich.edu delete req; 3902623SN/A } 3912623SN/A 3922623SN/A 3932623SN/A // If the write needs to have a fault on the access, consider calling 3942623SN/A // changeStatus() and changing it to "bad addr write" or something. 3952623SN/A return fault; 3962623SN/A} 3972623SN/A 3982623SN/A 3992623SN/A#ifndef DOXYGEN_SHOULD_SKIP_THIS 4002623SN/Atemplate 4012623SN/AFault 4024224Sgblack@eecs.umich.eduTimingSimpleCPU::write(Twin32_t data, Addr addr, 4034224Sgblack@eecs.umich.edu unsigned flags, uint64_t *res); 4044224Sgblack@eecs.umich.edu 4054224Sgblack@eecs.umich.edutemplate 4064224Sgblack@eecs.umich.eduFault 4074224Sgblack@eecs.umich.eduTimingSimpleCPU::write(Twin64_t data, Addr addr, 4084224Sgblack@eecs.umich.edu unsigned flags, uint64_t *res); 4094224Sgblack@eecs.umich.edu 4104224Sgblack@eecs.umich.edutemplate 4114224Sgblack@eecs.umich.eduFault 4122623SN/ATimingSimpleCPU::write(uint64_t data, Addr addr, 4132623SN/A unsigned flags, uint64_t *res); 4142623SN/A 4152623SN/Atemplate 4162623SN/AFault 4172623SN/ATimingSimpleCPU::write(uint32_t data, Addr addr, 4182623SN/A unsigned flags, uint64_t *res); 4192623SN/A 4202623SN/Atemplate 4212623SN/AFault 4222623SN/ATimingSimpleCPU::write(uint16_t data, Addr addr, 4232623SN/A unsigned flags, uint64_t *res); 4242623SN/A 4252623SN/Atemplate 4262623SN/AFault 4272623SN/ATimingSimpleCPU::write(uint8_t data, Addr addr, 4282623SN/A unsigned flags, uint64_t *res); 4292623SN/A 4302623SN/A#endif //DOXYGEN_SHOULD_SKIP_THIS 4312623SN/A 4322623SN/Atemplate<> 4332623SN/AFault 4342623SN/ATimingSimpleCPU::write(double data, Addr addr, unsigned flags, uint64_t *res) 4352623SN/A{ 4362623SN/A return write(*(uint64_t*)&data, addr, flags, res); 4372623SN/A} 4382623SN/A 4392623SN/Atemplate<> 4402623SN/AFault 4412623SN/ATimingSimpleCPU::write(float data, Addr addr, unsigned flags, uint64_t *res) 4422623SN/A{ 4432623SN/A return write(*(uint32_t*)&data, addr, flags, res); 4442623SN/A} 4452623SN/A 4462623SN/A 4472623SN/Atemplate<> 4482623SN/AFault 4492623SN/ATimingSimpleCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res) 4502623SN/A{ 4512623SN/A return write((uint32_t)data, addr, flags, res); 4522623SN/A} 4532623SN/A 4542623SN/A 4552623SN/Avoid 4562623SN/ATimingSimpleCPU::fetch() 4572623SN/A{ 4583387Sgblack@eecs.umich.edu if (!curStaticInst || !curStaticInst->isDelayedCommit()) 4593387Sgblack@eecs.umich.edu checkForInterrupts(); 4602631SN/A 4612663Sstever@eecs.umich.edu Request *ifetch_req = new Request(); 4623170Sstever@eecs.umich.edu ifetch_req->setThreadContext(cpu_id, /* thread ID */ 0); 4632662Sstever@eecs.umich.edu Fault fault = setupFetchRequest(ifetch_req); 4642623SN/A 4654022Sstever@eecs.umich.edu ifetch_pkt = new Packet(ifetch_req, MemCmd::ReadReq, Packet::Broadcast); 4662623SN/A ifetch_pkt->dataStatic(&inst); 4672623SN/A 4682623SN/A if (fault == NoFault) { 4692630SN/A if (!icachePort.sendTiming(ifetch_pkt)) { 4702623SN/A // Need to wait for retry 4712623SN/A _status = IcacheRetry; 4722623SN/A } else { 4732623SN/A // Need to wait for cache to respond 4742623SN/A _status = IcacheWaitResponse; 4752623SN/A // ownership of packet transferred to memory system 4762623SN/A ifetch_pkt = NULL; 4772623SN/A } 4782623SN/A } else { 4793658Sktlim@umich.edu delete ifetch_req; 4803658Sktlim@umich.edu delete ifetch_pkt; 4812644Sstever@eecs.umich.edu // fetch fault: advance directly to next instruction (fault handler) 4822644Sstever@eecs.umich.edu advanceInst(fault); 4832623SN/A } 4843222Sktlim@umich.edu 4853222Sktlim@umich.edu numCycles += curTick - previousTick; 4863222Sktlim@umich.edu previousTick = curTick; 4872623SN/A} 4882623SN/A 4892623SN/A 4902623SN/Avoid 4912644Sstever@eecs.umich.eduTimingSimpleCPU::advanceInst(Fault fault) 4922623SN/A{ 4932623SN/A advancePC(fault); 4942623SN/A 4952631SN/A if (_status == Running) { 4962631SN/A // kick off fetch of next instruction... callback from icache 4972631SN/A // response will cause that instruction to be executed, 4982631SN/A // keeping the CPU running. 4992631SN/A fetch(); 5002631SN/A } 5012623SN/A} 5022623SN/A 5032623SN/A 5042623SN/Avoid 5053349Sbinkertn@umich.eduTimingSimpleCPU::completeIfetch(PacketPtr pkt) 5062623SN/A{ 5072623SN/A // received a response from the icache: execute the received 5082623SN/A // instruction 5094870Sstever@eecs.umich.edu assert(!pkt->isError()); 5102623SN/A assert(_status == IcacheWaitResponse); 5112798Sktlim@umich.edu 5122623SN/A _status = Running; 5132644Sstever@eecs.umich.edu 5143222Sktlim@umich.edu numCycles += curTick - previousTick; 5153222Sktlim@umich.edu previousTick = curTick; 5163222Sktlim@umich.edu 5172839Sktlim@umich.edu if (getState() == SimObject::Draining) { 5183658Sktlim@umich.edu delete pkt->req; 5193658Sktlim@umich.edu delete pkt; 5203658Sktlim@umich.edu 5212839Sktlim@umich.edu completeDrain(); 5222798Sktlim@umich.edu return; 5232798Sktlim@umich.edu } 5242798Sktlim@umich.edu 5252623SN/A preExecute(); 5262644Sstever@eecs.umich.edu if (curStaticInst->isMemRef() && !curStaticInst->isDataPrefetch()) { 5272623SN/A // load or store: just send to dcache 5282623SN/A Fault fault = curStaticInst->initiateAcc(this, traceData); 5293170Sstever@eecs.umich.edu if (_status != Running) { 5303170Sstever@eecs.umich.edu // instruction will complete in dcache response callback 5313170Sstever@eecs.umich.edu assert(_status == DcacheWaitResponse || _status == DcacheRetry); 5323170Sstever@eecs.umich.edu assert(fault == NoFault); 5332644Sstever@eecs.umich.edu } else { 5343170Sstever@eecs.umich.edu if (fault == NoFault) { 5353170Sstever@eecs.umich.edu // early fail on store conditional: complete now 5363170Sstever@eecs.umich.edu assert(dcache_pkt != NULL); 5373170Sstever@eecs.umich.edu fault = curStaticInst->completeAcc(dcache_pkt, this, 5383170Sstever@eecs.umich.edu traceData); 5393170Sstever@eecs.umich.edu delete dcache_pkt->req; 5403170Sstever@eecs.umich.edu delete dcache_pkt; 5413170Sstever@eecs.umich.edu dcache_pkt = NULL; 5423170Sstever@eecs.umich.edu } 5432644Sstever@eecs.umich.edu postExecute(); 5442644Sstever@eecs.umich.edu advanceInst(fault); 5452644Sstever@eecs.umich.edu } 5462623SN/A } else { 5472623SN/A // non-memory instruction: execute completely now 5482623SN/A Fault fault = curStaticInst->execute(this, traceData); 5492644Sstever@eecs.umich.edu postExecute(); 5502644Sstever@eecs.umich.edu advanceInst(fault); 5512623SN/A } 5523658Sktlim@umich.edu 5533658Sktlim@umich.edu delete pkt->req; 5543658Sktlim@umich.edu delete pkt; 5552623SN/A} 5562623SN/A 5572948Ssaidi@eecs.umich.eduvoid 5582948Ssaidi@eecs.umich.eduTimingSimpleCPU::IcachePort::ITickEvent::process() 5592948Ssaidi@eecs.umich.edu{ 5602948Ssaidi@eecs.umich.edu cpu->completeIfetch(pkt); 5612948Ssaidi@eecs.umich.edu} 5622623SN/A 5632623SN/Abool 5643349Sbinkertn@umich.eduTimingSimpleCPU::IcachePort::recvTiming(PacketPtr pkt) 5652623SN/A{ 5663310Srdreslin@umich.edu if (pkt->isResponse()) { 5673310Srdreslin@umich.edu // delay processing of returned data until next CPU clock edge 5684584Ssaidi@eecs.umich.edu Tick next_tick = cpu->nextCycle(curTick); 5692948Ssaidi@eecs.umich.edu 5703495Sktlim@umich.edu if (next_tick == curTick) 5713310Srdreslin@umich.edu cpu->completeIfetch(pkt); 5723310Srdreslin@umich.edu else 5733495Sktlim@umich.edu tickEvent.schedule(pkt, next_tick); 5742948Ssaidi@eecs.umich.edu 5753310Srdreslin@umich.edu return true; 5763310Srdreslin@umich.edu } 5774870Sstever@eecs.umich.edu else if (pkt->wasNacked()) { 5784433Ssaidi@eecs.umich.edu assert(cpu->_status == IcacheWaitResponse); 5794433Ssaidi@eecs.umich.edu pkt->reinitNacked(); 5804433Ssaidi@eecs.umich.edu if (!sendTiming(pkt)) { 5814433Ssaidi@eecs.umich.edu cpu->_status = IcacheRetry; 5824433Ssaidi@eecs.umich.edu cpu->ifetch_pkt = pkt; 5834433Ssaidi@eecs.umich.edu } 5843310Srdreslin@umich.edu } 5854433Ssaidi@eecs.umich.edu //Snooping a Coherence Request, do nothing 5864433Ssaidi@eecs.umich.edu return true; 5872623SN/A} 5882623SN/A 5892657Ssaidi@eecs.umich.eduvoid 5902623SN/ATimingSimpleCPU::IcachePort::recvRetry() 5912623SN/A{ 5922623SN/A // we shouldn't get a retry unless we have a packet that we're 5932623SN/A // waiting to transmit 5942623SN/A assert(cpu->ifetch_pkt != NULL); 5952623SN/A assert(cpu->_status == IcacheRetry); 5963349Sbinkertn@umich.edu PacketPtr tmp = cpu->ifetch_pkt; 5972657Ssaidi@eecs.umich.edu if (sendTiming(tmp)) { 5982657Ssaidi@eecs.umich.edu cpu->_status = IcacheWaitResponse; 5992657Ssaidi@eecs.umich.edu cpu->ifetch_pkt = NULL; 6002657Ssaidi@eecs.umich.edu } 6012623SN/A} 6022623SN/A 6032623SN/Avoid 6043349Sbinkertn@umich.eduTimingSimpleCPU::completeDataAccess(PacketPtr pkt) 6052623SN/A{ 6062623SN/A // received a response from the dcache: complete the load or store 6072623SN/A // instruction 6084870Sstever@eecs.umich.edu assert(!pkt->isError()); 6092623SN/A assert(_status == DcacheWaitResponse); 6102623SN/A _status = Running; 6112623SN/A 6123222Sktlim@umich.edu numCycles += curTick - previousTick; 6133222Sktlim@umich.edu previousTick = curTick; 6143184Srdreslin@umich.edu 6152623SN/A Fault fault = curStaticInst->completeAcc(pkt, this, traceData); 6162623SN/A 6174878Sstever@eecs.umich.edu if (pkt->isRead() && pkt->isLocked()) { 6183170Sstever@eecs.umich.edu TheISA::handleLockedRead(thread, pkt->req); 6193170Sstever@eecs.umich.edu } 6203170Sstever@eecs.umich.edu 6212644Sstever@eecs.umich.edu delete pkt->req; 6222644Sstever@eecs.umich.edu delete pkt; 6232644Sstever@eecs.umich.edu 6243184Srdreslin@umich.edu postExecute(); 6253227Sktlim@umich.edu 6263201Shsul@eecs.umich.edu if (getState() == SimObject::Draining) { 6273201Shsul@eecs.umich.edu advancePC(fault); 6283201Shsul@eecs.umich.edu completeDrain(); 6293201Shsul@eecs.umich.edu 6303201Shsul@eecs.umich.edu return; 6313201Shsul@eecs.umich.edu } 6323201Shsul@eecs.umich.edu 6332644Sstever@eecs.umich.edu advanceInst(fault); 6342623SN/A} 6352623SN/A 6362623SN/A 6372798Sktlim@umich.eduvoid 6382839Sktlim@umich.eduTimingSimpleCPU::completeDrain() 6392798Sktlim@umich.edu{ 6402839Sktlim@umich.edu DPRINTF(Config, "Done draining\n"); 6412901Ssaidi@eecs.umich.edu changeState(SimObject::Drained); 6422839Sktlim@umich.edu drainEvent->process(); 6432798Sktlim@umich.edu} 6442623SN/A 6454192Sktlim@umich.eduvoid 6464192Sktlim@umich.eduTimingSimpleCPU::DcachePort::setPeer(Port *port) 6474192Sktlim@umich.edu{ 6484192Sktlim@umich.edu Port::setPeer(port); 6494192Sktlim@umich.edu 6504192Sktlim@umich.edu#if FULL_SYSTEM 6514192Sktlim@umich.edu // Update the ThreadContext's memory ports (Functional/Virtual 6524192Sktlim@umich.edu // Ports) 6534192Sktlim@umich.edu cpu->tcBase()->connectMemPorts(); 6544192Sktlim@umich.edu#endif 6554192Sktlim@umich.edu} 6564192Sktlim@umich.edu 6572623SN/Abool 6583349Sbinkertn@umich.eduTimingSimpleCPU::DcachePort::recvTiming(PacketPtr pkt) 6592623SN/A{ 6603310Srdreslin@umich.edu if (pkt->isResponse()) { 6613310Srdreslin@umich.edu // delay processing of returned data until next CPU clock edge 6624584Ssaidi@eecs.umich.edu Tick next_tick = cpu->nextCycle(curTick); 6632948Ssaidi@eecs.umich.edu 6643495Sktlim@umich.edu if (next_tick == curTick) 6653310Srdreslin@umich.edu cpu->completeDataAccess(pkt); 6663310Srdreslin@umich.edu else 6673495Sktlim@umich.edu tickEvent.schedule(pkt, next_tick); 6682948Ssaidi@eecs.umich.edu 6693310Srdreslin@umich.edu return true; 6703310Srdreslin@umich.edu } 6714870Sstever@eecs.umich.edu else if (pkt->wasNacked()) { 6724433Ssaidi@eecs.umich.edu assert(cpu->_status == DcacheWaitResponse); 6734433Ssaidi@eecs.umich.edu pkt->reinitNacked(); 6744433Ssaidi@eecs.umich.edu if (!sendTiming(pkt)) { 6754433Ssaidi@eecs.umich.edu cpu->_status = DcacheRetry; 6764433Ssaidi@eecs.umich.edu cpu->dcache_pkt = pkt; 6774433Ssaidi@eecs.umich.edu } 6783310Srdreslin@umich.edu } 6794433Ssaidi@eecs.umich.edu //Snooping a Coherence Request, do nothing 6804433Ssaidi@eecs.umich.edu return true; 6812948Ssaidi@eecs.umich.edu} 6822948Ssaidi@eecs.umich.edu 6832948Ssaidi@eecs.umich.eduvoid 6842948Ssaidi@eecs.umich.eduTimingSimpleCPU::DcachePort::DTickEvent::process() 6852948Ssaidi@eecs.umich.edu{ 6862630SN/A cpu->completeDataAccess(pkt); 6872623SN/A} 6882623SN/A 6892657Ssaidi@eecs.umich.eduvoid 6902623SN/ATimingSimpleCPU::DcachePort::recvRetry() 6912623SN/A{ 6922623SN/A // we shouldn't get a retry unless we have a packet that we're 6932623SN/A // waiting to transmit 6942623SN/A assert(cpu->dcache_pkt != NULL); 6952623SN/A assert(cpu->_status == DcacheRetry); 6963349Sbinkertn@umich.edu PacketPtr tmp = cpu->dcache_pkt; 6972657Ssaidi@eecs.umich.edu if (sendTiming(tmp)) { 6982657Ssaidi@eecs.umich.edu cpu->_status = DcacheWaitResponse; 6993170Sstever@eecs.umich.edu // memory system takes ownership of packet 7002657Ssaidi@eecs.umich.edu cpu->dcache_pkt = NULL; 7012657Ssaidi@eecs.umich.edu } 7022623SN/A} 7032623SN/A 7042623SN/A 7052623SN/A//////////////////////////////////////////////////////////////////////// 7062623SN/A// 7072623SN/A// TimingSimpleCPU Simulation Object 7082623SN/A// 7092623SN/ABEGIN_DECLARE_SIM_OBJECT_PARAMS(TimingSimpleCPU) 7102623SN/A 7112623SN/A Param<Counter> max_insts_any_thread; 7122623SN/A Param<Counter> max_insts_all_threads; 7132623SN/A Param<Counter> max_loads_any_thread; 7142623SN/A Param<Counter> max_loads_all_threads; 7153119Sktlim@umich.edu Param<Tick> progress_interval; 7162901Ssaidi@eecs.umich.edu SimObjectParam<System *> system; 7173170Sstever@eecs.umich.edu Param<int> cpu_id; 7182623SN/A 7192623SN/A#if FULL_SYSTEM 7203453Sgblack@eecs.umich.edu SimObjectParam<TheISA::ITB *> itb; 7213453Sgblack@eecs.umich.edu SimObjectParam<TheISA::DTB *> dtb; 7222623SN/A Param<Tick> profile; 7233617Sbinkertn@umich.edu 7243617Sbinkertn@umich.edu Param<bool> do_quiesce; 7253617Sbinkertn@umich.edu Param<bool> do_checkpoint_insts; 7263617Sbinkertn@umich.edu Param<bool> do_statistics_insts; 7272623SN/A#else 7282623SN/A SimObjectParam<Process *> workload; 7292623SN/A#endif // FULL_SYSTEM 7302623SN/A 7312623SN/A Param<int> clock; 7323661Srdreslin@umich.edu Param<int> phase; 7332623SN/A 7342623SN/A Param<bool> defer_registration; 7352623SN/A Param<int> width; 7362623SN/A Param<bool> function_trace; 7372623SN/A Param<Tick> function_trace_start; 7382623SN/A Param<bool> simulate_stalls; 7392623SN/A 7402623SN/AEND_DECLARE_SIM_OBJECT_PARAMS(TimingSimpleCPU) 7412623SN/A 7422623SN/ABEGIN_INIT_SIM_OBJECT_PARAMS(TimingSimpleCPU) 7432623SN/A 7442623SN/A INIT_PARAM(max_insts_any_thread, 7452623SN/A "terminate when any thread reaches this inst count"), 7462623SN/A INIT_PARAM(max_insts_all_threads, 7472623SN/A "terminate when all threads have reached this inst count"), 7482623SN/A INIT_PARAM(max_loads_any_thread, 7492623SN/A "terminate when any thread reaches this load count"), 7502623SN/A INIT_PARAM(max_loads_all_threads, 7512623SN/A "terminate when all threads have reached this load count"), 7523119Sktlim@umich.edu INIT_PARAM(progress_interval, "Progress interval"), 7532901Ssaidi@eecs.umich.edu INIT_PARAM(system, "system object"), 7543170Sstever@eecs.umich.edu INIT_PARAM(cpu_id, "processor ID"), 7552623SN/A 7562623SN/A#if FULL_SYSTEM 7572623SN/A INIT_PARAM(itb, "Instruction TLB"), 7582623SN/A INIT_PARAM(dtb, "Data TLB"), 7592623SN/A INIT_PARAM(profile, ""), 7603617Sbinkertn@umich.edu INIT_PARAM(do_quiesce, ""), 7613617Sbinkertn@umich.edu INIT_PARAM(do_checkpoint_insts, ""), 7623617Sbinkertn@umich.edu INIT_PARAM(do_statistics_insts, ""), 7632623SN/A#else 7642623SN/A INIT_PARAM(workload, "processes to run"), 7652623SN/A#endif // FULL_SYSTEM 7662623SN/A 7672623SN/A INIT_PARAM(clock, "clock speed"), 7683661Srdreslin@umich.edu INIT_PARAM_DFLT(phase, "clock phase", 0), 7692623SN/A INIT_PARAM(defer_registration, "defer system registration (for sampling)"), 7702623SN/A INIT_PARAM(width, "cpu width"), 7712623SN/A INIT_PARAM(function_trace, "Enable function trace"), 7722623SN/A INIT_PARAM(function_trace_start, "Cycle to start function trace"), 7732623SN/A INIT_PARAM(simulate_stalls, "Simulate cache stall cycles") 7742623SN/A 7752623SN/AEND_INIT_SIM_OBJECT_PARAMS(TimingSimpleCPU) 7762623SN/A 7772623SN/A 7782623SN/ACREATE_SIM_OBJECT(TimingSimpleCPU) 7792623SN/A{ 7802623SN/A TimingSimpleCPU::Params *params = new TimingSimpleCPU::Params(); 7812623SN/A params->name = getInstanceName(); 7822623SN/A params->numberOfThreads = 1; 7832623SN/A params->max_insts_any_thread = max_insts_any_thread; 7842623SN/A params->max_insts_all_threads = max_insts_all_threads; 7852623SN/A params->max_loads_any_thread = max_loads_any_thread; 7862623SN/A params->max_loads_all_threads = max_loads_all_threads; 7873119Sktlim@umich.edu params->progress_interval = progress_interval; 7882623SN/A params->deferRegistration = defer_registration; 7892623SN/A params->clock = clock; 7903661Srdreslin@umich.edu params->phase = phase; 7912623SN/A params->functionTrace = function_trace; 7922623SN/A params->functionTraceStart = function_trace_start; 7932901Ssaidi@eecs.umich.edu params->system = system; 7943170Sstever@eecs.umich.edu params->cpu_id = cpu_id; 7952623SN/A 7962623SN/A#if FULL_SYSTEM 7972623SN/A params->itb = itb; 7982623SN/A params->dtb = dtb; 7992623SN/A params->profile = profile; 8003617Sbinkertn@umich.edu params->do_quiesce = do_quiesce; 8013617Sbinkertn@umich.edu params->do_checkpoint_insts = do_checkpoint_insts; 8023617Sbinkertn@umich.edu params->do_statistics_insts = do_statistics_insts; 8032623SN/A#else 8042623SN/A params->process = workload; 8052623SN/A#endif 8062623SN/A 8072623SN/A TimingSimpleCPU *cpu = new TimingSimpleCPU(params); 8082623SN/A return cpu; 8092623SN/A} 8102623SN/A 8112623SN/AREGISTER_SIM_OBJECT("TimingSimpleCPU", TimingSimpleCPU) 8122623SN/A 813