timing.cc revision 3686
12623SN/A/* 22623SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 32623SN/A * All rights reserved. 42623SN/A * 52623SN/A * Redistribution and use in source and binary forms, with or without 62623SN/A * modification, are permitted provided that the following conditions are 72623SN/A * met: redistributions of source code must retain the above copyright 82623SN/A * notice, this list of conditions and the following disclaimer; 92623SN/A * redistributions in binary form must reproduce the above copyright 102623SN/A * notice, this list of conditions and the following disclaimer in the 112623SN/A * documentation and/or other materials provided with the distribution; 122623SN/A * neither the name of the copyright holders nor the names of its 132623SN/A * contributors may be used to endorse or promote products derived from 142623SN/A * this software without specific prior written permission. 152623SN/A * 162623SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172623SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182623SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192623SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202623SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212623SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222623SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232623SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242623SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252623SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262623SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 292623SN/A */ 302623SN/A 313170Sstever@eecs.umich.edu#include "arch/locked_mem.hh" 322623SN/A#include "arch/utility.hh" 332623SN/A#include "cpu/exetrace.hh" 342623SN/A#include "cpu/simple/timing.hh" 353348Sbinkertn@umich.edu#include "mem/packet.hh" 363348Sbinkertn@umich.edu#include "mem/packet_access.hh" 372623SN/A#include "sim/builder.hh" 382901Ssaidi@eecs.umich.edu#include "sim/system.hh" 392623SN/A 402623SN/Ausing namespace std; 412623SN/Ausing namespace TheISA; 422623SN/A 432856Srdreslin@umich.eduPort * 442856Srdreslin@umich.eduTimingSimpleCPU::getPort(const std::string &if_name, int idx) 452856Srdreslin@umich.edu{ 462856Srdreslin@umich.edu if (if_name == "dcache_port") 472856Srdreslin@umich.edu return &dcachePort; 482856Srdreslin@umich.edu else if (if_name == "icache_port") 492856Srdreslin@umich.edu return &icachePort; 502856Srdreslin@umich.edu else 512856Srdreslin@umich.edu panic("No Such Port\n"); 522856Srdreslin@umich.edu} 532623SN/A 542623SN/Avoid 552623SN/ATimingSimpleCPU::init() 562623SN/A{ 572623SN/A BaseCPU::init(); 582623SN/A#if FULL_SYSTEM 592680Sktlim@umich.edu for (int i = 0; i < threadContexts.size(); ++i) { 602680Sktlim@umich.edu ThreadContext *tc = threadContexts[i]; 612623SN/A 622623SN/A // initialize CPU, including PC 632680Sktlim@umich.edu TheISA::initCPU(tc, tc->readCpuId()); 642623SN/A } 652623SN/A#endif 662623SN/A} 672623SN/A 682623SN/ATick 693349Sbinkertn@umich.eduTimingSimpleCPU::CpuPort::recvAtomic(PacketPtr pkt) 702623SN/A{ 712623SN/A panic("TimingSimpleCPU doesn't expect recvAtomic callback!"); 722623SN/A return curTick; 732623SN/A} 742623SN/A 752623SN/Avoid 763349Sbinkertn@umich.eduTimingSimpleCPU::CpuPort::recvFunctional(PacketPtr pkt) 772623SN/A{ 783184Srdreslin@umich.edu //No internal storage to update, jusst return 793184Srdreslin@umich.edu return; 802623SN/A} 812623SN/A 822623SN/Avoid 832623SN/ATimingSimpleCPU::CpuPort::recvStatusChange(Status status) 842623SN/A{ 853647Srdreslin@umich.edu if (status == RangeChange) { 863647Srdreslin@umich.edu if (!snoopRangeSent) { 873647Srdreslin@umich.edu snoopRangeSent = true; 883647Srdreslin@umich.edu sendStatusChange(Port::RangeChange); 893647Srdreslin@umich.edu } 902631SN/A return; 913647Srdreslin@umich.edu } 922631SN/A 932623SN/A panic("TimingSimpleCPU doesn't expect recvStatusChange callback!"); 942623SN/A} 952623SN/A 962948Ssaidi@eecs.umich.edu 972948Ssaidi@eecs.umich.eduvoid 983349Sbinkertn@umich.eduTimingSimpleCPU::CpuPort::TickEvent::schedule(PacketPtr _pkt, Tick t) 992948Ssaidi@eecs.umich.edu{ 1002948Ssaidi@eecs.umich.edu pkt = _pkt; 1012948Ssaidi@eecs.umich.edu Event::schedule(t); 1022948Ssaidi@eecs.umich.edu} 1032948Ssaidi@eecs.umich.edu 1042623SN/ATimingSimpleCPU::TimingSimpleCPU(Params *p) 1053170Sstever@eecs.umich.edu : BaseSimpleCPU(p), icachePort(this, p->clock), dcachePort(this, p->clock), 1063170Sstever@eecs.umich.edu cpu_id(p->cpu_id) 1072623SN/A{ 1082623SN/A _status = Idle; 1093647Srdreslin@umich.edu 1103647Srdreslin@umich.edu icachePort.snoopRangeSent = false; 1113647Srdreslin@umich.edu dcachePort.snoopRangeSent = false; 1123647Srdreslin@umich.edu 1132623SN/A ifetch_pkt = dcache_pkt = NULL; 1142839Sktlim@umich.edu drainEvent = NULL; 1152867Sktlim@umich.edu fetchEvent = NULL; 1163222Sktlim@umich.edu previousTick = 0; 1172901Ssaidi@eecs.umich.edu changeState(SimObject::Running); 1182623SN/A} 1192623SN/A 1202623SN/A 1212623SN/ATimingSimpleCPU::~TimingSimpleCPU() 1222623SN/A{ 1232623SN/A} 1242623SN/A 1252623SN/Avoid 1262623SN/ATimingSimpleCPU::serialize(ostream &os) 1272623SN/A{ 1282915Sktlim@umich.edu SimObject::State so_state = SimObject::getState(); 1292915Sktlim@umich.edu SERIALIZE_ENUM(so_state); 1302623SN/A BaseSimpleCPU::serialize(os); 1312623SN/A} 1322623SN/A 1332623SN/Avoid 1342623SN/ATimingSimpleCPU::unserialize(Checkpoint *cp, const string §ion) 1352623SN/A{ 1362915Sktlim@umich.edu SimObject::State so_state; 1372915Sktlim@umich.edu UNSERIALIZE_ENUM(so_state); 1382623SN/A BaseSimpleCPU::unserialize(cp, section); 1392798Sktlim@umich.edu} 1402798Sktlim@umich.edu 1412901Ssaidi@eecs.umich.eduunsigned int 1422839Sktlim@umich.eduTimingSimpleCPU::drain(Event *drain_event) 1432798Sktlim@umich.edu{ 1442839Sktlim@umich.edu // TimingSimpleCPU is ready to drain if it's not waiting for 1452798Sktlim@umich.edu // an access to complete. 1462798Sktlim@umich.edu if (status() == Idle || status() == Running || status() == SwitchedOut) { 1472901Ssaidi@eecs.umich.edu changeState(SimObject::Drained); 1482901Ssaidi@eecs.umich.edu return 0; 1492798Sktlim@umich.edu } else { 1502839Sktlim@umich.edu changeState(SimObject::Draining); 1512839Sktlim@umich.edu drainEvent = drain_event; 1522901Ssaidi@eecs.umich.edu return 1; 1532798Sktlim@umich.edu } 1542623SN/A} 1552623SN/A 1562623SN/Avoid 1572798Sktlim@umich.eduTimingSimpleCPU::resume() 1582623SN/A{ 1592798Sktlim@umich.edu if (_status != SwitchedOut && _status != Idle) { 1603201Shsul@eecs.umich.edu assert(system->getMemoryMode() == System::Timing); 1613201Shsul@eecs.umich.edu 1622867Sktlim@umich.edu // Delete the old event if it existed. 1632867Sktlim@umich.edu if (fetchEvent) { 1642915Sktlim@umich.edu if (fetchEvent->scheduled()) 1652915Sktlim@umich.edu fetchEvent->deschedule(); 1662915Sktlim@umich.edu 1672867Sktlim@umich.edu delete fetchEvent; 1682867Sktlim@umich.edu } 1692867Sktlim@umich.edu 1702867Sktlim@umich.edu fetchEvent = 1712867Sktlim@umich.edu new EventWrapper<TimingSimpleCPU, &TimingSimpleCPU::fetch>(this, false); 1723661Srdreslin@umich.edu fetchEvent->schedule(nextCycle()); 1732623SN/A } 1742798Sktlim@umich.edu 1752901Ssaidi@eecs.umich.edu changeState(SimObject::Running); 1763222Sktlim@umich.edu previousTick = curTick; 1772798Sktlim@umich.edu} 1782798Sktlim@umich.edu 1792798Sktlim@umich.eduvoid 1802798Sktlim@umich.eduTimingSimpleCPU::switchOut() 1812798Sktlim@umich.edu{ 1822798Sktlim@umich.edu assert(status() == Running || status() == Idle); 1832798Sktlim@umich.edu _status = SwitchedOut; 1843222Sktlim@umich.edu numCycles += curTick - previousTick; 1852867Sktlim@umich.edu 1862867Sktlim@umich.edu // If we've been scheduled to resume but are then told to switch out, 1872867Sktlim@umich.edu // we'll need to cancel it. 1882867Sktlim@umich.edu if (fetchEvent && fetchEvent->scheduled()) 1892867Sktlim@umich.edu fetchEvent->deschedule(); 1902623SN/A} 1912623SN/A 1922623SN/A 1932623SN/Avoid 1942623SN/ATimingSimpleCPU::takeOverFrom(BaseCPU *oldCPU) 1952623SN/A{ 1962623SN/A BaseCPU::takeOverFrom(oldCPU); 1972623SN/A 1982680Sktlim@umich.edu // if any of this CPU's ThreadContexts are active, mark the CPU as 1992623SN/A // running and schedule its tick event. 2002680Sktlim@umich.edu for (int i = 0; i < threadContexts.size(); ++i) { 2012680Sktlim@umich.edu ThreadContext *tc = threadContexts[i]; 2022680Sktlim@umich.edu if (tc->status() == ThreadContext::Active && _status != Running) { 2032623SN/A _status = Running; 2042623SN/A break; 2052623SN/A } 2062623SN/A } 2073201Shsul@eecs.umich.edu 2083201Shsul@eecs.umich.edu if (_status != Running) { 2093201Shsul@eecs.umich.edu _status = Idle; 2103201Shsul@eecs.umich.edu } 2113227Sktlim@umich.edu 2123222Sktlim@umich.edu Port *peer; 2133222Sktlim@umich.edu if (icachePort.getPeer() == NULL) { 2143227Sktlim@umich.edu peer = oldCPU->getPort("icache_port")->getPeer(); 2153222Sktlim@umich.edu icachePort.setPeer(peer); 2163222Sktlim@umich.edu } else { 2173222Sktlim@umich.edu peer = icachePort.getPeer(); 2183222Sktlim@umich.edu } 2193222Sktlim@umich.edu peer->setPeer(&icachePort); 2203222Sktlim@umich.edu 2213222Sktlim@umich.edu if (dcachePort.getPeer() == NULL) { 2223227Sktlim@umich.edu peer = oldCPU->getPort("dcache_port")->getPeer(); 2233222Sktlim@umich.edu dcachePort.setPeer(peer); 2243222Sktlim@umich.edu } else { 2253222Sktlim@umich.edu peer = dcachePort.getPeer(); 2263222Sktlim@umich.edu } 2273222Sktlim@umich.edu peer->setPeer(&dcachePort); 2282623SN/A} 2292623SN/A 2302623SN/A 2312623SN/Avoid 2322623SN/ATimingSimpleCPU::activateContext(int thread_num, int delay) 2332623SN/A{ 2342623SN/A assert(thread_num == 0); 2352683Sktlim@umich.edu assert(thread); 2362623SN/A 2372623SN/A assert(_status == Idle); 2382623SN/A 2392623SN/A notIdleFraction++; 2402623SN/A _status = Running; 2413686Sktlim@umich.edu 2423686Sktlim@umich.edu#if FULL_SYSTEM 2433686Sktlim@umich.edu // Connect the ThreadContext's memory ports (Functional/Virtual 2443686Sktlim@umich.edu // Ports) 2453686Sktlim@umich.edu tc->connectMemPorts(); 2463686Sktlim@umich.edu#endif 2473686Sktlim@umich.edu 2482623SN/A // kick things off by initiating the fetch of the next instruction 2492867Sktlim@umich.edu fetchEvent = 2502867Sktlim@umich.edu new EventWrapper<TimingSimpleCPU, &TimingSimpleCPU::fetch>(this, false); 2513661Srdreslin@umich.edu fetchEvent->schedule(nextCycle(curTick + cycles(delay))); 2522623SN/A} 2532623SN/A 2542623SN/A 2552623SN/Avoid 2562623SN/ATimingSimpleCPU::suspendContext(int thread_num) 2572623SN/A{ 2582623SN/A assert(thread_num == 0); 2592683Sktlim@umich.edu assert(thread); 2602623SN/A 2612644Sstever@eecs.umich.edu assert(_status == Running); 2622623SN/A 2632644Sstever@eecs.umich.edu // just change status to Idle... if status != Running, 2642644Sstever@eecs.umich.edu // completeInst() will not initiate fetch of next instruction. 2652623SN/A 2662623SN/A notIdleFraction--; 2672623SN/A _status = Idle; 2682623SN/A} 2692623SN/A 2702623SN/A 2712623SN/Atemplate <class T> 2722623SN/AFault 2732623SN/ATimingSimpleCPU::read(Addr addr, T &data, unsigned flags) 2742623SN/A{ 2753169Sstever@eecs.umich.edu Request *req = 2763169Sstever@eecs.umich.edu new Request(/* asid */ 0, addr, sizeof(T), flags, thread->readPC(), 2773170Sstever@eecs.umich.edu cpu_id, /* thread ID */ 0); 2782623SN/A 2792623SN/A if (traceData) { 2803169Sstever@eecs.umich.edu traceData->setAddr(req->getVaddr()); 2812623SN/A } 2822623SN/A 2832623SN/A // translate to physical address 2843169Sstever@eecs.umich.edu Fault fault = thread->translateDataReadReq(req); 2852623SN/A 2862623SN/A // Now do the access. 2872623SN/A if (fault == NoFault) { 2883349Sbinkertn@umich.edu PacketPtr pkt = 2893169Sstever@eecs.umich.edu new Packet(req, Packet::ReadReq, Packet::Broadcast); 2903169Sstever@eecs.umich.edu pkt->dataDynamic<T>(new T); 2912623SN/A 2923169Sstever@eecs.umich.edu if (!dcachePort.sendTiming(pkt)) { 2932623SN/A _status = DcacheRetry; 2943169Sstever@eecs.umich.edu dcache_pkt = pkt; 2952623SN/A } else { 2962623SN/A _status = DcacheWaitResponse; 2973169Sstever@eecs.umich.edu // memory system takes ownership of packet 2982623SN/A dcache_pkt = NULL; 2992623SN/A } 3003658Sktlim@umich.edu } else { 3013658Sktlim@umich.edu delete req; 3022623SN/A } 3032623SN/A 3042623SN/A // This will need a new way to tell if it has a dcache attached. 3053172Sstever@eecs.umich.edu if (req->isUncacheable()) 3062623SN/A recordEvent("Uncached Read"); 3072623SN/A 3082623SN/A return fault; 3092623SN/A} 3102623SN/A 3112623SN/A#ifndef DOXYGEN_SHOULD_SKIP_THIS 3122623SN/A 3132623SN/Atemplate 3142623SN/AFault 3152623SN/ATimingSimpleCPU::read(Addr addr, uint64_t &data, unsigned flags); 3162623SN/A 3172623SN/Atemplate 3182623SN/AFault 3192623SN/ATimingSimpleCPU::read(Addr addr, uint32_t &data, unsigned flags); 3202623SN/A 3212623SN/Atemplate 3222623SN/AFault 3232623SN/ATimingSimpleCPU::read(Addr addr, uint16_t &data, unsigned flags); 3242623SN/A 3252623SN/Atemplate 3262623SN/AFault 3272623SN/ATimingSimpleCPU::read(Addr addr, uint8_t &data, unsigned flags); 3282623SN/A 3292623SN/A#endif //DOXYGEN_SHOULD_SKIP_THIS 3302623SN/A 3312623SN/Atemplate<> 3322623SN/AFault 3332623SN/ATimingSimpleCPU::read(Addr addr, double &data, unsigned flags) 3342623SN/A{ 3352623SN/A return read(addr, *(uint64_t*)&data, flags); 3362623SN/A} 3372623SN/A 3382623SN/Atemplate<> 3392623SN/AFault 3402623SN/ATimingSimpleCPU::read(Addr addr, float &data, unsigned flags) 3412623SN/A{ 3422623SN/A return read(addr, *(uint32_t*)&data, flags); 3432623SN/A} 3442623SN/A 3452623SN/A 3462623SN/Atemplate<> 3472623SN/AFault 3482623SN/ATimingSimpleCPU::read(Addr addr, int32_t &data, unsigned flags) 3492623SN/A{ 3502623SN/A return read(addr, (uint32_t&)data, flags); 3512623SN/A} 3522623SN/A 3532623SN/A 3542623SN/Atemplate <class T> 3552623SN/AFault 3562623SN/ATimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res) 3572623SN/A{ 3583169Sstever@eecs.umich.edu Request *req = 3593169Sstever@eecs.umich.edu new Request(/* asid */ 0, addr, sizeof(T), flags, thread->readPC(), 3603170Sstever@eecs.umich.edu cpu_id, /* thread ID */ 0); 3612623SN/A 3622623SN/A // translate to physical address 3633169Sstever@eecs.umich.edu Fault fault = thread->translateDataWriteReq(req); 3643169Sstever@eecs.umich.edu 3652623SN/A // Now do the access. 3662623SN/A if (fault == NoFault) { 3673169Sstever@eecs.umich.edu assert(dcache_pkt == NULL); 3683169Sstever@eecs.umich.edu dcache_pkt = new Packet(req, Packet::WriteReq, Packet::Broadcast); 3693169Sstever@eecs.umich.edu dcache_pkt->allocate(); 3703169Sstever@eecs.umich.edu dcache_pkt->set(data); 3712623SN/A 3723170Sstever@eecs.umich.edu bool do_access = true; // flag to suppress cache access 3733170Sstever@eecs.umich.edu 3743170Sstever@eecs.umich.edu if (req->isLocked()) { 3753170Sstever@eecs.umich.edu do_access = TheISA::handleLockedWrite(thread, req); 3763170Sstever@eecs.umich.edu } 3773170Sstever@eecs.umich.edu 3783170Sstever@eecs.umich.edu if (do_access) { 3793170Sstever@eecs.umich.edu if (!dcachePort.sendTiming(dcache_pkt)) { 3803170Sstever@eecs.umich.edu _status = DcacheRetry; 3813170Sstever@eecs.umich.edu } else { 3823170Sstever@eecs.umich.edu _status = DcacheWaitResponse; 3833170Sstever@eecs.umich.edu // memory system takes ownership of packet 3843170Sstever@eecs.umich.edu dcache_pkt = NULL; 3853170Sstever@eecs.umich.edu } 3862623SN/A } 3873658Sktlim@umich.edu } else { 3883658Sktlim@umich.edu delete req; 3892623SN/A } 3902623SN/A 3912623SN/A // This will need a new way to tell if it's hooked up to a cache or not. 3923172Sstever@eecs.umich.edu if (req->isUncacheable()) 3932623SN/A recordEvent("Uncached Write"); 3942623SN/A 3952623SN/A // If the write needs to have a fault on the access, consider calling 3962623SN/A // changeStatus() and changing it to "bad addr write" or something. 3972623SN/A return fault; 3982623SN/A} 3992623SN/A 4002623SN/A 4012623SN/A#ifndef DOXYGEN_SHOULD_SKIP_THIS 4022623SN/Atemplate 4032623SN/AFault 4042623SN/ATimingSimpleCPU::write(uint64_t data, Addr addr, 4052623SN/A unsigned flags, uint64_t *res); 4062623SN/A 4072623SN/Atemplate 4082623SN/AFault 4092623SN/ATimingSimpleCPU::write(uint32_t data, Addr addr, 4102623SN/A unsigned flags, uint64_t *res); 4112623SN/A 4122623SN/Atemplate 4132623SN/AFault 4142623SN/ATimingSimpleCPU::write(uint16_t data, Addr addr, 4152623SN/A unsigned flags, uint64_t *res); 4162623SN/A 4172623SN/Atemplate 4182623SN/AFault 4192623SN/ATimingSimpleCPU::write(uint8_t data, Addr addr, 4202623SN/A unsigned flags, uint64_t *res); 4212623SN/A 4222623SN/A#endif //DOXYGEN_SHOULD_SKIP_THIS 4232623SN/A 4242623SN/Atemplate<> 4252623SN/AFault 4262623SN/ATimingSimpleCPU::write(double data, Addr addr, unsigned flags, uint64_t *res) 4272623SN/A{ 4282623SN/A return write(*(uint64_t*)&data, addr, flags, res); 4292623SN/A} 4302623SN/A 4312623SN/Atemplate<> 4322623SN/AFault 4332623SN/ATimingSimpleCPU::write(float data, Addr addr, unsigned flags, uint64_t *res) 4342623SN/A{ 4352623SN/A return write(*(uint32_t*)&data, addr, flags, res); 4362623SN/A} 4372623SN/A 4382623SN/A 4392623SN/Atemplate<> 4402623SN/AFault 4412623SN/ATimingSimpleCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res) 4422623SN/A{ 4432623SN/A return write((uint32_t)data, addr, flags, res); 4442623SN/A} 4452623SN/A 4462623SN/A 4472623SN/Avoid 4482623SN/ATimingSimpleCPU::fetch() 4492623SN/A{ 4503387Sgblack@eecs.umich.edu if (!curStaticInst || !curStaticInst->isDelayedCommit()) 4513387Sgblack@eecs.umich.edu checkForInterrupts(); 4522631SN/A 4532663Sstever@eecs.umich.edu Request *ifetch_req = new Request(); 4543170Sstever@eecs.umich.edu ifetch_req->setThreadContext(cpu_id, /* thread ID */ 0); 4552662Sstever@eecs.umich.edu Fault fault = setupFetchRequest(ifetch_req); 4562623SN/A 4572641Sstever@eecs.umich.edu ifetch_pkt = new Packet(ifetch_req, Packet::ReadReq, Packet::Broadcast); 4582623SN/A ifetch_pkt->dataStatic(&inst); 4592623SN/A 4602623SN/A if (fault == NoFault) { 4612630SN/A if (!icachePort.sendTiming(ifetch_pkt)) { 4622623SN/A // Need to wait for retry 4632623SN/A _status = IcacheRetry; 4642623SN/A } else { 4652623SN/A // Need to wait for cache to respond 4662623SN/A _status = IcacheWaitResponse; 4672623SN/A // ownership of packet transferred to memory system 4682623SN/A ifetch_pkt = NULL; 4692623SN/A } 4702623SN/A } else { 4713658Sktlim@umich.edu delete ifetch_req; 4723658Sktlim@umich.edu delete ifetch_pkt; 4732644Sstever@eecs.umich.edu // fetch fault: advance directly to next instruction (fault handler) 4742644Sstever@eecs.umich.edu advanceInst(fault); 4752623SN/A } 4763222Sktlim@umich.edu 4773222Sktlim@umich.edu numCycles += curTick - previousTick; 4783222Sktlim@umich.edu previousTick = curTick; 4792623SN/A} 4802623SN/A 4812623SN/A 4822623SN/Avoid 4832644Sstever@eecs.umich.eduTimingSimpleCPU::advanceInst(Fault fault) 4842623SN/A{ 4852623SN/A advancePC(fault); 4862623SN/A 4872631SN/A if (_status == Running) { 4882631SN/A // kick off fetch of next instruction... callback from icache 4892631SN/A // response will cause that instruction to be executed, 4902631SN/A // keeping the CPU running. 4912631SN/A fetch(); 4922631SN/A } 4932623SN/A} 4942623SN/A 4952623SN/A 4962623SN/Avoid 4973349Sbinkertn@umich.eduTimingSimpleCPU::completeIfetch(PacketPtr pkt) 4982623SN/A{ 4992623SN/A // received a response from the icache: execute the received 5002623SN/A // instruction 5012644Sstever@eecs.umich.edu assert(pkt->result == Packet::Success); 5022623SN/A assert(_status == IcacheWaitResponse); 5032798Sktlim@umich.edu 5042623SN/A _status = Running; 5052644Sstever@eecs.umich.edu 5063222Sktlim@umich.edu numCycles += curTick - previousTick; 5073222Sktlim@umich.edu previousTick = curTick; 5083222Sktlim@umich.edu 5092839Sktlim@umich.edu if (getState() == SimObject::Draining) { 5103658Sktlim@umich.edu delete pkt->req; 5113658Sktlim@umich.edu delete pkt; 5123658Sktlim@umich.edu 5132839Sktlim@umich.edu completeDrain(); 5142798Sktlim@umich.edu return; 5152798Sktlim@umich.edu } 5162798Sktlim@umich.edu 5172623SN/A preExecute(); 5182644Sstever@eecs.umich.edu if (curStaticInst->isMemRef() && !curStaticInst->isDataPrefetch()) { 5192623SN/A // load or store: just send to dcache 5202623SN/A Fault fault = curStaticInst->initiateAcc(this, traceData); 5213170Sstever@eecs.umich.edu if (_status != Running) { 5223170Sstever@eecs.umich.edu // instruction will complete in dcache response callback 5233170Sstever@eecs.umich.edu assert(_status == DcacheWaitResponse || _status == DcacheRetry); 5243170Sstever@eecs.umich.edu assert(fault == NoFault); 5252644Sstever@eecs.umich.edu } else { 5263170Sstever@eecs.umich.edu if (fault == NoFault) { 5273170Sstever@eecs.umich.edu // early fail on store conditional: complete now 5283170Sstever@eecs.umich.edu assert(dcache_pkt != NULL); 5293170Sstever@eecs.umich.edu fault = curStaticInst->completeAcc(dcache_pkt, this, 5303170Sstever@eecs.umich.edu traceData); 5313170Sstever@eecs.umich.edu delete dcache_pkt->req; 5323170Sstever@eecs.umich.edu delete dcache_pkt; 5333170Sstever@eecs.umich.edu dcache_pkt = NULL; 5343170Sstever@eecs.umich.edu } 5352644Sstever@eecs.umich.edu postExecute(); 5362644Sstever@eecs.umich.edu advanceInst(fault); 5372644Sstever@eecs.umich.edu } 5382623SN/A } else { 5392623SN/A // non-memory instruction: execute completely now 5402623SN/A Fault fault = curStaticInst->execute(this, traceData); 5412644Sstever@eecs.umich.edu postExecute(); 5422644Sstever@eecs.umich.edu advanceInst(fault); 5432623SN/A } 5443658Sktlim@umich.edu 5453658Sktlim@umich.edu delete pkt->req; 5463658Sktlim@umich.edu delete pkt; 5472623SN/A} 5482623SN/A 5492948Ssaidi@eecs.umich.eduvoid 5502948Ssaidi@eecs.umich.eduTimingSimpleCPU::IcachePort::ITickEvent::process() 5512948Ssaidi@eecs.umich.edu{ 5522948Ssaidi@eecs.umich.edu cpu->completeIfetch(pkt); 5532948Ssaidi@eecs.umich.edu} 5542623SN/A 5552623SN/Abool 5563349Sbinkertn@umich.eduTimingSimpleCPU::IcachePort::recvTiming(PacketPtr pkt) 5572623SN/A{ 5583310Srdreslin@umich.edu if (pkt->isResponse()) { 5593310Srdreslin@umich.edu // delay processing of returned data until next CPU clock edge 5603495Sktlim@umich.edu Tick mem_time = pkt->req->getTime(); 5613495Sktlim@umich.edu Tick next_tick = cpu->nextCycle(mem_time); 5622948Ssaidi@eecs.umich.edu 5633495Sktlim@umich.edu if (next_tick == curTick) 5643310Srdreslin@umich.edu cpu->completeIfetch(pkt); 5653310Srdreslin@umich.edu else 5663495Sktlim@umich.edu tickEvent.schedule(pkt, next_tick); 5672948Ssaidi@eecs.umich.edu 5683310Srdreslin@umich.edu return true; 5693310Srdreslin@umich.edu } 5703310Srdreslin@umich.edu else { 5713310Srdreslin@umich.edu //Snooping a Coherence Request, do nothing 5723310Srdreslin@umich.edu return true; 5733310Srdreslin@umich.edu } 5742623SN/A} 5752623SN/A 5762657Ssaidi@eecs.umich.eduvoid 5772623SN/ATimingSimpleCPU::IcachePort::recvRetry() 5782623SN/A{ 5792623SN/A // we shouldn't get a retry unless we have a packet that we're 5802623SN/A // waiting to transmit 5812623SN/A assert(cpu->ifetch_pkt != NULL); 5822623SN/A assert(cpu->_status == IcacheRetry); 5833349Sbinkertn@umich.edu PacketPtr tmp = cpu->ifetch_pkt; 5842657Ssaidi@eecs.umich.edu if (sendTiming(tmp)) { 5852657Ssaidi@eecs.umich.edu cpu->_status = IcacheWaitResponse; 5862657Ssaidi@eecs.umich.edu cpu->ifetch_pkt = NULL; 5872657Ssaidi@eecs.umich.edu } 5882623SN/A} 5892623SN/A 5902623SN/Avoid 5913349Sbinkertn@umich.eduTimingSimpleCPU::completeDataAccess(PacketPtr pkt) 5922623SN/A{ 5932623SN/A // received a response from the dcache: complete the load or store 5942623SN/A // instruction 5952641Sstever@eecs.umich.edu assert(pkt->result == Packet::Success); 5962623SN/A assert(_status == DcacheWaitResponse); 5972623SN/A _status = Running; 5982623SN/A 5993222Sktlim@umich.edu numCycles += curTick - previousTick; 6003222Sktlim@umich.edu previousTick = curTick; 6013184Srdreslin@umich.edu 6022623SN/A Fault fault = curStaticInst->completeAcc(pkt, this, traceData); 6032623SN/A 6043170Sstever@eecs.umich.edu if (pkt->isRead() && pkt->req->isLocked()) { 6053170Sstever@eecs.umich.edu TheISA::handleLockedRead(thread, pkt->req); 6063170Sstever@eecs.umich.edu } 6073170Sstever@eecs.umich.edu 6082644Sstever@eecs.umich.edu delete pkt->req; 6092644Sstever@eecs.umich.edu delete pkt; 6102644Sstever@eecs.umich.edu 6113184Srdreslin@umich.edu postExecute(); 6123227Sktlim@umich.edu 6133201Shsul@eecs.umich.edu if (getState() == SimObject::Draining) { 6143201Shsul@eecs.umich.edu advancePC(fault); 6153201Shsul@eecs.umich.edu completeDrain(); 6163201Shsul@eecs.umich.edu 6173201Shsul@eecs.umich.edu return; 6183201Shsul@eecs.umich.edu } 6193201Shsul@eecs.umich.edu 6202644Sstever@eecs.umich.edu advanceInst(fault); 6212623SN/A} 6222623SN/A 6232623SN/A 6242798Sktlim@umich.eduvoid 6252839Sktlim@umich.eduTimingSimpleCPU::completeDrain() 6262798Sktlim@umich.edu{ 6272839Sktlim@umich.edu DPRINTF(Config, "Done draining\n"); 6282901Ssaidi@eecs.umich.edu changeState(SimObject::Drained); 6292839Sktlim@umich.edu drainEvent->process(); 6302798Sktlim@umich.edu} 6312623SN/A 6322623SN/Abool 6333349Sbinkertn@umich.eduTimingSimpleCPU::DcachePort::recvTiming(PacketPtr pkt) 6342623SN/A{ 6353310Srdreslin@umich.edu if (pkt->isResponse()) { 6363310Srdreslin@umich.edu // delay processing of returned data until next CPU clock edge 6373495Sktlim@umich.edu Tick mem_time = pkt->req->getTime(); 6383495Sktlim@umich.edu Tick next_tick = cpu->nextCycle(mem_time); 6392948Ssaidi@eecs.umich.edu 6403495Sktlim@umich.edu if (next_tick == curTick) 6413310Srdreslin@umich.edu cpu->completeDataAccess(pkt); 6423310Srdreslin@umich.edu else 6433495Sktlim@umich.edu tickEvent.schedule(pkt, next_tick); 6442948Ssaidi@eecs.umich.edu 6453310Srdreslin@umich.edu return true; 6463310Srdreslin@umich.edu } 6473310Srdreslin@umich.edu else { 6483310Srdreslin@umich.edu //Snooping a coherence req, do nothing 6493310Srdreslin@umich.edu return true; 6503310Srdreslin@umich.edu } 6512948Ssaidi@eecs.umich.edu} 6522948Ssaidi@eecs.umich.edu 6532948Ssaidi@eecs.umich.eduvoid 6542948Ssaidi@eecs.umich.eduTimingSimpleCPU::DcachePort::DTickEvent::process() 6552948Ssaidi@eecs.umich.edu{ 6562630SN/A cpu->completeDataAccess(pkt); 6572623SN/A} 6582623SN/A 6592657Ssaidi@eecs.umich.eduvoid 6602623SN/ATimingSimpleCPU::DcachePort::recvRetry() 6612623SN/A{ 6622623SN/A // we shouldn't get a retry unless we have a packet that we're 6632623SN/A // waiting to transmit 6642623SN/A assert(cpu->dcache_pkt != NULL); 6652623SN/A assert(cpu->_status == DcacheRetry); 6663349Sbinkertn@umich.edu PacketPtr tmp = cpu->dcache_pkt; 6672657Ssaidi@eecs.umich.edu if (sendTiming(tmp)) { 6682657Ssaidi@eecs.umich.edu cpu->_status = DcacheWaitResponse; 6693170Sstever@eecs.umich.edu // memory system takes ownership of packet 6702657Ssaidi@eecs.umich.edu cpu->dcache_pkt = NULL; 6712657Ssaidi@eecs.umich.edu } 6722623SN/A} 6732623SN/A 6742623SN/A 6752623SN/A//////////////////////////////////////////////////////////////////////// 6762623SN/A// 6772623SN/A// TimingSimpleCPU Simulation Object 6782623SN/A// 6792623SN/ABEGIN_DECLARE_SIM_OBJECT_PARAMS(TimingSimpleCPU) 6802623SN/A 6812623SN/A Param<Counter> max_insts_any_thread; 6822623SN/A Param<Counter> max_insts_all_threads; 6832623SN/A Param<Counter> max_loads_any_thread; 6842623SN/A Param<Counter> max_loads_all_threads; 6853119Sktlim@umich.edu Param<Tick> progress_interval; 6862901Ssaidi@eecs.umich.edu SimObjectParam<System *> system; 6873170Sstever@eecs.umich.edu Param<int> cpu_id; 6882623SN/A 6892623SN/A#if FULL_SYSTEM 6903453Sgblack@eecs.umich.edu SimObjectParam<TheISA::ITB *> itb; 6913453Sgblack@eecs.umich.edu SimObjectParam<TheISA::DTB *> dtb; 6922623SN/A Param<Tick> profile; 6933617Sbinkertn@umich.edu 6943617Sbinkertn@umich.edu Param<bool> do_quiesce; 6953617Sbinkertn@umich.edu Param<bool> do_checkpoint_insts; 6963617Sbinkertn@umich.edu Param<bool> do_statistics_insts; 6972623SN/A#else 6982623SN/A SimObjectParam<Process *> workload; 6992623SN/A#endif // FULL_SYSTEM 7002623SN/A 7012623SN/A Param<int> clock; 7023661Srdreslin@umich.edu Param<int> phase; 7032623SN/A 7042623SN/A Param<bool> defer_registration; 7052623SN/A Param<int> width; 7062623SN/A Param<bool> function_trace; 7072623SN/A Param<Tick> function_trace_start; 7082623SN/A Param<bool> simulate_stalls; 7092623SN/A 7102623SN/AEND_DECLARE_SIM_OBJECT_PARAMS(TimingSimpleCPU) 7112623SN/A 7122623SN/ABEGIN_INIT_SIM_OBJECT_PARAMS(TimingSimpleCPU) 7132623SN/A 7142623SN/A INIT_PARAM(max_insts_any_thread, 7152623SN/A "terminate when any thread reaches this inst count"), 7162623SN/A INIT_PARAM(max_insts_all_threads, 7172623SN/A "terminate when all threads have reached this inst count"), 7182623SN/A INIT_PARAM(max_loads_any_thread, 7192623SN/A "terminate when any thread reaches this load count"), 7202623SN/A INIT_PARAM(max_loads_all_threads, 7212623SN/A "terminate when all threads have reached this load count"), 7223119Sktlim@umich.edu INIT_PARAM(progress_interval, "Progress interval"), 7232901Ssaidi@eecs.umich.edu INIT_PARAM(system, "system object"), 7243170Sstever@eecs.umich.edu INIT_PARAM(cpu_id, "processor ID"), 7252623SN/A 7262623SN/A#if FULL_SYSTEM 7272623SN/A INIT_PARAM(itb, "Instruction TLB"), 7282623SN/A INIT_PARAM(dtb, "Data TLB"), 7292623SN/A INIT_PARAM(profile, ""), 7303617Sbinkertn@umich.edu INIT_PARAM(do_quiesce, ""), 7313617Sbinkertn@umich.edu INIT_PARAM(do_checkpoint_insts, ""), 7323617Sbinkertn@umich.edu INIT_PARAM(do_statistics_insts, ""), 7332623SN/A#else 7342623SN/A INIT_PARAM(workload, "processes to run"), 7352623SN/A#endif // FULL_SYSTEM 7362623SN/A 7372623SN/A INIT_PARAM(clock, "clock speed"), 7383661Srdreslin@umich.edu INIT_PARAM_DFLT(phase, "clock phase", 0), 7392623SN/A INIT_PARAM(defer_registration, "defer system registration (for sampling)"), 7402623SN/A INIT_PARAM(width, "cpu width"), 7412623SN/A INIT_PARAM(function_trace, "Enable function trace"), 7422623SN/A INIT_PARAM(function_trace_start, "Cycle to start function trace"), 7432623SN/A INIT_PARAM(simulate_stalls, "Simulate cache stall cycles") 7442623SN/A 7452623SN/AEND_INIT_SIM_OBJECT_PARAMS(TimingSimpleCPU) 7462623SN/A 7472623SN/A 7482623SN/ACREATE_SIM_OBJECT(TimingSimpleCPU) 7492623SN/A{ 7502623SN/A TimingSimpleCPU::Params *params = new TimingSimpleCPU::Params(); 7512623SN/A params->name = getInstanceName(); 7522623SN/A params->numberOfThreads = 1; 7532623SN/A params->max_insts_any_thread = max_insts_any_thread; 7542623SN/A params->max_insts_all_threads = max_insts_all_threads; 7552623SN/A params->max_loads_any_thread = max_loads_any_thread; 7562623SN/A params->max_loads_all_threads = max_loads_all_threads; 7573119Sktlim@umich.edu params->progress_interval = progress_interval; 7582623SN/A params->deferRegistration = defer_registration; 7592623SN/A params->clock = clock; 7603661Srdreslin@umich.edu params->phase = phase; 7612623SN/A params->functionTrace = function_trace; 7622623SN/A params->functionTraceStart = function_trace_start; 7632901Ssaidi@eecs.umich.edu params->system = system; 7643170Sstever@eecs.umich.edu params->cpu_id = cpu_id; 7652623SN/A 7662623SN/A#if FULL_SYSTEM 7672623SN/A params->itb = itb; 7682623SN/A params->dtb = dtb; 7692623SN/A params->profile = profile; 7703617Sbinkertn@umich.edu params->do_quiesce = do_quiesce; 7713617Sbinkertn@umich.edu params->do_checkpoint_insts = do_checkpoint_insts; 7723617Sbinkertn@umich.edu params->do_statistics_insts = do_statistics_insts; 7732623SN/A#else 7742623SN/A params->process = workload; 7752623SN/A#endif 7762623SN/A 7772623SN/A TimingSimpleCPU *cpu = new TimingSimpleCPU(params); 7782623SN/A return cpu; 7792623SN/A} 7802623SN/A 7812623SN/AREGISTER_SIM_OBJECT("TimingSimpleCPU", TimingSimpleCPU) 7822623SN/A 783