timing.cc revision 2915
12623SN/A/* 22623SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 32623SN/A * All rights reserved. 42623SN/A * 52623SN/A * Redistribution and use in source and binary forms, with or without 62623SN/A * modification, are permitted provided that the following conditions are 72623SN/A * met: redistributions of source code must retain the above copyright 82623SN/A * notice, this list of conditions and the following disclaimer; 92623SN/A * redistributions in binary form must reproduce the above copyright 102623SN/A * notice, this list of conditions and the following disclaimer in the 112623SN/A * documentation and/or other materials provided with the distribution; 122623SN/A * neither the name of the copyright holders nor the names of its 132623SN/A * contributors may be used to endorse or promote products derived from 142623SN/A * this software without specific prior written permission. 152623SN/A * 162623SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172623SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182623SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192623SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202623SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212623SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222623SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232623SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242623SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252623SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262623SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 292623SN/A */ 302623SN/A 312623SN/A#include "arch/utility.hh" 322623SN/A#include "cpu/exetrace.hh" 332623SN/A#include "cpu/simple/timing.hh" 342623SN/A#include "mem/packet_impl.hh" 352623SN/A#include "sim/builder.hh" 362623SN/A 372623SN/Ausing namespace std; 382623SN/Ausing namespace TheISA; 392623SN/A 402856Srdreslin@umich.eduPort * 412856Srdreslin@umich.eduTimingSimpleCPU::getPort(const std::string &if_name, int idx) 422856Srdreslin@umich.edu{ 432856Srdreslin@umich.edu if (if_name == "dcache_port") 442856Srdreslin@umich.edu return &dcachePort; 452856Srdreslin@umich.edu else if (if_name == "icache_port") 462856Srdreslin@umich.edu return &icachePort; 472856Srdreslin@umich.edu else 482856Srdreslin@umich.edu panic("No Such Port\n"); 492856Srdreslin@umich.edu} 502623SN/A 512623SN/Avoid 522623SN/ATimingSimpleCPU::init() 532623SN/A{ 542623SN/A BaseCPU::init(); 552623SN/A#if FULL_SYSTEM 562680Sktlim@umich.edu for (int i = 0; i < threadContexts.size(); ++i) { 572680Sktlim@umich.edu ThreadContext *tc = threadContexts[i]; 582623SN/A 592623SN/A // initialize CPU, including PC 602680Sktlim@umich.edu TheISA::initCPU(tc, tc->readCpuId()); 612623SN/A } 622623SN/A#endif 632623SN/A} 642623SN/A 652623SN/ATick 662630SN/ATimingSimpleCPU::CpuPort::recvAtomic(Packet *pkt) 672623SN/A{ 682623SN/A panic("TimingSimpleCPU doesn't expect recvAtomic callback!"); 692623SN/A return curTick; 702623SN/A} 712623SN/A 722623SN/Avoid 732630SN/ATimingSimpleCPU::CpuPort::recvFunctional(Packet *pkt) 742623SN/A{ 752623SN/A panic("TimingSimpleCPU doesn't expect recvFunctional callback!"); 762623SN/A} 772623SN/A 782623SN/Avoid 792623SN/ATimingSimpleCPU::CpuPort::recvStatusChange(Status status) 802623SN/A{ 812631SN/A if (status == RangeChange) 822631SN/A return; 832631SN/A 842623SN/A panic("TimingSimpleCPU doesn't expect recvStatusChange callback!"); 852623SN/A} 862623SN/A 872623SN/ATimingSimpleCPU::TimingSimpleCPU(Params *p) 882623SN/A : BaseSimpleCPU(p), icachePort(this), dcachePort(this) 892623SN/A{ 902623SN/A _status = Idle; 912623SN/A ifetch_pkt = dcache_pkt = NULL; 922839Sktlim@umich.edu drainEvent = NULL; 932867Sktlim@umich.edu fetchEvent = NULL; 942798Sktlim@umich.edu state = SimObject::Timing; 952623SN/A} 962623SN/A 972623SN/A 982623SN/ATimingSimpleCPU::~TimingSimpleCPU() 992623SN/A{ 1002623SN/A} 1012623SN/A 1022623SN/Avoid 1032623SN/ATimingSimpleCPU::serialize(ostream &os) 1042623SN/A{ 1052915Sktlim@umich.edu SimObject::State so_state = SimObject::getState(); 1062915Sktlim@umich.edu SERIALIZE_ENUM(so_state); 1072623SN/A BaseSimpleCPU::serialize(os); 1082623SN/A} 1092623SN/A 1102623SN/Avoid 1112623SN/ATimingSimpleCPU::unserialize(Checkpoint *cp, const string §ion) 1122623SN/A{ 1132915Sktlim@umich.edu SimObject::State so_state; 1142915Sktlim@umich.edu UNSERIALIZE_ENUM(so_state); 1152623SN/A BaseSimpleCPU::unserialize(cp, section); 1162798Sktlim@umich.edu} 1172798Sktlim@umich.edu 1182798Sktlim@umich.edubool 1192839Sktlim@umich.eduTimingSimpleCPU::drain(Event *drain_event) 1202798Sktlim@umich.edu{ 1212839Sktlim@umich.edu // TimingSimpleCPU is ready to drain if it's not waiting for 1222798Sktlim@umich.edu // an access to complete. 1232798Sktlim@umich.edu if (status() == Idle || status() == Running || status() == SwitchedOut) { 1242839Sktlim@umich.edu changeState(SimObject::DrainedTiming); 1252860Sktlim@umich.edu return true; 1262798Sktlim@umich.edu } else { 1272839Sktlim@umich.edu changeState(SimObject::Draining); 1282839Sktlim@umich.edu drainEvent = drain_event; 1292860Sktlim@umich.edu return false; 1302798Sktlim@umich.edu } 1312623SN/A} 1322623SN/A 1332623SN/Avoid 1342798Sktlim@umich.eduTimingSimpleCPU::resume() 1352623SN/A{ 1362798Sktlim@umich.edu if (_status != SwitchedOut && _status != Idle) { 1372867Sktlim@umich.edu // Delete the old event if it existed. 1382867Sktlim@umich.edu if (fetchEvent) { 1392915Sktlim@umich.edu if (fetchEvent->scheduled()) 1402915Sktlim@umich.edu fetchEvent->deschedule(); 1412915Sktlim@umich.edu 1422867Sktlim@umich.edu delete fetchEvent; 1432867Sktlim@umich.edu } 1442867Sktlim@umich.edu 1452867Sktlim@umich.edu fetchEvent = 1462867Sktlim@umich.edu new EventWrapper<TimingSimpleCPU, &TimingSimpleCPU::fetch>(this, false); 1472867Sktlim@umich.edu fetchEvent->schedule(curTick); 1482623SN/A } 1492798Sktlim@umich.edu} 1502798Sktlim@umich.edu 1512798Sktlim@umich.eduvoid 1522798Sktlim@umich.eduTimingSimpleCPU::setMemoryMode(State new_mode) 1532798Sktlim@umich.edu{ 1542798Sktlim@umich.edu assert(new_mode == SimObject::Timing); 1552798Sktlim@umich.edu} 1562798Sktlim@umich.edu 1572798Sktlim@umich.eduvoid 1582798Sktlim@umich.eduTimingSimpleCPU::switchOut() 1592798Sktlim@umich.edu{ 1602798Sktlim@umich.edu assert(status() == Running || status() == Idle); 1612798Sktlim@umich.edu _status = SwitchedOut; 1622867Sktlim@umich.edu 1632867Sktlim@umich.edu // If we've been scheduled to resume but are then told to switch out, 1642867Sktlim@umich.edu // we'll need to cancel it. 1652867Sktlim@umich.edu if (fetchEvent && fetchEvent->scheduled()) 1662867Sktlim@umich.edu fetchEvent->deschedule(); 1672623SN/A} 1682623SN/A 1692623SN/A 1702623SN/Avoid 1712623SN/ATimingSimpleCPU::takeOverFrom(BaseCPU *oldCPU) 1722623SN/A{ 1732623SN/A BaseCPU::takeOverFrom(oldCPU); 1742623SN/A 1752680Sktlim@umich.edu // if any of this CPU's ThreadContexts are active, mark the CPU as 1762623SN/A // running and schedule its tick event. 1772680Sktlim@umich.edu for (int i = 0; i < threadContexts.size(); ++i) { 1782680Sktlim@umich.edu ThreadContext *tc = threadContexts[i]; 1792680Sktlim@umich.edu if (tc->status() == ThreadContext::Active && _status != Running) { 1802623SN/A _status = Running; 1812623SN/A break; 1822623SN/A } 1832623SN/A } 1842623SN/A} 1852623SN/A 1862623SN/A 1872623SN/Avoid 1882623SN/ATimingSimpleCPU::activateContext(int thread_num, int delay) 1892623SN/A{ 1902623SN/A assert(thread_num == 0); 1912683Sktlim@umich.edu assert(thread); 1922623SN/A 1932623SN/A assert(_status == Idle); 1942623SN/A 1952623SN/A notIdleFraction++; 1962623SN/A _status = Running; 1972623SN/A // kick things off by initiating the fetch of the next instruction 1982867Sktlim@umich.edu fetchEvent = 1992867Sktlim@umich.edu new EventWrapper<TimingSimpleCPU, &TimingSimpleCPU::fetch>(this, false); 2002867Sktlim@umich.edu fetchEvent->schedule(curTick + cycles(delay)); 2012623SN/A} 2022623SN/A 2032623SN/A 2042623SN/Avoid 2052623SN/ATimingSimpleCPU::suspendContext(int thread_num) 2062623SN/A{ 2072623SN/A assert(thread_num == 0); 2082683Sktlim@umich.edu assert(thread); 2092623SN/A 2102644Sstever@eecs.umich.edu assert(_status == Running); 2112623SN/A 2122644Sstever@eecs.umich.edu // just change status to Idle... if status != Running, 2132644Sstever@eecs.umich.edu // completeInst() will not initiate fetch of next instruction. 2142623SN/A 2152623SN/A notIdleFraction--; 2162623SN/A _status = Idle; 2172623SN/A} 2182623SN/A 2192623SN/A 2202623SN/Atemplate <class T> 2212623SN/AFault 2222623SN/ATimingSimpleCPU::read(Addr addr, T &data, unsigned flags) 2232623SN/A{ 2242663Sstever@eecs.umich.edu // need to fill in CPU & thread IDs here 2252663Sstever@eecs.umich.edu Request *data_read_req = new Request(); 2262835Srdreslin@umich.edu data_read_req->setThreadContext(0,0); //Need CPU/Thread IDS HERE 2272683Sktlim@umich.edu data_read_req->setVirt(0, addr, sizeof(T), flags, thread->readPC()); 2282623SN/A 2292623SN/A if (traceData) { 2302623SN/A traceData->setAddr(data_read_req->getVaddr()); 2312623SN/A } 2322623SN/A 2332623SN/A // translate to physical address 2342683Sktlim@umich.edu Fault fault = thread->translateDataReadReq(data_read_req); 2352623SN/A 2362623SN/A // Now do the access. 2372623SN/A if (fault == NoFault) { 2382641Sstever@eecs.umich.edu Packet *data_read_pkt = 2392641Sstever@eecs.umich.edu new Packet(data_read_req, Packet::ReadReq, Packet::Broadcast); 2402623SN/A data_read_pkt->dataDynamic<T>(new T); 2412623SN/A 2422630SN/A if (!dcachePort.sendTiming(data_read_pkt)) { 2432623SN/A _status = DcacheRetry; 2442623SN/A dcache_pkt = data_read_pkt; 2452623SN/A } else { 2462623SN/A _status = DcacheWaitResponse; 2472623SN/A dcache_pkt = NULL; 2482623SN/A } 2492623SN/A } 2502623SN/A 2512623SN/A // This will need a new way to tell if it has a dcache attached. 2522623SN/A if (data_read_req->getFlags() & UNCACHEABLE) 2532623SN/A recordEvent("Uncached Read"); 2542623SN/A 2552623SN/A return fault; 2562623SN/A} 2572623SN/A 2582623SN/A#ifndef DOXYGEN_SHOULD_SKIP_THIS 2592623SN/A 2602623SN/Atemplate 2612623SN/AFault 2622623SN/ATimingSimpleCPU::read(Addr addr, uint64_t &data, unsigned flags); 2632623SN/A 2642623SN/Atemplate 2652623SN/AFault 2662623SN/ATimingSimpleCPU::read(Addr addr, uint32_t &data, unsigned flags); 2672623SN/A 2682623SN/Atemplate 2692623SN/AFault 2702623SN/ATimingSimpleCPU::read(Addr addr, uint16_t &data, unsigned flags); 2712623SN/A 2722623SN/Atemplate 2732623SN/AFault 2742623SN/ATimingSimpleCPU::read(Addr addr, uint8_t &data, unsigned flags); 2752623SN/A 2762623SN/A#endif //DOXYGEN_SHOULD_SKIP_THIS 2772623SN/A 2782623SN/Atemplate<> 2792623SN/AFault 2802623SN/ATimingSimpleCPU::read(Addr addr, double &data, unsigned flags) 2812623SN/A{ 2822623SN/A return read(addr, *(uint64_t*)&data, flags); 2832623SN/A} 2842623SN/A 2852623SN/Atemplate<> 2862623SN/AFault 2872623SN/ATimingSimpleCPU::read(Addr addr, float &data, unsigned flags) 2882623SN/A{ 2892623SN/A return read(addr, *(uint32_t*)&data, flags); 2902623SN/A} 2912623SN/A 2922623SN/A 2932623SN/Atemplate<> 2942623SN/AFault 2952623SN/ATimingSimpleCPU::read(Addr addr, int32_t &data, unsigned flags) 2962623SN/A{ 2972623SN/A return read(addr, (uint32_t&)data, flags); 2982623SN/A} 2992623SN/A 3002623SN/A 3012623SN/Atemplate <class T> 3022623SN/AFault 3032623SN/ATimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res) 3042623SN/A{ 3052663Sstever@eecs.umich.edu // need to fill in CPU & thread IDs here 3062663Sstever@eecs.umich.edu Request *data_write_req = new Request(); 3072835Srdreslin@umich.edu data_write_req->setThreadContext(0,0); //Need CPU/Thread IDS HERE 3082683Sktlim@umich.edu data_write_req->setVirt(0, addr, sizeof(T), flags, thread->readPC()); 3092623SN/A 3102623SN/A // translate to physical address 3112683Sktlim@umich.edu Fault fault = thread->translateDataWriteReq(data_write_req); 3122623SN/A // Now do the access. 3132623SN/A if (fault == NoFault) { 3142641Sstever@eecs.umich.edu Packet *data_write_pkt = 3152641Sstever@eecs.umich.edu new Packet(data_write_req, Packet::WriteReq, Packet::Broadcast); 3162623SN/A data_write_pkt->allocate(); 3172623SN/A data_write_pkt->set(data); 3182623SN/A 3192630SN/A if (!dcachePort.sendTiming(data_write_pkt)) { 3202623SN/A _status = DcacheRetry; 3212623SN/A dcache_pkt = data_write_pkt; 3222623SN/A } else { 3232623SN/A _status = DcacheWaitResponse; 3242623SN/A dcache_pkt = NULL; 3252623SN/A } 3262623SN/A } 3272623SN/A 3282623SN/A // This will need a new way to tell if it's hooked up to a cache or not. 3292623SN/A if (data_write_req->getFlags() & UNCACHEABLE) 3302623SN/A recordEvent("Uncached Write"); 3312623SN/A 3322623SN/A // If the write needs to have a fault on the access, consider calling 3332623SN/A // changeStatus() and changing it to "bad addr write" or something. 3342623SN/A return fault; 3352623SN/A} 3362623SN/A 3372623SN/A 3382623SN/A#ifndef DOXYGEN_SHOULD_SKIP_THIS 3392623SN/Atemplate 3402623SN/AFault 3412623SN/ATimingSimpleCPU::write(uint64_t data, Addr addr, 3422623SN/A unsigned flags, uint64_t *res); 3432623SN/A 3442623SN/Atemplate 3452623SN/AFault 3462623SN/ATimingSimpleCPU::write(uint32_t data, Addr addr, 3472623SN/A unsigned flags, uint64_t *res); 3482623SN/A 3492623SN/Atemplate 3502623SN/AFault 3512623SN/ATimingSimpleCPU::write(uint16_t data, Addr addr, 3522623SN/A unsigned flags, uint64_t *res); 3532623SN/A 3542623SN/Atemplate 3552623SN/AFault 3562623SN/ATimingSimpleCPU::write(uint8_t data, Addr addr, 3572623SN/A unsigned flags, uint64_t *res); 3582623SN/A 3592623SN/A#endif //DOXYGEN_SHOULD_SKIP_THIS 3602623SN/A 3612623SN/Atemplate<> 3622623SN/AFault 3632623SN/ATimingSimpleCPU::write(double data, Addr addr, unsigned flags, uint64_t *res) 3642623SN/A{ 3652623SN/A return write(*(uint64_t*)&data, addr, flags, res); 3662623SN/A} 3672623SN/A 3682623SN/Atemplate<> 3692623SN/AFault 3702623SN/ATimingSimpleCPU::write(float data, Addr addr, unsigned flags, uint64_t *res) 3712623SN/A{ 3722623SN/A return write(*(uint32_t*)&data, addr, flags, res); 3732623SN/A} 3742623SN/A 3752623SN/A 3762623SN/Atemplate<> 3772623SN/AFault 3782623SN/ATimingSimpleCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res) 3792623SN/A{ 3802623SN/A return write((uint32_t)data, addr, flags, res); 3812623SN/A} 3822623SN/A 3832623SN/A 3842623SN/Avoid 3852623SN/ATimingSimpleCPU::fetch() 3862623SN/A{ 3872631SN/A checkForInterrupts(); 3882631SN/A 3892663Sstever@eecs.umich.edu // need to fill in CPU & thread IDs here 3902663Sstever@eecs.umich.edu Request *ifetch_req = new Request(); 3912835Srdreslin@umich.edu ifetch_req->setThreadContext(0,0); //Need CPU/Thread IDS HERE 3922662Sstever@eecs.umich.edu Fault fault = setupFetchRequest(ifetch_req); 3932623SN/A 3942641Sstever@eecs.umich.edu ifetch_pkt = new Packet(ifetch_req, Packet::ReadReq, Packet::Broadcast); 3952623SN/A ifetch_pkt->dataStatic(&inst); 3962623SN/A 3972623SN/A if (fault == NoFault) { 3982630SN/A if (!icachePort.sendTiming(ifetch_pkt)) { 3992623SN/A // Need to wait for retry 4002623SN/A _status = IcacheRetry; 4012623SN/A } else { 4022623SN/A // Need to wait for cache to respond 4032623SN/A _status = IcacheWaitResponse; 4042623SN/A // ownership of packet transferred to memory system 4052623SN/A ifetch_pkt = NULL; 4062623SN/A } 4072623SN/A } else { 4082644Sstever@eecs.umich.edu // fetch fault: advance directly to next instruction (fault handler) 4092644Sstever@eecs.umich.edu advanceInst(fault); 4102623SN/A } 4112623SN/A} 4122623SN/A 4132623SN/A 4142623SN/Avoid 4152644Sstever@eecs.umich.eduTimingSimpleCPU::advanceInst(Fault fault) 4162623SN/A{ 4172623SN/A advancePC(fault); 4182623SN/A 4192631SN/A if (_status == Running) { 4202631SN/A // kick off fetch of next instruction... callback from icache 4212631SN/A // response will cause that instruction to be executed, 4222631SN/A // keeping the CPU running. 4232631SN/A fetch(); 4242631SN/A } 4252623SN/A} 4262623SN/A 4272623SN/A 4282623SN/Avoid 4292644Sstever@eecs.umich.eduTimingSimpleCPU::completeIfetch(Packet *pkt) 4302623SN/A{ 4312623SN/A // received a response from the icache: execute the received 4322623SN/A // instruction 4332644Sstever@eecs.umich.edu assert(pkt->result == Packet::Success); 4342623SN/A assert(_status == IcacheWaitResponse); 4352798Sktlim@umich.edu 4362623SN/A _status = Running; 4372644Sstever@eecs.umich.edu 4382644Sstever@eecs.umich.edu delete pkt->req; 4392644Sstever@eecs.umich.edu delete pkt; 4402644Sstever@eecs.umich.edu 4412839Sktlim@umich.edu if (getState() == SimObject::Draining) { 4422839Sktlim@umich.edu completeDrain(); 4432798Sktlim@umich.edu return; 4442798Sktlim@umich.edu } 4452798Sktlim@umich.edu 4462623SN/A preExecute(); 4472644Sstever@eecs.umich.edu if (curStaticInst->isMemRef() && !curStaticInst->isDataPrefetch()) { 4482623SN/A // load or store: just send to dcache 4492623SN/A Fault fault = curStaticInst->initiateAcc(this, traceData); 4502644Sstever@eecs.umich.edu if (fault == NoFault) { 4512644Sstever@eecs.umich.edu // successfully initiated access: instruction will 4522644Sstever@eecs.umich.edu // complete in dcache response callback 4532644Sstever@eecs.umich.edu assert(_status == DcacheWaitResponse); 4542644Sstever@eecs.umich.edu } else { 4552644Sstever@eecs.umich.edu // fault: complete now to invoke fault handler 4562644Sstever@eecs.umich.edu postExecute(); 4572644Sstever@eecs.umich.edu advanceInst(fault); 4582644Sstever@eecs.umich.edu } 4592623SN/A } else { 4602623SN/A // non-memory instruction: execute completely now 4612623SN/A Fault fault = curStaticInst->execute(this, traceData); 4622644Sstever@eecs.umich.edu postExecute(); 4632644Sstever@eecs.umich.edu advanceInst(fault); 4642623SN/A } 4652623SN/A} 4662623SN/A 4672623SN/A 4682623SN/Abool 4692630SN/ATimingSimpleCPU::IcachePort::recvTiming(Packet *pkt) 4702623SN/A{ 4712857Srdreslin@umich.edu cpu->completeIfetch(pkt); 4722623SN/A return true; 4732623SN/A} 4742623SN/A 4752657Ssaidi@eecs.umich.eduvoid 4762623SN/ATimingSimpleCPU::IcachePort::recvRetry() 4772623SN/A{ 4782623SN/A // we shouldn't get a retry unless we have a packet that we're 4792623SN/A // waiting to transmit 4802623SN/A assert(cpu->ifetch_pkt != NULL); 4812623SN/A assert(cpu->_status == IcacheRetry); 4822623SN/A Packet *tmp = cpu->ifetch_pkt; 4832657Ssaidi@eecs.umich.edu if (sendTiming(tmp)) { 4842657Ssaidi@eecs.umich.edu cpu->_status = IcacheWaitResponse; 4852657Ssaidi@eecs.umich.edu cpu->ifetch_pkt = NULL; 4862657Ssaidi@eecs.umich.edu } 4872623SN/A} 4882623SN/A 4892623SN/Avoid 4902623SN/ATimingSimpleCPU::completeDataAccess(Packet *pkt) 4912623SN/A{ 4922623SN/A // received a response from the dcache: complete the load or store 4932623SN/A // instruction 4942641Sstever@eecs.umich.edu assert(pkt->result == Packet::Success); 4952623SN/A assert(_status == DcacheWaitResponse); 4962623SN/A _status = Running; 4972623SN/A 4982839Sktlim@umich.edu if (getState() == SimObject::Draining) { 4992839Sktlim@umich.edu completeDrain(); 5002798Sktlim@umich.edu 5012798Sktlim@umich.edu delete pkt->req; 5022798Sktlim@umich.edu delete pkt; 5032798Sktlim@umich.edu 5042798Sktlim@umich.edu return; 5052798Sktlim@umich.edu } 5062798Sktlim@umich.edu 5072623SN/A Fault fault = curStaticInst->completeAcc(pkt, this, traceData); 5082623SN/A 5092644Sstever@eecs.umich.edu delete pkt->req; 5102644Sstever@eecs.umich.edu delete pkt; 5112644Sstever@eecs.umich.edu 5122644Sstever@eecs.umich.edu postExecute(); 5132644Sstever@eecs.umich.edu advanceInst(fault); 5142623SN/A} 5152623SN/A 5162623SN/A 5172798Sktlim@umich.eduvoid 5182839Sktlim@umich.eduTimingSimpleCPU::completeDrain() 5192798Sktlim@umich.edu{ 5202839Sktlim@umich.edu DPRINTF(Config, "Done draining\n"); 5212839Sktlim@umich.edu changeState(SimObject::DrainedTiming); 5222839Sktlim@umich.edu drainEvent->process(); 5232798Sktlim@umich.edu} 5242623SN/A 5252623SN/Abool 5262630SN/ATimingSimpleCPU::DcachePort::recvTiming(Packet *pkt) 5272623SN/A{ 5282630SN/A cpu->completeDataAccess(pkt); 5292623SN/A return true; 5302623SN/A} 5312623SN/A 5322657Ssaidi@eecs.umich.eduvoid 5332623SN/ATimingSimpleCPU::DcachePort::recvRetry() 5342623SN/A{ 5352623SN/A // we shouldn't get a retry unless we have a packet that we're 5362623SN/A // waiting to transmit 5372623SN/A assert(cpu->dcache_pkt != NULL); 5382623SN/A assert(cpu->_status == DcacheRetry); 5392623SN/A Packet *tmp = cpu->dcache_pkt; 5402657Ssaidi@eecs.umich.edu if (sendTiming(tmp)) { 5412657Ssaidi@eecs.umich.edu cpu->_status = DcacheWaitResponse; 5422657Ssaidi@eecs.umich.edu cpu->dcache_pkt = NULL; 5432657Ssaidi@eecs.umich.edu } 5442623SN/A} 5452623SN/A 5462623SN/A 5472623SN/A//////////////////////////////////////////////////////////////////////// 5482623SN/A// 5492623SN/A// TimingSimpleCPU Simulation Object 5502623SN/A// 5512623SN/ABEGIN_DECLARE_SIM_OBJECT_PARAMS(TimingSimpleCPU) 5522623SN/A 5532623SN/A Param<Counter> max_insts_any_thread; 5542623SN/A Param<Counter> max_insts_all_threads; 5552623SN/A Param<Counter> max_loads_any_thread; 5562623SN/A Param<Counter> max_loads_all_threads; 5572623SN/A SimObjectParam<MemObject *> mem; 5582623SN/A 5592623SN/A#if FULL_SYSTEM 5602623SN/A SimObjectParam<AlphaITB *> itb; 5612623SN/A SimObjectParam<AlphaDTB *> dtb; 5622623SN/A SimObjectParam<System *> system; 5632623SN/A Param<int> cpu_id; 5642623SN/A Param<Tick> profile; 5652623SN/A#else 5662623SN/A SimObjectParam<Process *> workload; 5672623SN/A#endif // FULL_SYSTEM 5682623SN/A 5692623SN/A Param<int> clock; 5702623SN/A 5712623SN/A Param<bool> defer_registration; 5722623SN/A Param<int> width; 5732623SN/A Param<bool> function_trace; 5742623SN/A Param<Tick> function_trace_start; 5752623SN/A Param<bool> simulate_stalls; 5762623SN/A 5772623SN/AEND_DECLARE_SIM_OBJECT_PARAMS(TimingSimpleCPU) 5782623SN/A 5792623SN/ABEGIN_INIT_SIM_OBJECT_PARAMS(TimingSimpleCPU) 5802623SN/A 5812623SN/A INIT_PARAM(max_insts_any_thread, 5822623SN/A "terminate when any thread reaches this inst count"), 5832623SN/A INIT_PARAM(max_insts_all_threads, 5842623SN/A "terminate when all threads have reached this inst count"), 5852623SN/A INIT_PARAM(max_loads_any_thread, 5862623SN/A "terminate when any thread reaches this load count"), 5872623SN/A INIT_PARAM(max_loads_all_threads, 5882623SN/A "terminate when all threads have reached this load count"), 5892623SN/A INIT_PARAM(mem, "memory"), 5902623SN/A 5912623SN/A#if FULL_SYSTEM 5922623SN/A INIT_PARAM(itb, "Instruction TLB"), 5932623SN/A INIT_PARAM(dtb, "Data TLB"), 5942623SN/A INIT_PARAM(system, "system object"), 5952623SN/A INIT_PARAM(cpu_id, "processor ID"), 5962623SN/A INIT_PARAM(profile, ""), 5972623SN/A#else 5982623SN/A INIT_PARAM(workload, "processes to run"), 5992623SN/A#endif // FULL_SYSTEM 6002623SN/A 6012623SN/A INIT_PARAM(clock, "clock speed"), 6022623SN/A INIT_PARAM(defer_registration, "defer system registration (for sampling)"), 6032623SN/A INIT_PARAM(width, "cpu width"), 6042623SN/A INIT_PARAM(function_trace, "Enable function trace"), 6052623SN/A INIT_PARAM(function_trace_start, "Cycle to start function trace"), 6062623SN/A INIT_PARAM(simulate_stalls, "Simulate cache stall cycles") 6072623SN/A 6082623SN/AEND_INIT_SIM_OBJECT_PARAMS(TimingSimpleCPU) 6092623SN/A 6102623SN/A 6112623SN/ACREATE_SIM_OBJECT(TimingSimpleCPU) 6122623SN/A{ 6132623SN/A TimingSimpleCPU::Params *params = new TimingSimpleCPU::Params(); 6142623SN/A params->name = getInstanceName(); 6152623SN/A params->numberOfThreads = 1; 6162623SN/A params->max_insts_any_thread = max_insts_any_thread; 6172623SN/A params->max_insts_all_threads = max_insts_all_threads; 6182623SN/A params->max_loads_any_thread = max_loads_any_thread; 6192623SN/A params->max_loads_all_threads = max_loads_all_threads; 6202623SN/A params->deferRegistration = defer_registration; 6212623SN/A params->clock = clock; 6222623SN/A params->functionTrace = function_trace; 6232623SN/A params->functionTraceStart = function_trace_start; 6242623SN/A params->mem = mem; 6252623SN/A 6262623SN/A#if FULL_SYSTEM 6272623SN/A params->itb = itb; 6282623SN/A params->dtb = dtb; 6292623SN/A params->system = system; 6302623SN/A params->cpu_id = cpu_id; 6312623SN/A params->profile = profile; 6322623SN/A#else 6332623SN/A params->process = workload; 6342623SN/A#endif 6352623SN/A 6362623SN/A TimingSimpleCPU *cpu = new TimingSimpleCPU(params); 6372623SN/A return cpu; 6382623SN/A} 6392623SN/A 6402623SN/AREGISTER_SIM_OBJECT("TimingSimpleCPU", TimingSimpleCPU) 6412623SN/A 642