timing.cc revision 2665
12623SN/A/* 22623SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 32623SN/A * All rights reserved. 42623SN/A * 52623SN/A * Redistribution and use in source and binary forms, with or without 62623SN/A * modification, are permitted provided that the following conditions are 72623SN/A * met: redistributions of source code must retain the above copyright 82623SN/A * notice, this list of conditions and the following disclaimer; 92623SN/A * redistributions in binary form must reproduce the above copyright 102623SN/A * notice, this list of conditions and the following disclaimer in the 112623SN/A * documentation and/or other materials provided with the distribution; 122623SN/A * neither the name of the copyright holders nor the names of its 132623SN/A * contributors may be used to endorse or promote products derived from 142623SN/A * this software without specific prior written permission. 152623SN/A * 162623SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172623SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182623SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192623SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202623SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212623SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222623SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232623SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242623SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252623SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262623SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 292623SN/A */ 302623SN/A 312623SN/A#include "arch/utility.hh" 322623SN/A#include "cpu/exetrace.hh" 332623SN/A#include "cpu/simple/timing.hh" 342623SN/A#include "mem/packet_impl.hh" 352623SN/A#include "sim/builder.hh" 362623SN/A 372623SN/Ausing namespace std; 382623SN/Ausing namespace TheISA; 392623SN/A 402623SN/A 412623SN/Avoid 422623SN/ATimingSimpleCPU::init() 432623SN/A{ 442623SN/A //Create Memory Ports (conect them up) 452623SN/A Port *mem_dport = mem->getPort(""); 462623SN/A dcachePort.setPeer(mem_dport); 472623SN/A mem_dport->setPeer(&dcachePort); 482623SN/A 492623SN/A Port *mem_iport = mem->getPort(""); 502623SN/A icachePort.setPeer(mem_iport); 512623SN/A mem_iport->setPeer(&icachePort); 522623SN/A 532623SN/A BaseCPU::init(); 542623SN/A#if FULL_SYSTEM 552623SN/A for (int i = 0; i < execContexts.size(); ++i) { 562623SN/A ExecContext *xc = execContexts[i]; 572623SN/A 582623SN/A // initialize CPU, including PC 592623SN/A TheISA::initCPU(xc, xc->readCpuId()); 602623SN/A } 612623SN/A#endif 622623SN/A} 632623SN/A 642623SN/ATick 652630SN/ATimingSimpleCPU::CpuPort::recvAtomic(Packet *pkt) 662623SN/A{ 672623SN/A panic("TimingSimpleCPU doesn't expect recvAtomic callback!"); 682623SN/A return curTick; 692623SN/A} 702623SN/A 712623SN/Avoid 722630SN/ATimingSimpleCPU::CpuPort::recvFunctional(Packet *pkt) 732623SN/A{ 742623SN/A panic("TimingSimpleCPU doesn't expect recvFunctional callback!"); 752623SN/A} 762623SN/A 772623SN/Avoid 782623SN/ATimingSimpleCPU::CpuPort::recvStatusChange(Status status) 792623SN/A{ 802631SN/A if (status == RangeChange) 812631SN/A return; 822631SN/A 832623SN/A panic("TimingSimpleCPU doesn't expect recvStatusChange callback!"); 842623SN/A} 852623SN/A 862623SN/ATimingSimpleCPU::TimingSimpleCPU(Params *p) 872623SN/A : BaseSimpleCPU(p), icachePort(this), dcachePort(this) 882623SN/A{ 892623SN/A _status = Idle; 902623SN/A ifetch_pkt = dcache_pkt = NULL; 912623SN/A} 922623SN/A 932623SN/A 942623SN/ATimingSimpleCPU::~TimingSimpleCPU() 952623SN/A{ 962623SN/A} 972623SN/A 982623SN/Avoid 992623SN/ATimingSimpleCPU::serialize(ostream &os) 1002623SN/A{ 1012623SN/A BaseSimpleCPU::serialize(os); 1022623SN/A SERIALIZE_ENUM(_status); 1032623SN/A} 1042623SN/A 1052623SN/Avoid 1062623SN/ATimingSimpleCPU::unserialize(Checkpoint *cp, const string §ion) 1072623SN/A{ 1082623SN/A BaseSimpleCPU::unserialize(cp, section); 1092623SN/A UNSERIALIZE_ENUM(_status); 1102623SN/A} 1112623SN/A 1122623SN/Avoid 1132623SN/ATimingSimpleCPU::switchOut(Sampler *s) 1142623SN/A{ 1152623SN/A sampler = s; 1162623SN/A if (status() == Running) { 1172623SN/A _status = SwitchedOut; 1182623SN/A } 1192623SN/A sampler->signalSwitched(); 1202623SN/A} 1212623SN/A 1222623SN/A 1232623SN/Avoid 1242623SN/ATimingSimpleCPU::takeOverFrom(BaseCPU *oldCPU) 1252623SN/A{ 1262623SN/A BaseCPU::takeOverFrom(oldCPU); 1272623SN/A 1282623SN/A // if any of this CPU's ExecContexts are active, mark the CPU as 1292623SN/A // running and schedule its tick event. 1302623SN/A for (int i = 0; i < execContexts.size(); ++i) { 1312623SN/A ExecContext *xc = execContexts[i]; 1322623SN/A if (xc->status() == ExecContext::Active && _status != Running) { 1332623SN/A _status = Running; 1342623SN/A break; 1352623SN/A } 1362623SN/A } 1372623SN/A} 1382623SN/A 1392623SN/A 1402623SN/Avoid 1412623SN/ATimingSimpleCPU::activateContext(int thread_num, int delay) 1422623SN/A{ 1432623SN/A assert(thread_num == 0); 1442623SN/A assert(cpuXC); 1452623SN/A 1462623SN/A assert(_status == Idle); 1472623SN/A 1482623SN/A notIdleFraction++; 1492623SN/A _status = Running; 1502623SN/A // kick things off by initiating the fetch of the next instruction 1512623SN/A Event *e = 1522623SN/A new EventWrapper<TimingSimpleCPU, &TimingSimpleCPU::fetch>(this, true); 1532623SN/A e->schedule(curTick + cycles(delay)); 1542623SN/A} 1552623SN/A 1562623SN/A 1572623SN/Avoid 1582623SN/ATimingSimpleCPU::suspendContext(int thread_num) 1592623SN/A{ 1602623SN/A assert(thread_num == 0); 1612623SN/A assert(cpuXC); 1622623SN/A 1632644Sstever@eecs.umich.edu assert(_status == Running); 1642623SN/A 1652644Sstever@eecs.umich.edu // just change status to Idle... if status != Running, 1662644Sstever@eecs.umich.edu // completeInst() will not initiate fetch of next instruction. 1672623SN/A 1682623SN/A notIdleFraction--; 1692623SN/A _status = Idle; 1702623SN/A} 1712623SN/A 1722623SN/A 1732623SN/Atemplate <class T> 1742623SN/AFault 1752623SN/ATimingSimpleCPU::read(Addr addr, T &data, unsigned flags) 1762623SN/A{ 1772663Sstever@eecs.umich.edu // need to fill in CPU & thread IDs here 1782663Sstever@eecs.umich.edu Request *data_read_req = new Request(); 1792623SN/A 1802663Sstever@eecs.umich.edu data_read_req->setVirt(0, addr, sizeof(T), flags, cpuXC->readPC()); 1812623SN/A 1822623SN/A if (traceData) { 1832623SN/A traceData->setAddr(data_read_req->getVaddr()); 1842623SN/A } 1852623SN/A 1862623SN/A // translate to physical address 1872623SN/A Fault fault = cpuXC->translateDataReadReq(data_read_req); 1882623SN/A 1892623SN/A // Now do the access. 1902623SN/A if (fault == NoFault) { 1912641Sstever@eecs.umich.edu Packet *data_read_pkt = 1922641Sstever@eecs.umich.edu new Packet(data_read_req, Packet::ReadReq, Packet::Broadcast); 1932623SN/A data_read_pkt->dataDynamic<T>(new T); 1942623SN/A 1952630SN/A if (!dcachePort.sendTiming(data_read_pkt)) { 1962623SN/A _status = DcacheRetry; 1972623SN/A dcache_pkt = data_read_pkt; 1982623SN/A } else { 1992623SN/A _status = DcacheWaitResponse; 2002623SN/A dcache_pkt = NULL; 2012623SN/A } 2022623SN/A } 2032623SN/A 2042623SN/A // This will need a new way to tell if it has a dcache attached. 2052623SN/A if (data_read_req->getFlags() & UNCACHEABLE) 2062623SN/A recordEvent("Uncached Read"); 2072623SN/A 2082623SN/A return fault; 2092623SN/A} 2102623SN/A 2112623SN/A#ifndef DOXYGEN_SHOULD_SKIP_THIS 2122623SN/A 2132623SN/Atemplate 2142623SN/AFault 2152623SN/ATimingSimpleCPU::read(Addr addr, uint64_t &data, unsigned flags); 2162623SN/A 2172623SN/Atemplate 2182623SN/AFault 2192623SN/ATimingSimpleCPU::read(Addr addr, uint32_t &data, unsigned flags); 2202623SN/A 2212623SN/Atemplate 2222623SN/AFault 2232623SN/ATimingSimpleCPU::read(Addr addr, uint16_t &data, unsigned flags); 2242623SN/A 2252623SN/Atemplate 2262623SN/AFault 2272623SN/ATimingSimpleCPU::read(Addr addr, uint8_t &data, unsigned flags); 2282623SN/A 2292623SN/A#endif //DOXYGEN_SHOULD_SKIP_THIS 2302623SN/A 2312623SN/Atemplate<> 2322623SN/AFault 2332623SN/ATimingSimpleCPU::read(Addr addr, double &data, unsigned flags) 2342623SN/A{ 2352623SN/A return read(addr, *(uint64_t*)&data, flags); 2362623SN/A} 2372623SN/A 2382623SN/Atemplate<> 2392623SN/AFault 2402623SN/ATimingSimpleCPU::read(Addr addr, float &data, unsigned flags) 2412623SN/A{ 2422623SN/A return read(addr, *(uint32_t*)&data, flags); 2432623SN/A} 2442623SN/A 2452623SN/A 2462623SN/Atemplate<> 2472623SN/AFault 2482623SN/ATimingSimpleCPU::read(Addr addr, int32_t &data, unsigned flags) 2492623SN/A{ 2502623SN/A return read(addr, (uint32_t&)data, flags); 2512623SN/A} 2522623SN/A 2532623SN/A 2542623SN/Atemplate <class T> 2552623SN/AFault 2562623SN/ATimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res) 2572623SN/A{ 2582663Sstever@eecs.umich.edu // need to fill in CPU & thread IDs here 2592663Sstever@eecs.umich.edu Request *data_write_req = new Request(); 2602663Sstever@eecs.umich.edu data_write_req->setVirt(0, addr, sizeof(T), flags, cpuXC->readPC()); 2612623SN/A 2622623SN/A // translate to physical address 2632623SN/A Fault fault = cpuXC->translateDataWriteReq(data_write_req); 2642623SN/A // Now do the access. 2652623SN/A if (fault == NoFault) { 2662641Sstever@eecs.umich.edu Packet *data_write_pkt = 2672641Sstever@eecs.umich.edu new Packet(data_write_req, Packet::WriteReq, Packet::Broadcast); 2682623SN/A data_write_pkt->allocate(); 2692623SN/A data_write_pkt->set(data); 2702623SN/A 2712630SN/A if (!dcachePort.sendTiming(data_write_pkt)) { 2722623SN/A _status = DcacheRetry; 2732623SN/A dcache_pkt = data_write_pkt; 2742623SN/A } else { 2752623SN/A _status = DcacheWaitResponse; 2762623SN/A dcache_pkt = NULL; 2772623SN/A } 2782623SN/A } 2792623SN/A 2802623SN/A // This will need a new way to tell if it's hooked up to a cache or not. 2812623SN/A if (data_write_req->getFlags() & UNCACHEABLE) 2822623SN/A recordEvent("Uncached Write"); 2832623SN/A 2842623SN/A // If the write needs to have a fault on the access, consider calling 2852623SN/A // changeStatus() and changing it to "bad addr write" or something. 2862623SN/A return fault; 2872623SN/A} 2882623SN/A 2892623SN/A 2902623SN/A#ifndef DOXYGEN_SHOULD_SKIP_THIS 2912623SN/Atemplate 2922623SN/AFault 2932623SN/ATimingSimpleCPU::write(uint64_t data, Addr addr, 2942623SN/A unsigned flags, uint64_t *res); 2952623SN/A 2962623SN/Atemplate 2972623SN/AFault 2982623SN/ATimingSimpleCPU::write(uint32_t data, Addr addr, 2992623SN/A unsigned flags, uint64_t *res); 3002623SN/A 3012623SN/Atemplate 3022623SN/AFault 3032623SN/ATimingSimpleCPU::write(uint16_t data, Addr addr, 3042623SN/A unsigned flags, uint64_t *res); 3052623SN/A 3062623SN/Atemplate 3072623SN/AFault 3082623SN/ATimingSimpleCPU::write(uint8_t data, Addr addr, 3092623SN/A unsigned flags, uint64_t *res); 3102623SN/A 3112623SN/A#endif //DOXYGEN_SHOULD_SKIP_THIS 3122623SN/A 3132623SN/Atemplate<> 3142623SN/AFault 3152623SN/ATimingSimpleCPU::write(double data, Addr addr, unsigned flags, uint64_t *res) 3162623SN/A{ 3172623SN/A return write(*(uint64_t*)&data, addr, flags, res); 3182623SN/A} 3192623SN/A 3202623SN/Atemplate<> 3212623SN/AFault 3222623SN/ATimingSimpleCPU::write(float data, Addr addr, unsigned flags, uint64_t *res) 3232623SN/A{ 3242623SN/A return write(*(uint32_t*)&data, addr, flags, res); 3252623SN/A} 3262623SN/A 3272623SN/A 3282623SN/Atemplate<> 3292623SN/AFault 3302623SN/ATimingSimpleCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res) 3312623SN/A{ 3322623SN/A return write((uint32_t)data, addr, flags, res); 3332623SN/A} 3342623SN/A 3352623SN/A 3362623SN/Avoid 3372623SN/ATimingSimpleCPU::fetch() 3382623SN/A{ 3392631SN/A checkForInterrupts(); 3402631SN/A 3412663Sstever@eecs.umich.edu // need to fill in CPU & thread IDs here 3422663Sstever@eecs.umich.edu Request *ifetch_req = new Request(); 3432662Sstever@eecs.umich.edu Fault fault = setupFetchRequest(ifetch_req); 3442623SN/A 3452641Sstever@eecs.umich.edu ifetch_pkt = new Packet(ifetch_req, Packet::ReadReq, Packet::Broadcast); 3462623SN/A ifetch_pkt->dataStatic(&inst); 3472623SN/A 3482623SN/A if (fault == NoFault) { 3492630SN/A if (!icachePort.sendTiming(ifetch_pkt)) { 3502623SN/A // Need to wait for retry 3512623SN/A _status = IcacheRetry; 3522623SN/A } else { 3532623SN/A // Need to wait for cache to respond 3542623SN/A _status = IcacheWaitResponse; 3552623SN/A // ownership of packet transferred to memory system 3562623SN/A ifetch_pkt = NULL; 3572623SN/A } 3582623SN/A } else { 3592644Sstever@eecs.umich.edu // fetch fault: advance directly to next instruction (fault handler) 3602644Sstever@eecs.umich.edu advanceInst(fault); 3612623SN/A } 3622623SN/A} 3632623SN/A 3642623SN/A 3652623SN/Avoid 3662644Sstever@eecs.umich.eduTimingSimpleCPU::advanceInst(Fault fault) 3672623SN/A{ 3682623SN/A advancePC(fault); 3692623SN/A 3702631SN/A if (_status == Running) { 3712631SN/A // kick off fetch of next instruction... callback from icache 3722631SN/A // response will cause that instruction to be executed, 3732631SN/A // keeping the CPU running. 3742631SN/A fetch(); 3752631SN/A } 3762623SN/A} 3772623SN/A 3782623SN/A 3792623SN/Avoid 3802644Sstever@eecs.umich.eduTimingSimpleCPU::completeIfetch(Packet *pkt) 3812623SN/A{ 3822623SN/A // received a response from the icache: execute the received 3832623SN/A // instruction 3842644Sstever@eecs.umich.edu assert(pkt->result == Packet::Success); 3852623SN/A assert(_status == IcacheWaitResponse); 3862623SN/A _status = Running; 3872644Sstever@eecs.umich.edu 3882644Sstever@eecs.umich.edu delete pkt->req; 3892644Sstever@eecs.umich.edu delete pkt; 3902644Sstever@eecs.umich.edu 3912623SN/A preExecute(); 3922644Sstever@eecs.umich.edu if (curStaticInst->isMemRef() && !curStaticInst->isDataPrefetch()) { 3932623SN/A // load or store: just send to dcache 3942623SN/A Fault fault = curStaticInst->initiateAcc(this, traceData); 3952644Sstever@eecs.umich.edu if (fault == NoFault) { 3962644Sstever@eecs.umich.edu // successfully initiated access: instruction will 3972644Sstever@eecs.umich.edu // complete in dcache response callback 3982644Sstever@eecs.umich.edu assert(_status == DcacheWaitResponse); 3992644Sstever@eecs.umich.edu } else { 4002644Sstever@eecs.umich.edu // fault: complete now to invoke fault handler 4012644Sstever@eecs.umich.edu postExecute(); 4022644Sstever@eecs.umich.edu advanceInst(fault); 4032644Sstever@eecs.umich.edu } 4042623SN/A } else { 4052623SN/A // non-memory instruction: execute completely now 4062623SN/A Fault fault = curStaticInst->execute(this, traceData); 4072644Sstever@eecs.umich.edu postExecute(); 4082644Sstever@eecs.umich.edu advanceInst(fault); 4092623SN/A } 4102623SN/A} 4112623SN/A 4122623SN/A 4132623SN/Abool 4142630SN/ATimingSimpleCPU::IcachePort::recvTiming(Packet *pkt) 4152623SN/A{ 4162644Sstever@eecs.umich.edu cpu->completeIfetch(pkt); 4172623SN/A return true; 4182623SN/A} 4192623SN/A 4202657Ssaidi@eecs.umich.eduvoid 4212623SN/ATimingSimpleCPU::IcachePort::recvRetry() 4222623SN/A{ 4232623SN/A // we shouldn't get a retry unless we have a packet that we're 4242623SN/A // waiting to transmit 4252623SN/A assert(cpu->ifetch_pkt != NULL); 4262623SN/A assert(cpu->_status == IcacheRetry); 4272623SN/A Packet *tmp = cpu->ifetch_pkt; 4282657Ssaidi@eecs.umich.edu if (sendTiming(tmp)) { 4292657Ssaidi@eecs.umich.edu cpu->_status = IcacheWaitResponse; 4302657Ssaidi@eecs.umich.edu cpu->ifetch_pkt = NULL; 4312657Ssaidi@eecs.umich.edu } 4322623SN/A} 4332623SN/A 4342623SN/Avoid 4352623SN/ATimingSimpleCPU::completeDataAccess(Packet *pkt) 4362623SN/A{ 4372623SN/A // received a response from the dcache: complete the load or store 4382623SN/A // instruction 4392641Sstever@eecs.umich.edu assert(pkt->result == Packet::Success); 4402623SN/A assert(_status == DcacheWaitResponse); 4412623SN/A _status = Running; 4422623SN/A 4432623SN/A Fault fault = curStaticInst->completeAcc(pkt, this, traceData); 4442623SN/A 4452644Sstever@eecs.umich.edu delete pkt->req; 4462644Sstever@eecs.umich.edu delete pkt; 4472644Sstever@eecs.umich.edu 4482644Sstever@eecs.umich.edu postExecute(); 4492644Sstever@eecs.umich.edu advanceInst(fault); 4502623SN/A} 4512623SN/A 4522623SN/A 4532623SN/A 4542623SN/Abool 4552630SN/ATimingSimpleCPU::DcachePort::recvTiming(Packet *pkt) 4562623SN/A{ 4572630SN/A cpu->completeDataAccess(pkt); 4582623SN/A return true; 4592623SN/A} 4602623SN/A 4612657Ssaidi@eecs.umich.eduvoid 4622623SN/ATimingSimpleCPU::DcachePort::recvRetry() 4632623SN/A{ 4642623SN/A // we shouldn't get a retry unless we have a packet that we're 4652623SN/A // waiting to transmit 4662623SN/A assert(cpu->dcache_pkt != NULL); 4672623SN/A assert(cpu->_status == DcacheRetry); 4682623SN/A Packet *tmp = cpu->dcache_pkt; 4692657Ssaidi@eecs.umich.edu if (sendTiming(tmp)) { 4702657Ssaidi@eecs.umich.edu cpu->_status = DcacheWaitResponse; 4712657Ssaidi@eecs.umich.edu cpu->dcache_pkt = NULL; 4722657Ssaidi@eecs.umich.edu } 4732623SN/A} 4742623SN/A 4752623SN/A 4762623SN/A//////////////////////////////////////////////////////////////////////// 4772623SN/A// 4782623SN/A// TimingSimpleCPU Simulation Object 4792623SN/A// 4802623SN/ABEGIN_DECLARE_SIM_OBJECT_PARAMS(TimingSimpleCPU) 4812623SN/A 4822623SN/A Param<Counter> max_insts_any_thread; 4832623SN/A Param<Counter> max_insts_all_threads; 4842623SN/A Param<Counter> max_loads_any_thread; 4852623SN/A Param<Counter> max_loads_all_threads; 4862623SN/A SimObjectParam<MemObject *> mem; 4872623SN/A 4882623SN/A#if FULL_SYSTEM 4892623SN/A SimObjectParam<AlphaITB *> itb; 4902623SN/A SimObjectParam<AlphaDTB *> dtb; 4912623SN/A SimObjectParam<System *> system; 4922623SN/A Param<int> cpu_id; 4932623SN/A Param<Tick> profile; 4942623SN/A#else 4952623SN/A SimObjectParam<Process *> workload; 4962623SN/A#endif // FULL_SYSTEM 4972623SN/A 4982623SN/A Param<int> clock; 4992623SN/A 5002623SN/A Param<bool> defer_registration; 5012623SN/A Param<int> width; 5022623SN/A Param<bool> function_trace; 5032623SN/A Param<Tick> function_trace_start; 5042623SN/A Param<bool> simulate_stalls; 5052623SN/A 5062623SN/AEND_DECLARE_SIM_OBJECT_PARAMS(TimingSimpleCPU) 5072623SN/A 5082623SN/ABEGIN_INIT_SIM_OBJECT_PARAMS(TimingSimpleCPU) 5092623SN/A 5102623SN/A INIT_PARAM(max_insts_any_thread, 5112623SN/A "terminate when any thread reaches this inst count"), 5122623SN/A INIT_PARAM(max_insts_all_threads, 5132623SN/A "terminate when all threads have reached this inst count"), 5142623SN/A INIT_PARAM(max_loads_any_thread, 5152623SN/A "terminate when any thread reaches this load count"), 5162623SN/A INIT_PARAM(max_loads_all_threads, 5172623SN/A "terminate when all threads have reached this load count"), 5182623SN/A INIT_PARAM(mem, "memory"), 5192623SN/A 5202623SN/A#if FULL_SYSTEM 5212623SN/A INIT_PARAM(itb, "Instruction TLB"), 5222623SN/A INIT_PARAM(dtb, "Data TLB"), 5232623SN/A INIT_PARAM(system, "system object"), 5242623SN/A INIT_PARAM(cpu_id, "processor ID"), 5252623SN/A INIT_PARAM(profile, ""), 5262623SN/A#else 5272623SN/A INIT_PARAM(workload, "processes to run"), 5282623SN/A#endif // FULL_SYSTEM 5292623SN/A 5302623SN/A INIT_PARAM(clock, "clock speed"), 5312623SN/A INIT_PARAM(defer_registration, "defer system registration (for sampling)"), 5322623SN/A INIT_PARAM(width, "cpu width"), 5332623SN/A INIT_PARAM(function_trace, "Enable function trace"), 5342623SN/A INIT_PARAM(function_trace_start, "Cycle to start function trace"), 5352623SN/A INIT_PARAM(simulate_stalls, "Simulate cache stall cycles") 5362623SN/A 5372623SN/AEND_INIT_SIM_OBJECT_PARAMS(TimingSimpleCPU) 5382623SN/A 5392623SN/A 5402623SN/ACREATE_SIM_OBJECT(TimingSimpleCPU) 5412623SN/A{ 5422623SN/A TimingSimpleCPU::Params *params = new TimingSimpleCPU::Params(); 5432623SN/A params->name = getInstanceName(); 5442623SN/A params->numberOfThreads = 1; 5452623SN/A params->max_insts_any_thread = max_insts_any_thread; 5462623SN/A params->max_insts_all_threads = max_insts_all_threads; 5472623SN/A params->max_loads_any_thread = max_loads_any_thread; 5482623SN/A params->max_loads_all_threads = max_loads_all_threads; 5492623SN/A params->deferRegistration = defer_registration; 5502623SN/A params->clock = clock; 5512623SN/A params->functionTrace = function_trace; 5522623SN/A params->functionTraceStart = function_trace_start; 5532623SN/A params->mem = mem; 5542623SN/A 5552623SN/A#if FULL_SYSTEM 5562623SN/A params->itb = itb; 5572623SN/A params->dtb = dtb; 5582623SN/A params->system = system; 5592623SN/A params->cpu_id = cpu_id; 5602623SN/A params->profile = profile; 5612623SN/A#else 5622623SN/A params->process = workload; 5632623SN/A#endif 5642623SN/A 5652623SN/A TimingSimpleCPU *cpu = new TimingSimpleCPU(params); 5662623SN/A return cpu; 5672623SN/A} 5682623SN/A 5692623SN/AREGISTER_SIM_OBJECT("TimingSimpleCPU", TimingSimpleCPU) 5702623SN/A 571