timing.cc revision 13652
12623SN/A/* 210596Sgabeblack@google.com * Copyright 2014 Google, Inc. 312276Sanouk.vanlaer@arm.com * Copyright (c) 2010-2013,2015,2017 ARM Limited 47725SAli.Saidi@ARM.com * All rights reserved 57725SAli.Saidi@ARM.com * 67725SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall 77725SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 87725SAli.Saidi@ARM.com * property including but not limited to intellectual property relating 97725SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software 107725SAli.Saidi@ARM.com * licensed hereunder. You may use the software subject to the license 117725SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated 127725SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software, 137725SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form. 147725SAli.Saidi@ARM.com * 152623SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 162623SN/A * All rights reserved. 172623SN/A * 182623SN/A * Redistribution and use in source and binary forms, with or without 192623SN/A * modification, are permitted provided that the following conditions are 202623SN/A * met: redistributions of source code must retain the above copyright 212623SN/A * notice, this list of conditions and the following disclaimer; 222623SN/A * redistributions in binary form must reproduce the above copyright 232623SN/A * notice, this list of conditions and the following disclaimer in the 242623SN/A * documentation and/or other materials provided with the distribution; 252623SN/A * neither the name of the copyright holders nor the names of its 262623SN/A * contributors may be used to endorse or promote products derived from 272623SN/A * this software without specific prior written permission. 282623SN/A * 292623SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 302623SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 312623SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 322623SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 332623SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 342623SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 352623SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 362623SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 372623SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 382623SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 392623SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402665Ssaidi@eecs.umich.edu * 412665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 422623SN/A */ 432623SN/A 4411793Sbrandon.potter@amd.com#include "cpu/simple/timing.hh" 4511793Sbrandon.potter@amd.com 463170Sstever@eecs.umich.edu#include "arch/locked_mem.hh" 478105Sgblack@eecs.umich.edu#include "arch/mmapped_ipr.hh" 482623SN/A#include "arch/utility.hh" 496658Snate@binkert.org#include "config/the_isa.hh" 502623SN/A#include "cpu/exetrace.hh" 518232Snate@binkert.org#include "debug/Config.hh" 529152Satgutier@umich.edu#include "debug/Drain.hh" 538232Snate@binkert.org#include "debug/ExecFaulting.hh" 5411793Sbrandon.potter@amd.com#include "debug/Mwait.hh" 558232Snate@binkert.org#include "debug/SimpleCPU.hh" 563348Sbinkertn@umich.edu#include "mem/packet.hh" 573348Sbinkertn@umich.edu#include "mem/packet_access.hh" 584762Snate@binkert.org#include "params/TimingSimpleCPU.hh" 597678Sgblack@eecs.umich.edu#include "sim/faults.hh" 608779Sgblack@eecs.umich.edu#include "sim/full_system.hh" 612901Ssaidi@eecs.umich.edu#include "sim/system.hh" 622623SN/A 632623SN/Ausing namespace std; 642623SN/Ausing namespace TheISA; 652623SN/A 662623SN/Avoid 672623SN/ATimingSimpleCPU::init() 682623SN/A{ 6911147Smitch.hayenga@arm.com BaseSimpleCPU::init(); 702623SN/A} 712623SN/A 722623SN/Avoid 738707Sandreas.hansson@arm.comTimingSimpleCPU::TimingCPUPort::TickEvent::schedule(PacketPtr _pkt, Tick t) 742948Ssaidi@eecs.umich.edu{ 752948Ssaidi@eecs.umich.edu pkt = _pkt; 765606Snate@binkert.org cpu->schedule(this, t); 772948Ssaidi@eecs.umich.edu} 782948Ssaidi@eecs.umich.edu 795529Snate@binkert.orgTimingSimpleCPU::TimingSimpleCPU(TimingSimpleCPUParams *p) 808707Sandreas.hansson@arm.com : BaseSimpleCPU(p), fetchTranslation(this), icachePort(this), 819179Sandreas.hansson@arm.com dcachePort(this), ifetch_pkt(NULL), dcache_pkt(NULL), previousCycle(0), 8212085Sspwilson2@wisc.edu fetchEvent([this]{ fetch(); }, name()) 832623SN/A{ 842623SN/A _status = Idle; 852623SN/A} 862623SN/A 872623SN/A 8810030SAli.Saidi@ARM.com 892623SN/ATimingSimpleCPU::~TimingSimpleCPU() 902623SN/A{ 912623SN/A} 922623SN/A 9310913Sandreas.sandberg@arm.comDrainState 9410913Sandreas.sandberg@arm.comTimingSimpleCPU::drain() 952798Sktlim@umich.edu{ 9612276Sanouk.vanlaer@arm.com // Deschedule any power gating event (if any) 9712276Sanouk.vanlaer@arm.com deschedulePowerGatingEvent(); 9812276Sanouk.vanlaer@arm.com 999448SAndreas.Sandberg@ARM.com if (switchedOut()) 10010913Sandreas.sandberg@arm.com return DrainState::Drained; 1019448SAndreas.Sandberg@ARM.com 1029342SAndreas.Sandberg@arm.com if (_status == Idle || 1039448SAndreas.Sandberg@ARM.com (_status == BaseSimpleCPU::Running && isDrained())) { 1049442SAndreas.Sandberg@ARM.com DPRINTF(Drain, "No need to drain.\n"); 10511147Smitch.hayenga@arm.com activeThreads.clear(); 10610913Sandreas.sandberg@arm.com return DrainState::Drained; 1072798Sktlim@umich.edu } else { 10811147Smitch.hayenga@arm.com DPRINTF(Drain, "Requesting drain.\n"); 1099442SAndreas.Sandberg@ARM.com 1109442SAndreas.Sandberg@ARM.com // The fetch event can become descheduled if a drain didn't 1119442SAndreas.Sandberg@ARM.com // succeed on the first attempt. We need to reschedule it if 1129442SAndreas.Sandberg@ARM.com // the CPU is waiting for a microcode routine to complete. 1139448SAndreas.Sandberg@ARM.com if (_status == BaseSimpleCPU::Running && !fetchEvent.scheduled()) 1149648Sdam.sunwoo@arm.com schedule(fetchEvent, clockEdge()); 1159442SAndreas.Sandberg@ARM.com 11610913Sandreas.sandberg@arm.com return DrainState::Draining; 1172798Sktlim@umich.edu } 1182623SN/A} 1192623SN/A 1202623SN/Avoid 1219342SAndreas.Sandberg@arm.comTimingSimpleCPU::drainResume() 1222623SN/A{ 1239442SAndreas.Sandberg@ARM.com assert(!fetchEvent.scheduled()); 1249448SAndreas.Sandberg@ARM.com if (switchedOut()) 1259448SAndreas.Sandberg@ARM.com return; 1269442SAndreas.Sandberg@ARM.com 1275221Ssaidi@eecs.umich.edu DPRINTF(SimpleCPU, "Resume\n"); 1289523SAndreas.Sandberg@ARM.com verifyMemoryMode(); 1293201Shsul@eecs.umich.edu 1309448SAndreas.Sandberg@ARM.com assert(!threadContexts.empty()); 1319448SAndreas.Sandberg@ARM.com 13211147Smitch.hayenga@arm.com _status = BaseSimpleCPU::Idle; 13311147Smitch.hayenga@arm.com 13411147Smitch.hayenga@arm.com for (ThreadID tid = 0; tid < numThreads; tid++) { 13511147Smitch.hayenga@arm.com if (threadInfo[tid]->thread->status() == ThreadContext::Active) { 13611147Smitch.hayenga@arm.com threadInfo[tid]->notIdleFraction = 1; 13711147Smitch.hayenga@arm.com 13811147Smitch.hayenga@arm.com activeThreads.push_back(tid); 13911147Smitch.hayenga@arm.com 14011147Smitch.hayenga@arm.com _status = BaseSimpleCPU::Running; 14111147Smitch.hayenga@arm.com 14211147Smitch.hayenga@arm.com // Fetch if any threads active 14311147Smitch.hayenga@arm.com if (!fetchEvent.scheduled()) { 14411147Smitch.hayenga@arm.com schedule(fetchEvent, nextCycle()); 14511147Smitch.hayenga@arm.com } 14611147Smitch.hayenga@arm.com } else { 14711147Smitch.hayenga@arm.com threadInfo[tid]->notIdleFraction = 0; 14811147Smitch.hayenga@arm.com } 1492623SN/A } 15011147Smitch.hayenga@arm.com 15112276Sanouk.vanlaer@arm.com // Reschedule any power gating event (if any) 15212276Sanouk.vanlaer@arm.com schedulePowerGatingEvent(); 15312276Sanouk.vanlaer@arm.com 15411147Smitch.hayenga@arm.com system->totalNumInsts = 0; 1559442SAndreas.Sandberg@ARM.com} 1562798Sktlim@umich.edu 1579442SAndreas.Sandberg@ARM.combool 1589442SAndreas.Sandberg@ARM.comTimingSimpleCPU::tryCompleteDrain() 1599442SAndreas.Sandberg@ARM.com{ 16010913Sandreas.sandberg@arm.com if (drainState() != DrainState::Draining) 1619442SAndreas.Sandberg@ARM.com return false; 1629442SAndreas.Sandberg@ARM.com 16311147Smitch.hayenga@arm.com DPRINTF(Drain, "tryCompleteDrain.\n"); 1649442SAndreas.Sandberg@ARM.com if (!isDrained()) 1659442SAndreas.Sandberg@ARM.com return false; 1669442SAndreas.Sandberg@ARM.com 1679442SAndreas.Sandberg@ARM.com DPRINTF(Drain, "CPU done draining, processing drain event\n"); 16810913Sandreas.sandberg@arm.com signalDrainDone(); 1699442SAndreas.Sandberg@ARM.com 1709442SAndreas.Sandberg@ARM.com return true; 1712798Sktlim@umich.edu} 1722798Sktlim@umich.edu 1732798Sktlim@umich.eduvoid 1742798Sktlim@umich.eduTimingSimpleCPU::switchOut() 1752798Sktlim@umich.edu{ 17611147Smitch.hayenga@arm.com SimpleExecContext& t_info = *threadInfo[curThread]; 17711147Smitch.hayenga@arm.com M5_VAR_USED SimpleThread* thread = t_info.thread; 17811147Smitch.hayenga@arm.com 1799429SAndreas.Sandberg@ARM.com BaseSimpleCPU::switchOut(); 1809429SAndreas.Sandberg@ARM.com 1819442SAndreas.Sandberg@ARM.com assert(!fetchEvent.scheduled()); 1829342SAndreas.Sandberg@arm.com assert(_status == BaseSimpleCPU::Running || _status == Idle); 18311147Smitch.hayenga@arm.com assert(!t_info.stayAtPC); 18411147Smitch.hayenga@arm.com assert(thread->microPC() == 0); 1859442SAndreas.Sandberg@ARM.com 18610464SAndreas.Sandberg@ARM.com updateCycleCounts(); 18712284Sjose.marinho@arm.com updateCycleCounters(BaseCPU::CPU_STATE_ON); 1882623SN/A} 1892623SN/A 1902623SN/A 1912623SN/Avoid 1922623SN/ATimingSimpleCPU::takeOverFrom(BaseCPU *oldCPU) 1932623SN/A{ 1949429SAndreas.Sandberg@ARM.com BaseSimpleCPU::takeOverFrom(oldCPU); 1952623SN/A 1969179Sandreas.hansson@arm.com previousCycle = curCycle(); 1972623SN/A} 1982623SN/A 1999523SAndreas.Sandberg@ARM.comvoid 2009523SAndreas.Sandberg@ARM.comTimingSimpleCPU::verifyMemoryMode() const 2019523SAndreas.Sandberg@ARM.com{ 2029524SAndreas.Sandberg@ARM.com if (!system->isTimingMode()) { 2039523SAndreas.Sandberg@ARM.com fatal("The timing CPU requires the memory system to be in " 2049523SAndreas.Sandberg@ARM.com "'timing' mode.\n"); 2059523SAndreas.Sandberg@ARM.com } 2069523SAndreas.Sandberg@ARM.com} 2072623SN/A 2082623SN/Avoid 20910407Smitch.hayenga@arm.comTimingSimpleCPU::activateContext(ThreadID thread_num) 2102623SN/A{ 21110407Smitch.hayenga@arm.com DPRINTF(SimpleCPU, "ActivateContext %d\n", thread_num); 2125221Ssaidi@eecs.umich.edu 21311147Smitch.hayenga@arm.com assert(thread_num < numThreads); 2142623SN/A 21511147Smitch.hayenga@arm.com threadInfo[thread_num]->notIdleFraction = 1; 21611147Smitch.hayenga@arm.com if (_status == BaseSimpleCPU::Idle) 21711147Smitch.hayenga@arm.com _status = BaseSimpleCPU::Running; 2183686Sktlim@umich.edu 2192623SN/A // kick things off by initiating the fetch of the next instruction 22011147Smitch.hayenga@arm.com if (!fetchEvent.scheduled()) 22111147Smitch.hayenga@arm.com schedule(fetchEvent, clockEdge(Cycles(0))); 22211147Smitch.hayenga@arm.com 22311147Smitch.hayenga@arm.com if (std::find(activeThreads.begin(), activeThreads.end(), thread_num) 22411147Smitch.hayenga@arm.com == activeThreads.end()) { 22511147Smitch.hayenga@arm.com activeThreads.push_back(thread_num); 22611147Smitch.hayenga@arm.com } 22711526Sdavid.guillen@arm.com 22811526Sdavid.guillen@arm.com BaseCPU::activateContext(thread_num); 2292623SN/A} 2302623SN/A 2312623SN/A 2322623SN/Avoid 2338737Skoansin.tan@gmail.comTimingSimpleCPU::suspendContext(ThreadID thread_num) 2342623SN/A{ 2355221Ssaidi@eecs.umich.edu DPRINTF(SimpleCPU, "SuspendContext %d\n", thread_num); 2365221Ssaidi@eecs.umich.edu 23711147Smitch.hayenga@arm.com assert(thread_num < numThreads); 23811147Smitch.hayenga@arm.com activeThreads.remove(thread_num); 2392623SN/A 2406043Sgblack@eecs.umich.edu if (_status == Idle) 2416043Sgblack@eecs.umich.edu return; 2426043Sgblack@eecs.umich.edu 2439342SAndreas.Sandberg@arm.com assert(_status == BaseSimpleCPU::Running); 2442623SN/A 24511147Smitch.hayenga@arm.com threadInfo[thread_num]->notIdleFraction = 0; 2462623SN/A 24711147Smitch.hayenga@arm.com if (activeThreads.empty()) { 24811147Smitch.hayenga@arm.com _status = Idle; 24911147Smitch.hayenga@arm.com 25011147Smitch.hayenga@arm.com if (fetchEvent.scheduled()) { 25111147Smitch.hayenga@arm.com deschedule(fetchEvent); 25211147Smitch.hayenga@arm.com } 25311147Smitch.hayenga@arm.com } 25411526Sdavid.guillen@arm.com 25511526Sdavid.guillen@arm.com BaseCPU::suspendContext(thread_num); 2562623SN/A} 2572623SN/A 2585728Sgblack@eecs.umich.edubool 2595728Sgblack@eecs.umich.eduTimingSimpleCPU::handleReadPacket(PacketPtr pkt) 2605728Sgblack@eecs.umich.edu{ 26111147Smitch.hayenga@arm.com SimpleExecContext &t_info = *threadInfo[curThread]; 26211147Smitch.hayenga@arm.com SimpleThread* thread = t_info.thread; 26311147Smitch.hayenga@arm.com 26412749Sgiacomo.travaglini@arm.com const RequestPtr &req = pkt->req; 26510533Sali.saidi@arm.com 26610533Sali.saidi@arm.com // We're about the issues a locked load, so tell the monitor 26710533Sali.saidi@arm.com // to start caring about this address 26810533Sali.saidi@arm.com if (pkt->isRead() && pkt->req->isLLSC()) { 26910533Sali.saidi@arm.com TheISA::handleLockedRead(thread, pkt->req); 27010533Sali.saidi@arm.com } 2718105Sgblack@eecs.umich.edu if (req->isMmappedIpr()) { 2729180Sandreas.hansson@arm.com Cycles delay = TheISA::handleIprRead(thread->getTC(), pkt); 2739179Sandreas.hansson@arm.com new IprEvent(pkt, this, clockEdge(delay)); 2745728Sgblack@eecs.umich.edu _status = DcacheWaitResponse; 2755728Sgblack@eecs.umich.edu dcache_pkt = NULL; 2768975Sandreas.hansson@arm.com } else if (!dcachePort.sendTimingReq(pkt)) { 2775728Sgblack@eecs.umich.edu _status = DcacheRetry; 2785728Sgblack@eecs.umich.edu dcache_pkt = pkt; 2795728Sgblack@eecs.umich.edu } else { 2805728Sgblack@eecs.umich.edu _status = DcacheWaitResponse; 2815728Sgblack@eecs.umich.edu // memory system takes ownership of packet 2825728Sgblack@eecs.umich.edu dcache_pkt = NULL; 2835728Sgblack@eecs.umich.edu } 2845728Sgblack@eecs.umich.edu return dcache_pkt == NULL; 2855728Sgblack@eecs.umich.edu} 2862623SN/A 2875894Sgblack@eecs.umich.eduvoid 28812749Sgiacomo.travaglini@arm.comTimingSimpleCPU::sendData(const RequestPtr &req, uint8_t *data, uint64_t *res, 2896973Stjones1@inf.ed.ac.uk bool read) 2905744Sgblack@eecs.umich.edu{ 29111147Smitch.hayenga@arm.com SimpleExecContext &t_info = *threadInfo[curThread]; 29211147Smitch.hayenga@arm.com SimpleThread* thread = t_info.thread; 29311147Smitch.hayenga@arm.com 29410653Sandreas.hansson@arm.com PacketPtr pkt = buildPacket(req, read); 29510566Sandreas.hansson@arm.com pkt->dataDynamic<uint8_t>(data); 29613652Sqtt2@cornell.edu 2975894Sgblack@eecs.umich.edu if (req->getFlags().isSet(Request::NO_ACCESS)) { 2985894Sgblack@eecs.umich.edu assert(!dcache_pkt); 2995894Sgblack@eecs.umich.edu pkt->makeResponse(); 3005894Sgblack@eecs.umich.edu completeDataAccess(pkt); 3015894Sgblack@eecs.umich.edu } else if (read) { 3025894Sgblack@eecs.umich.edu handleReadPacket(pkt); 3035894Sgblack@eecs.umich.edu } else { 3045894Sgblack@eecs.umich.edu bool do_access = true; // flag to suppress cache access 3055894Sgblack@eecs.umich.edu 3066102Sgblack@eecs.umich.edu if (req->isLLSC()) { 30710030SAli.Saidi@ARM.com do_access = TheISA::handleLockedWrite(thread, req, dcachePort.cacheBlockMask); 3085894Sgblack@eecs.umich.edu } else if (req->isCondSwap()) { 3095894Sgblack@eecs.umich.edu assert(res); 3105894Sgblack@eecs.umich.edu req->setExtraData(*res); 3115894Sgblack@eecs.umich.edu } 3125894Sgblack@eecs.umich.edu 3135894Sgblack@eecs.umich.edu if (do_access) { 3145894Sgblack@eecs.umich.edu dcache_pkt = pkt; 3155894Sgblack@eecs.umich.edu handleWritePacket(); 31611148Smitch.hayenga@arm.com threadSnoop(pkt, curThread); 3175894Sgblack@eecs.umich.edu } else { 3185894Sgblack@eecs.umich.edu _status = DcacheWaitResponse; 3195894Sgblack@eecs.umich.edu completeDataAccess(pkt); 3205894Sgblack@eecs.umich.edu } 3215894Sgblack@eecs.umich.edu } 3225894Sgblack@eecs.umich.edu} 3235894Sgblack@eecs.umich.edu 3245894Sgblack@eecs.umich.eduvoid 32512749Sgiacomo.travaglini@arm.comTimingSimpleCPU::sendSplitData(const RequestPtr &req1, const RequestPtr &req2, 32612749Sgiacomo.travaglini@arm.com const RequestPtr &req, uint8_t *data, bool read) 3275894Sgblack@eecs.umich.edu{ 3285894Sgblack@eecs.umich.edu PacketPtr pkt1, pkt2; 3295894Sgblack@eecs.umich.edu buildSplitPacket(pkt1, pkt2, req1, req2, req, data, read); 3305894Sgblack@eecs.umich.edu if (req->getFlags().isSet(Request::NO_ACCESS)) { 3315894Sgblack@eecs.umich.edu assert(!dcache_pkt); 3325894Sgblack@eecs.umich.edu pkt1->makeResponse(); 3335894Sgblack@eecs.umich.edu completeDataAccess(pkt1); 3345894Sgblack@eecs.umich.edu } else if (read) { 3357911Shestness@cs.utexas.edu SplitFragmentSenderState * send_state = 3367911Shestness@cs.utexas.edu dynamic_cast<SplitFragmentSenderState *>(pkt1->senderState); 3375894Sgblack@eecs.umich.edu if (handleReadPacket(pkt1)) { 3385894Sgblack@eecs.umich.edu send_state->clearFromParent(); 3397911Shestness@cs.utexas.edu send_state = dynamic_cast<SplitFragmentSenderState *>( 3407911Shestness@cs.utexas.edu pkt2->senderState); 3415894Sgblack@eecs.umich.edu if (handleReadPacket(pkt2)) { 3425894Sgblack@eecs.umich.edu send_state->clearFromParent(); 3435894Sgblack@eecs.umich.edu } 3445894Sgblack@eecs.umich.edu } 3455894Sgblack@eecs.umich.edu } else { 3465894Sgblack@eecs.umich.edu dcache_pkt = pkt1; 3477911Shestness@cs.utexas.edu SplitFragmentSenderState * send_state = 3487911Shestness@cs.utexas.edu dynamic_cast<SplitFragmentSenderState *>(pkt1->senderState); 3495894Sgblack@eecs.umich.edu if (handleWritePacket()) { 3505894Sgblack@eecs.umich.edu send_state->clearFromParent(); 3515894Sgblack@eecs.umich.edu dcache_pkt = pkt2; 3527911Shestness@cs.utexas.edu send_state = dynamic_cast<SplitFragmentSenderState *>( 3537911Shestness@cs.utexas.edu pkt2->senderState); 3545894Sgblack@eecs.umich.edu if (handleWritePacket()) { 3555894Sgblack@eecs.umich.edu send_state->clearFromParent(); 3565894Sgblack@eecs.umich.edu } 3575894Sgblack@eecs.umich.edu } 3585894Sgblack@eecs.umich.edu } 3595894Sgblack@eecs.umich.edu} 3605894Sgblack@eecs.umich.edu 3615894Sgblack@eecs.umich.eduvoid 36210379Sandreas.hansson@arm.comTimingSimpleCPU::translationFault(const Fault &fault) 3635894Sgblack@eecs.umich.edu{ 3646739Sgblack@eecs.umich.edu // fault may be NoFault in cases where a fault is suppressed, 3656739Sgblack@eecs.umich.edu // for instance prefetches. 36610464SAndreas.Sandberg@ARM.com updateCycleCounts(); 36712284Sjose.marinho@arm.com updateCycleCounters(BaseCPU::CPU_STATE_ON); 3685894Sgblack@eecs.umich.edu 3695894Sgblack@eecs.umich.edu if (traceData) { 3705894Sgblack@eecs.umich.edu // Since there was a fault, we shouldn't trace this instruction. 3715894Sgblack@eecs.umich.edu delete traceData; 3725894Sgblack@eecs.umich.edu traceData = NULL; 3735744Sgblack@eecs.umich.edu } 3745744Sgblack@eecs.umich.edu 3755894Sgblack@eecs.umich.edu postExecute(); 3765894Sgblack@eecs.umich.edu 3779442SAndreas.Sandberg@ARM.com advanceInst(fault); 3785894Sgblack@eecs.umich.edu} 3795894Sgblack@eecs.umich.edu 38010653Sandreas.hansson@arm.comPacketPtr 38112749Sgiacomo.travaglini@arm.comTimingSimpleCPU::buildPacket(const RequestPtr &req, bool read) 3825894Sgblack@eecs.umich.edu{ 38310653Sandreas.hansson@arm.com return read ? Packet::createRead(req) : Packet::createWrite(req); 3845894Sgblack@eecs.umich.edu} 3855894Sgblack@eecs.umich.edu 3865894Sgblack@eecs.umich.eduvoid 3875894Sgblack@eecs.umich.eduTimingSimpleCPU::buildSplitPacket(PacketPtr &pkt1, PacketPtr &pkt2, 38812749Sgiacomo.travaglini@arm.com const RequestPtr &req1, const RequestPtr &req2, const RequestPtr &req, 3895894Sgblack@eecs.umich.edu uint8_t *data, bool read) 3905894Sgblack@eecs.umich.edu{ 3915894Sgblack@eecs.umich.edu pkt1 = pkt2 = NULL; 3925894Sgblack@eecs.umich.edu 3938105Sgblack@eecs.umich.edu assert(!req1->isMmappedIpr() && !req2->isMmappedIpr()); 3945744Sgblack@eecs.umich.edu 3955894Sgblack@eecs.umich.edu if (req->getFlags().isSet(Request::NO_ACCESS)) { 39610653Sandreas.hansson@arm.com pkt1 = buildPacket(req, read); 3975894Sgblack@eecs.umich.edu return; 3985894Sgblack@eecs.umich.edu } 3995894Sgblack@eecs.umich.edu 40010653Sandreas.hansson@arm.com pkt1 = buildPacket(req1, read); 40110653Sandreas.hansson@arm.com pkt2 = buildPacket(req2, read); 4025894Sgblack@eecs.umich.edu 4038949Sandreas.hansson@arm.com PacketPtr pkt = new Packet(req, pkt1->cmd.responseCommand()); 4045744Sgblack@eecs.umich.edu 40510566Sandreas.hansson@arm.com pkt->dataDynamic<uint8_t>(data); 4065744Sgblack@eecs.umich.edu pkt1->dataStatic<uint8_t>(data); 4075744Sgblack@eecs.umich.edu pkt2->dataStatic<uint8_t>(data + req1->getSize()); 4085744Sgblack@eecs.umich.edu 4095744Sgblack@eecs.umich.edu SplitMainSenderState * main_send_state = new SplitMainSenderState; 4105744Sgblack@eecs.umich.edu pkt->senderState = main_send_state; 4115744Sgblack@eecs.umich.edu main_send_state->fragments[0] = pkt1; 4125744Sgblack@eecs.umich.edu main_send_state->fragments[1] = pkt2; 4135744Sgblack@eecs.umich.edu main_send_state->outstanding = 2; 4145744Sgblack@eecs.umich.edu pkt1->senderState = new SplitFragmentSenderState(pkt, 0); 4155744Sgblack@eecs.umich.edu pkt2->senderState = new SplitFragmentSenderState(pkt, 1); 4165744Sgblack@eecs.umich.edu} 4175744Sgblack@eecs.umich.edu 4182623SN/AFault 41911608Snikos.nikoleris@arm.comTimingSimpleCPU::initiateMemRead(Addr addr, unsigned size, 42011608Snikos.nikoleris@arm.com Request::Flags flags) 42111303Ssteve.reinhardt@amd.com{ 42211147Smitch.hayenga@arm.com SimpleExecContext &t_info = *threadInfo[curThread]; 42311147Smitch.hayenga@arm.com SimpleThread* thread = t_info.thread; 42411147Smitch.hayenga@arm.com 4255728Sgblack@eecs.umich.edu Fault fault; 4265728Sgblack@eecs.umich.edu const int asid = 0; 4277720Sgblack@eecs.umich.edu const Addr pc = thread->instAddr(); 4289814Sandreas.hansson@arm.com unsigned block_size = cacheLineSize(); 4296973Stjones1@inf.ed.ac.uk BaseTLB::Mode mode = BaseTLB::Read; 4302623SN/A 43110665SAli.Saidi@ARM.com if (traceData) 43210665SAli.Saidi@ARM.com traceData->setMem(addr, size, flags); 4337045Ssteve.reinhardt@amd.com 43412749Sgiacomo.travaglini@arm.com RequestPtr req = std::make_shared<Request>( 43512749Sgiacomo.travaglini@arm.com asid, addr, size, flags, dataMasterId(), pc, 43612749Sgiacomo.travaglini@arm.com thread->contextId()); 4375728Sgblack@eecs.umich.edu 43810024Sdam.sunwoo@arm.com req->taskId(taskId()); 43910024Sdam.sunwoo@arm.com 4407520Sgblack@eecs.umich.edu Addr split_addr = roundDown(addr + size - 1, block_size); 4415744Sgblack@eecs.umich.edu assert(split_addr <= addr || split_addr - addr < block_size); 4425728Sgblack@eecs.umich.edu 4435894Sgblack@eecs.umich.edu _status = DTBWaitResponse; 4445744Sgblack@eecs.umich.edu if (split_addr > addr) { 4455894Sgblack@eecs.umich.edu RequestPtr req1, req2; 4466102Sgblack@eecs.umich.edu assert(!req->isLLSC() && !req->isSwap()); 4475894Sgblack@eecs.umich.edu req->splitOnVaddr(split_addr, req1, req2); 4485894Sgblack@eecs.umich.edu 4496973Stjones1@inf.ed.ac.uk WholeTranslationState *state = 4507520Sgblack@eecs.umich.edu new WholeTranslationState(req, req1, req2, new uint8_t[size], 4516973Stjones1@inf.ed.ac.uk NULL, mode); 4528486Sgblack@eecs.umich.edu DataTranslation<TimingSimpleCPU *> *trans1 = 4538486Sgblack@eecs.umich.edu new DataTranslation<TimingSimpleCPU *>(this, state, 0); 4548486Sgblack@eecs.umich.edu DataTranslation<TimingSimpleCPU *> *trans2 = 4558486Sgblack@eecs.umich.edu new DataTranslation<TimingSimpleCPU *>(this, state, 1); 4566973Stjones1@inf.ed.ac.uk 45711147Smitch.hayenga@arm.com thread->dtb->translateTiming(req1, thread->getTC(), trans1, mode); 45811147Smitch.hayenga@arm.com thread->dtb->translateTiming(req2, thread->getTC(), trans2, mode); 4595744Sgblack@eecs.umich.edu } else { 4606973Stjones1@inf.ed.ac.uk WholeTranslationState *state = 4617520Sgblack@eecs.umich.edu new WholeTranslationState(req, new uint8_t[size], NULL, mode); 4628486Sgblack@eecs.umich.edu DataTranslation<TimingSimpleCPU *> *translation 4638486Sgblack@eecs.umich.edu = new DataTranslation<TimingSimpleCPU *>(this, state); 46411147Smitch.hayenga@arm.com thread->dtb->translateTiming(req, thread->getTC(), translation, mode); 4652623SN/A } 4662623SN/A 4675728Sgblack@eecs.umich.edu return NoFault; 4682623SN/A} 4692623SN/A 4705728Sgblack@eecs.umich.edubool 4715728Sgblack@eecs.umich.eduTimingSimpleCPU::handleWritePacket() 4725728Sgblack@eecs.umich.edu{ 47311147Smitch.hayenga@arm.com SimpleExecContext &t_info = *threadInfo[curThread]; 47411147Smitch.hayenga@arm.com SimpleThread* thread = t_info.thread; 47511147Smitch.hayenga@arm.com 47612749Sgiacomo.travaglini@arm.com const RequestPtr &req = dcache_pkt->req; 4778105Sgblack@eecs.umich.edu if (req->isMmappedIpr()) { 4789180Sandreas.hansson@arm.com Cycles delay = TheISA::handleIprWrite(thread->getTC(), dcache_pkt); 4799179Sandreas.hansson@arm.com new IprEvent(dcache_pkt, this, clockEdge(delay)); 4805728Sgblack@eecs.umich.edu _status = DcacheWaitResponse; 4815728Sgblack@eecs.umich.edu dcache_pkt = NULL; 4828975Sandreas.hansson@arm.com } else if (!dcachePort.sendTimingReq(dcache_pkt)) { 4835728Sgblack@eecs.umich.edu _status = DcacheRetry; 4845728Sgblack@eecs.umich.edu } else { 4855728Sgblack@eecs.umich.edu _status = DcacheWaitResponse; 4865728Sgblack@eecs.umich.edu // memory system takes ownership of packet 4875728Sgblack@eecs.umich.edu dcache_pkt = NULL; 4885728Sgblack@eecs.umich.edu } 4895728Sgblack@eecs.umich.edu return dcache_pkt == NULL; 4905728Sgblack@eecs.umich.edu} 4912623SN/A 4922623SN/AFault 4938444Sgblack@eecs.umich.eduTimingSimpleCPU::writeMem(uint8_t *data, unsigned size, 49411608Snikos.nikoleris@arm.com Addr addr, Request::Flags flags, uint64_t *res) 4952623SN/A{ 49611147Smitch.hayenga@arm.com SimpleExecContext &t_info = *threadInfo[curThread]; 49711147Smitch.hayenga@arm.com SimpleThread* thread = t_info.thread; 49811147Smitch.hayenga@arm.com 4998443Sgblack@eecs.umich.edu uint8_t *newData = new uint8_t[size]; 5005728Sgblack@eecs.umich.edu const int asid = 0; 5017720Sgblack@eecs.umich.edu const Addr pc = thread->instAddr(); 5029814Sandreas.hansson@arm.com unsigned block_size = cacheLineSize(); 5036973Stjones1@inf.ed.ac.uk BaseTLB::Mode mode = BaseTLB::Write; 5043169Sstever@eecs.umich.edu 50510031SAli.Saidi@ARM.com if (data == NULL) { 50612355Snikos.nikoleris@arm.com assert(flags & Request::STORE_NO_DATA); 50710031SAli.Saidi@ARM.com // This must be a cache block cleaning request 50810031SAli.Saidi@ARM.com memset(newData, 0, size); 50910031SAli.Saidi@ARM.com } else { 51010031SAli.Saidi@ARM.com memcpy(newData, data, size); 51110031SAli.Saidi@ARM.com } 51210031SAli.Saidi@ARM.com 51310665SAli.Saidi@ARM.com if (traceData) 51410665SAli.Saidi@ARM.com traceData->setMem(addr, size, flags); 5157045Ssteve.reinhardt@amd.com 51612749Sgiacomo.travaglini@arm.com RequestPtr req = std::make_shared<Request>( 51712749Sgiacomo.travaglini@arm.com asid, addr, size, flags, dataMasterId(), pc, 51812749Sgiacomo.travaglini@arm.com thread->contextId()); 5195728Sgblack@eecs.umich.edu 52010024Sdam.sunwoo@arm.com req->taskId(taskId()); 52110024Sdam.sunwoo@arm.com 5227520Sgblack@eecs.umich.edu Addr split_addr = roundDown(addr + size - 1, block_size); 5235744Sgblack@eecs.umich.edu assert(split_addr <= addr || split_addr - addr < block_size); 5245728Sgblack@eecs.umich.edu 5255894Sgblack@eecs.umich.edu _status = DTBWaitResponse; 5265744Sgblack@eecs.umich.edu if (split_addr > addr) { 5275894Sgblack@eecs.umich.edu RequestPtr req1, req2; 5286102Sgblack@eecs.umich.edu assert(!req->isLLSC() && !req->isSwap()); 5295894Sgblack@eecs.umich.edu req->splitOnVaddr(split_addr, req1, req2); 5305894Sgblack@eecs.umich.edu 5316973Stjones1@inf.ed.ac.uk WholeTranslationState *state = 5328443Sgblack@eecs.umich.edu new WholeTranslationState(req, req1, req2, newData, res, mode); 5338486Sgblack@eecs.umich.edu DataTranslation<TimingSimpleCPU *> *trans1 = 5348486Sgblack@eecs.umich.edu new DataTranslation<TimingSimpleCPU *>(this, state, 0); 5358486Sgblack@eecs.umich.edu DataTranslation<TimingSimpleCPU *> *trans2 = 5368486Sgblack@eecs.umich.edu new DataTranslation<TimingSimpleCPU *>(this, state, 1); 5376973Stjones1@inf.ed.ac.uk 53811147Smitch.hayenga@arm.com thread->dtb->translateTiming(req1, thread->getTC(), trans1, mode); 53911147Smitch.hayenga@arm.com thread->dtb->translateTiming(req2, thread->getTC(), trans2, mode); 5405744Sgblack@eecs.umich.edu } else { 5416973Stjones1@inf.ed.ac.uk WholeTranslationState *state = 5428443Sgblack@eecs.umich.edu new WholeTranslationState(req, newData, res, mode); 5438486Sgblack@eecs.umich.edu DataTranslation<TimingSimpleCPU *> *translation = 5448486Sgblack@eecs.umich.edu new DataTranslation<TimingSimpleCPU *>(this, state); 54511147Smitch.hayenga@arm.com thread->dtb->translateTiming(req, thread->getTC(), translation, mode); 5462623SN/A } 5472623SN/A 5487045Ssteve.reinhardt@amd.com // Translation faults will be returned via finishTranslation() 5495728Sgblack@eecs.umich.edu return NoFault; 5502623SN/A} 5512623SN/A 55213652Sqtt2@cornell.eduFault 55313652Sqtt2@cornell.eduTimingSimpleCPU::initiateMemAMO(Addr addr, unsigned size, 55413652Sqtt2@cornell.edu Request::Flags flags, 55513652Sqtt2@cornell.edu AtomicOpFunctor *amo_op) 55613652Sqtt2@cornell.edu{ 55713652Sqtt2@cornell.edu SimpleExecContext &t_info = *threadInfo[curThread]; 55813652Sqtt2@cornell.edu SimpleThread* thread = t_info.thread; 55913652Sqtt2@cornell.edu 56013652Sqtt2@cornell.edu Fault fault; 56113652Sqtt2@cornell.edu const int asid = 0; 56213652Sqtt2@cornell.edu const Addr pc = thread->instAddr(); 56313652Sqtt2@cornell.edu unsigned block_size = cacheLineSize(); 56413652Sqtt2@cornell.edu BaseTLB::Mode mode = BaseTLB::Write; 56513652Sqtt2@cornell.edu 56613652Sqtt2@cornell.edu if (traceData) 56713652Sqtt2@cornell.edu traceData->setMem(addr, size, flags); 56813652Sqtt2@cornell.edu 56913652Sqtt2@cornell.edu RequestPtr req = make_shared<Request>(asid, addr, size, flags, 57013652Sqtt2@cornell.edu dataMasterId(), pc, thread->contextId(), amo_op); 57113652Sqtt2@cornell.edu 57213652Sqtt2@cornell.edu assert(req->hasAtomicOpFunctor()); 57313652Sqtt2@cornell.edu 57413652Sqtt2@cornell.edu req->taskId(taskId()); 57513652Sqtt2@cornell.edu 57613652Sqtt2@cornell.edu Addr split_addr = roundDown(addr + size - 1, block_size); 57713652Sqtt2@cornell.edu 57813652Sqtt2@cornell.edu // AMO requests that access across a cache line boundary are not 57913652Sqtt2@cornell.edu // allowed since the cache does not guarantee AMO ops to be executed 58013652Sqtt2@cornell.edu // atomically in two cache lines 58113652Sqtt2@cornell.edu // For ISAs such as x86 that requires AMO operations to work on 58213652Sqtt2@cornell.edu // accesses that cross cache-line boundaries, the cache needs to be 58313652Sqtt2@cornell.edu // modified to support locking both cache lines to guarantee the 58413652Sqtt2@cornell.edu // atomicity. 58513652Sqtt2@cornell.edu if (split_addr > addr) { 58613652Sqtt2@cornell.edu panic("AMO requests should not access across a cache line boundary\n"); 58713652Sqtt2@cornell.edu } 58813652Sqtt2@cornell.edu 58913652Sqtt2@cornell.edu _status = DTBWaitResponse; 59013652Sqtt2@cornell.edu 59113652Sqtt2@cornell.edu WholeTranslationState *state = 59213652Sqtt2@cornell.edu new WholeTranslationState(req, new uint8_t[size], NULL, mode); 59313652Sqtt2@cornell.edu DataTranslation<TimingSimpleCPU *> *translation 59413652Sqtt2@cornell.edu = new DataTranslation<TimingSimpleCPU *>(this, state); 59513652Sqtt2@cornell.edu thread->dtb->translateTiming(req, thread->getTC(), translation, mode); 59613652Sqtt2@cornell.edu 59713652Sqtt2@cornell.edu return NoFault; 59813652Sqtt2@cornell.edu} 59913652Sqtt2@cornell.edu 60011148Smitch.hayenga@arm.comvoid 60111148Smitch.hayenga@arm.comTimingSimpleCPU::threadSnoop(PacketPtr pkt, ThreadID sender) 60211148Smitch.hayenga@arm.com{ 60311148Smitch.hayenga@arm.com for (ThreadID tid = 0; tid < numThreads; tid++) { 60411148Smitch.hayenga@arm.com if (tid != sender) { 60511321Ssteve.reinhardt@amd.com if (getCpuAddrMonitor(tid)->doMonitor(pkt)) { 60611151Smitch.hayenga@arm.com wakeup(tid); 60711148Smitch.hayenga@arm.com } 60811148Smitch.hayenga@arm.com TheISA::handleLockedSnoop(threadInfo[tid]->thread, pkt, 60911148Smitch.hayenga@arm.com dcachePort.cacheBlockMask); 61011148Smitch.hayenga@arm.com } 61111148Smitch.hayenga@arm.com } 61211148Smitch.hayenga@arm.com} 6132623SN/A 6142623SN/Avoid 6156973Stjones1@inf.ed.ac.ukTimingSimpleCPU::finishTranslation(WholeTranslationState *state) 6166973Stjones1@inf.ed.ac.uk{ 6179342SAndreas.Sandberg@arm.com _status = BaseSimpleCPU::Running; 6186973Stjones1@inf.ed.ac.uk 6196973Stjones1@inf.ed.ac.uk if (state->getFault() != NoFault) { 6206973Stjones1@inf.ed.ac.uk if (state->isPrefetch()) { 6216973Stjones1@inf.ed.ac.uk state->setNoFault(); 6226973Stjones1@inf.ed.ac.uk } 6237691SAli.Saidi@ARM.com delete [] state->data; 6246973Stjones1@inf.ed.ac.uk state->deleteReqs(); 6256973Stjones1@inf.ed.ac.uk translationFault(state->getFault()); 6266973Stjones1@inf.ed.ac.uk } else { 6276973Stjones1@inf.ed.ac.uk if (!state->isSplit) { 6286973Stjones1@inf.ed.ac.uk sendData(state->mainReq, state->data, state->res, 6296973Stjones1@inf.ed.ac.uk state->mode == BaseTLB::Read); 6306973Stjones1@inf.ed.ac.uk } else { 6316973Stjones1@inf.ed.ac.uk sendSplitData(state->sreqLow, state->sreqHigh, state->mainReq, 6326973Stjones1@inf.ed.ac.uk state->data, state->mode == BaseTLB::Read); 6336973Stjones1@inf.ed.ac.uk } 6346973Stjones1@inf.ed.ac.uk } 6356973Stjones1@inf.ed.ac.uk 6366973Stjones1@inf.ed.ac.uk delete state; 6376973Stjones1@inf.ed.ac.uk} 6386973Stjones1@inf.ed.ac.uk 6396973Stjones1@inf.ed.ac.uk 6406973Stjones1@inf.ed.ac.ukvoid 6412623SN/ATimingSimpleCPU::fetch() 6422623SN/A{ 64311147Smitch.hayenga@arm.com // Change thread if multi-threaded 64411147Smitch.hayenga@arm.com swapActiveThread(); 64511147Smitch.hayenga@arm.com 64611147Smitch.hayenga@arm.com SimpleExecContext &t_info = *threadInfo[curThread]; 64711147Smitch.hayenga@arm.com SimpleThread* thread = t_info.thread; 64811147Smitch.hayenga@arm.com 6495221Ssaidi@eecs.umich.edu DPRINTF(SimpleCPU, "Fetch\n"); 6505221Ssaidi@eecs.umich.edu 65110596Sgabeblack@google.com if (!curStaticInst || !curStaticInst->isDelayedCommit()) { 6523387Sgblack@eecs.umich.edu checkForInterrupts(); 65310596Sgabeblack@google.com checkPcEventQueue(); 65410596Sgabeblack@google.com } 6555348Ssaidi@eecs.umich.edu 6568143SAli.Saidi@ARM.com // We must have just got suspended by a PC event 6578143SAli.Saidi@ARM.com if (_status == Idle) 6588143SAli.Saidi@ARM.com return; 6598143SAli.Saidi@ARM.com 6607720Sgblack@eecs.umich.edu TheISA::PCState pcState = thread->pcState(); 66111147Smitch.hayenga@arm.com bool needToFetch = !isRomMicroPC(pcState.microPC()) && 66211147Smitch.hayenga@arm.com !curMacroStaticInst; 6632623SN/A 6647720Sgblack@eecs.umich.edu if (needToFetch) { 6659342SAndreas.Sandberg@arm.com _status = BaseSimpleCPU::Running; 66612749Sgiacomo.travaglini@arm.com RequestPtr ifetch_req = std::make_shared<Request>(); 66710024Sdam.sunwoo@arm.com ifetch_req->taskId(taskId()); 66811435Smitch.hayenga@arm.com ifetch_req->setContext(thread->contextId()); 6695894Sgblack@eecs.umich.edu setupFetchRequest(ifetch_req); 6708277SAli.Saidi@ARM.com DPRINTF(SimpleCPU, "Translating address %#x\n", ifetch_req->getVaddr()); 67111147Smitch.hayenga@arm.com thread->itb->translateTiming(ifetch_req, thread->getTC(), 67211147Smitch.hayenga@arm.com &fetchTranslation, BaseTLB::Execute); 6732623SN/A } else { 6745669Sgblack@eecs.umich.edu _status = IcacheWaitResponse; 6755669Sgblack@eecs.umich.edu completeIfetch(NULL); 6765894Sgblack@eecs.umich.edu 67710464SAndreas.Sandberg@ARM.com updateCycleCounts(); 67812284Sjose.marinho@arm.com updateCycleCounters(BaseCPU::CPU_STATE_ON); 6795894Sgblack@eecs.umich.edu } 6805894Sgblack@eecs.umich.edu} 6815894Sgblack@eecs.umich.edu 6825894Sgblack@eecs.umich.edu 6835894Sgblack@eecs.umich.eduvoid 68412749Sgiacomo.travaglini@arm.comTimingSimpleCPU::sendFetch(const Fault &fault, const RequestPtr &req, 68510379Sandreas.hansson@arm.com ThreadContext *tc) 6865894Sgblack@eecs.umich.edu{ 6875894Sgblack@eecs.umich.edu if (fault == NoFault) { 6888277SAli.Saidi@ARM.com DPRINTF(SimpleCPU, "Sending fetch for addr %#x(pa: %#x)\n", 6898277SAli.Saidi@ARM.com req->getVaddr(), req->getPaddr()); 6908949Sandreas.hansson@arm.com ifetch_pkt = new Packet(req, MemCmd::ReadReq); 6915894Sgblack@eecs.umich.edu ifetch_pkt->dataStatic(&inst); 6928277SAli.Saidi@ARM.com DPRINTF(SimpleCPU, " -- pkt addr: %#x\n", ifetch_pkt->getAddr()); 6935894Sgblack@eecs.umich.edu 6948975Sandreas.hansson@arm.com if (!icachePort.sendTimingReq(ifetch_pkt)) { 6955894Sgblack@eecs.umich.edu // Need to wait for retry 6965894Sgblack@eecs.umich.edu _status = IcacheRetry; 6975894Sgblack@eecs.umich.edu } else { 6985894Sgblack@eecs.umich.edu // Need to wait for cache to respond 6995894Sgblack@eecs.umich.edu _status = IcacheWaitResponse; 7005894Sgblack@eecs.umich.edu // ownership of packet transferred to memory system 7015894Sgblack@eecs.umich.edu ifetch_pkt = NULL; 7025894Sgblack@eecs.umich.edu } 7035894Sgblack@eecs.umich.edu } else { 7048277SAli.Saidi@ARM.com DPRINTF(SimpleCPU, "Translation of addr %#x faulted\n", req->getVaddr()); 7055894Sgblack@eecs.umich.edu // fetch fault: advance directly to next instruction (fault handler) 7069342SAndreas.Sandberg@arm.com _status = BaseSimpleCPU::Running; 7075894Sgblack@eecs.umich.edu advanceInst(fault); 7082623SN/A } 7093222Sktlim@umich.edu 71010464SAndreas.Sandberg@ARM.com updateCycleCounts(); 71112284Sjose.marinho@arm.com updateCycleCounters(BaseCPU::CPU_STATE_ON); 7122623SN/A} 7132623SN/A 7142623SN/A 7152623SN/Avoid 71610379Sandreas.hansson@arm.comTimingSimpleCPU::advanceInst(const Fault &fault) 7172623SN/A{ 71811147Smitch.hayenga@arm.com SimpleExecContext &t_info = *threadInfo[curThread]; 71911147Smitch.hayenga@arm.com 7208276SAli.Saidi@ARM.com if (_status == Faulting) 7218276SAli.Saidi@ARM.com return; 7228276SAli.Saidi@ARM.com 7238276SAli.Saidi@ARM.com if (fault != NoFault) { 72412769Sqtt2@cornell.edu DPRINTF(SimpleCPU, "Fault occured. Handling the fault\n"); 72511877Sbrandon.potter@amd.com 7268276SAli.Saidi@ARM.com advancePC(fault); 72711877Sbrandon.potter@amd.com 72812769Sqtt2@cornell.edu // A syscall fault could suspend this CPU (e.g., futex_wait) 72912769Sqtt2@cornell.edu // If the _status is not Idle, schedule an event to fetch the next 73012769Sqtt2@cornell.edu // instruction after 'stall' ticks. 73112769Sqtt2@cornell.edu // If the cpu has been suspended (i.e., _status == Idle), another 73212769Sqtt2@cornell.edu // cpu will wake this cpu up later. 73312769Sqtt2@cornell.edu if (_status != Idle) { 73412769Sqtt2@cornell.edu DPRINTF(SimpleCPU, "Scheduling fetch event after the Fault\n"); 73511877Sbrandon.potter@amd.com 73612769Sqtt2@cornell.edu Tick stall = dynamic_pointer_cast<SyscallRetryFault>(fault) ? 73712769Sqtt2@cornell.edu clockEdge(syscallRetryLatency) : clockEdge(); 73812769Sqtt2@cornell.edu reschedule(fetchEvent, stall, true); 73912769Sqtt2@cornell.edu _status = Faulting; 74012769Sqtt2@cornell.edu } 74111877Sbrandon.potter@amd.com 7428276SAli.Saidi@ARM.com return; 7438276SAli.Saidi@ARM.com } 7448276SAli.Saidi@ARM.com 74511147Smitch.hayenga@arm.com if (!t_info.stayAtPC) 7465726Sgblack@eecs.umich.edu advancePC(fault); 7472623SN/A 7489442SAndreas.Sandberg@ARM.com if (tryCompleteDrain()) 74912769Sqtt2@cornell.edu return; 7509442SAndreas.Sandberg@ARM.com 7519342SAndreas.Sandberg@arm.com if (_status == BaseSimpleCPU::Running) { 7522631SN/A // kick off fetch of next instruction... callback from icache 7532631SN/A // response will cause that instruction to be executed, 7542631SN/A // keeping the CPU running. 7552631SN/A fetch(); 7562631SN/A } 7572623SN/A} 7582623SN/A 7592623SN/A 7602623SN/Avoid 7613349Sbinkertn@umich.eduTimingSimpleCPU::completeIfetch(PacketPtr pkt) 7622623SN/A{ 76311147Smitch.hayenga@arm.com SimpleExecContext& t_info = *threadInfo[curThread]; 76411147Smitch.hayenga@arm.com 7658277SAli.Saidi@ARM.com DPRINTF(SimpleCPU, "Complete ICache Fetch for addr %#x\n", pkt ? 7668277SAli.Saidi@ARM.com pkt->getAddr() : 0); 7678277SAli.Saidi@ARM.com 7682623SN/A // received a response from the icache: execute the received 7692623SN/A // instruction 7705669Sgblack@eecs.umich.edu assert(!pkt || !pkt->isError()); 7712623SN/A assert(_status == IcacheWaitResponse); 7722798Sktlim@umich.edu 7739342SAndreas.Sandberg@arm.com _status = BaseSimpleCPU::Running; 7742644Sstever@eecs.umich.edu 77510464SAndreas.Sandberg@ARM.com updateCycleCounts(); 77612284Sjose.marinho@arm.com updateCycleCounters(BaseCPU::CPU_STATE_ON); 7773222Sktlim@umich.edu 77810020Smatt.horsnell@ARM.com if (pkt) 77910020Smatt.horsnell@ARM.com pkt->req->setAccessLatency(); 78010020Smatt.horsnell@ARM.com 78110020Smatt.horsnell@ARM.com 7822623SN/A preExecute(); 7837725SAli.Saidi@ARM.com if (curStaticInst && curStaticInst->isMemRef()) { 7842623SN/A // load or store: just send to dcache 78511147Smitch.hayenga@arm.com Fault fault = curStaticInst->initiateAcc(&t_info, traceData); 7867945SAli.Saidi@ARM.com 7877945SAli.Saidi@ARM.com // If we're not running now the instruction will complete in a dcache 7887945SAli.Saidi@ARM.com // response callback or the instruction faulted and has started an 7897945SAli.Saidi@ARM.com // ifetch 7909342SAndreas.Sandberg@arm.com if (_status == BaseSimpleCPU::Running) { 7915894Sgblack@eecs.umich.edu if (fault != NoFault && traceData) { 7925001Sgblack@eecs.umich.edu // If there was a fault, we shouldn't trace this instruction. 7935001Sgblack@eecs.umich.edu delete traceData; 7945001Sgblack@eecs.umich.edu traceData = NULL; 7953170Sstever@eecs.umich.edu } 7964998Sgblack@eecs.umich.edu 7972644Sstever@eecs.umich.edu postExecute(); 7985103Ssaidi@eecs.umich.edu // @todo remove me after debugging with legion done 7995103Ssaidi@eecs.umich.edu if (curStaticInst && (!curStaticInst->isMicroop() || 8005103Ssaidi@eecs.umich.edu curStaticInst->isFirstMicroop())) 8015103Ssaidi@eecs.umich.edu instCnt++; 8022644Sstever@eecs.umich.edu advanceInst(fault); 8032644Sstever@eecs.umich.edu } 8045726Sgblack@eecs.umich.edu } else if (curStaticInst) { 8052623SN/A // non-memory instruction: execute completely now 80611147Smitch.hayenga@arm.com Fault fault = curStaticInst->execute(&t_info, traceData); 8074998Sgblack@eecs.umich.edu 8084998Sgblack@eecs.umich.edu // keep an instruction count 8094998Sgblack@eecs.umich.edu if (fault == NoFault) 8104998Sgblack@eecs.umich.edu countInst(); 8117655Sali.saidi@arm.com else if (traceData && !DTRACE(ExecFaulting)) { 8125001Sgblack@eecs.umich.edu delete traceData; 8135001Sgblack@eecs.umich.edu traceData = NULL; 8145001Sgblack@eecs.umich.edu } 8154998Sgblack@eecs.umich.edu 8162644Sstever@eecs.umich.edu postExecute(); 8175103Ssaidi@eecs.umich.edu // @todo remove me after debugging with legion done 8185103Ssaidi@eecs.umich.edu if (curStaticInst && (!curStaticInst->isMicroop() || 81911147Smitch.hayenga@arm.com curStaticInst->isFirstMicroop())) 8205103Ssaidi@eecs.umich.edu instCnt++; 8212644Sstever@eecs.umich.edu advanceInst(fault); 8225726Sgblack@eecs.umich.edu } else { 8235726Sgblack@eecs.umich.edu advanceInst(NoFault); 8242623SN/A } 8253658Sktlim@umich.edu 8265669Sgblack@eecs.umich.edu if (pkt) { 8275669Sgblack@eecs.umich.edu delete pkt; 8285669Sgblack@eecs.umich.edu } 8292623SN/A} 8302623SN/A 8312948Ssaidi@eecs.umich.eduvoid 8322948Ssaidi@eecs.umich.eduTimingSimpleCPU::IcachePort::ITickEvent::process() 8332948Ssaidi@eecs.umich.edu{ 8342948Ssaidi@eecs.umich.edu cpu->completeIfetch(pkt); 8352948Ssaidi@eecs.umich.edu} 8362623SN/A 8372623SN/Abool 8388975Sandreas.hansson@arm.comTimingSimpleCPU::IcachePort::recvTimingResp(PacketPtr pkt) 8392623SN/A{ 84010669Sandreas.hansson@arm.com DPRINTF(SimpleCPU, "Received fetch response %#x\n", pkt->getAddr()); 84110669Sandreas.hansson@arm.com // we should only ever see one response per cycle since we only 84210669Sandreas.hansson@arm.com // issue a new request once this response is sunk 84310669Sandreas.hansson@arm.com assert(!tickEvent.scheduled()); 8449165Sandreas.hansson@arm.com // delay processing of returned data until next CPU clock edge 84510669Sandreas.hansson@arm.com tickEvent.schedule(pkt, cpu->clockEdge()); 8468948Sandreas.hansson@arm.com 8474433Ssaidi@eecs.umich.edu return true; 8482623SN/A} 8492623SN/A 8502657Ssaidi@eecs.umich.eduvoid 85110713Sandreas.hansson@arm.comTimingSimpleCPU::IcachePort::recvReqRetry() 8522623SN/A{ 8532623SN/A // we shouldn't get a retry unless we have a packet that we're 8542623SN/A // waiting to transmit 8552623SN/A assert(cpu->ifetch_pkt != NULL); 8562623SN/A assert(cpu->_status == IcacheRetry); 8573349Sbinkertn@umich.edu PacketPtr tmp = cpu->ifetch_pkt; 8588975Sandreas.hansson@arm.com if (sendTimingReq(tmp)) { 8592657Ssaidi@eecs.umich.edu cpu->_status = IcacheWaitResponse; 8602657Ssaidi@eecs.umich.edu cpu->ifetch_pkt = NULL; 8612657Ssaidi@eecs.umich.edu } 8622623SN/A} 8632623SN/A 8642623SN/Avoid 8653349Sbinkertn@umich.eduTimingSimpleCPU::completeDataAccess(PacketPtr pkt) 8662623SN/A{ 8672623SN/A // received a response from the dcache: complete the load or store 8682623SN/A // instruction 8694870Sstever@eecs.umich.edu assert(!pkt->isError()); 8707516Shestness@cs.utexas.edu assert(_status == DcacheWaitResponse || _status == DTBWaitResponse || 8717516Shestness@cs.utexas.edu pkt->req->getFlags().isSet(Request::NO_ACCESS)); 8722623SN/A 87310020Smatt.horsnell@ARM.com pkt->req->setAccessLatency(); 87410464SAndreas.Sandberg@ARM.com 87510464SAndreas.Sandberg@ARM.com updateCycleCounts(); 87612284Sjose.marinho@arm.com updateCycleCounters(BaseCPU::CPU_STATE_ON); 8773184Srdreslin@umich.edu 8785728Sgblack@eecs.umich.edu if (pkt->senderState) { 8795728Sgblack@eecs.umich.edu SplitFragmentSenderState * send_state = 8805728Sgblack@eecs.umich.edu dynamic_cast<SplitFragmentSenderState *>(pkt->senderState); 8815728Sgblack@eecs.umich.edu assert(send_state); 8825728Sgblack@eecs.umich.edu delete pkt; 8835728Sgblack@eecs.umich.edu PacketPtr big_pkt = send_state->bigPkt; 8845728Sgblack@eecs.umich.edu delete send_state; 88511320Ssteve.reinhardt@amd.com 8865728Sgblack@eecs.umich.edu SplitMainSenderState * main_send_state = 8875728Sgblack@eecs.umich.edu dynamic_cast<SplitMainSenderState *>(big_pkt->senderState); 8885728Sgblack@eecs.umich.edu assert(main_send_state); 8895728Sgblack@eecs.umich.edu // Record the fact that this packet is no longer outstanding. 8905728Sgblack@eecs.umich.edu assert(main_send_state->outstanding != 0); 8915728Sgblack@eecs.umich.edu main_send_state->outstanding--; 8925728Sgblack@eecs.umich.edu 8935728Sgblack@eecs.umich.edu if (main_send_state->outstanding) { 8945728Sgblack@eecs.umich.edu return; 8955728Sgblack@eecs.umich.edu } else { 8965728Sgblack@eecs.umich.edu delete main_send_state; 8975728Sgblack@eecs.umich.edu big_pkt->senderState = NULL; 8985728Sgblack@eecs.umich.edu pkt = big_pkt; 8995728Sgblack@eecs.umich.edu } 9005728Sgblack@eecs.umich.edu } 9015728Sgblack@eecs.umich.edu 9029342SAndreas.Sandberg@arm.com _status = BaseSimpleCPU::Running; 9035728Sgblack@eecs.umich.edu 90411147Smitch.hayenga@arm.com Fault fault = curStaticInst->completeAcc(pkt, threadInfo[curThread], 90511147Smitch.hayenga@arm.com traceData); 9062623SN/A 9074998Sgblack@eecs.umich.edu // keep an instruction count 9084998Sgblack@eecs.umich.edu if (fault == NoFault) 9094998Sgblack@eecs.umich.edu countInst(); 9105001Sgblack@eecs.umich.edu else if (traceData) { 9115001Sgblack@eecs.umich.edu // If there was a fault, we shouldn't trace this instruction. 9125001Sgblack@eecs.umich.edu delete traceData; 9135001Sgblack@eecs.umich.edu traceData = NULL; 9145001Sgblack@eecs.umich.edu } 9154998Sgblack@eecs.umich.edu 9162644Sstever@eecs.umich.edu delete pkt; 9172644Sstever@eecs.umich.edu 9183184Srdreslin@umich.edu postExecute(); 9193227Sktlim@umich.edu 9202644Sstever@eecs.umich.edu advanceInst(fault); 9212623SN/A} 9222623SN/A 92310030SAli.Saidi@ARM.comvoid 92410464SAndreas.Sandberg@ARM.comTimingSimpleCPU::updateCycleCounts() 92510464SAndreas.Sandberg@ARM.com{ 92610464SAndreas.Sandberg@ARM.com const Cycles delta(curCycle() - previousCycle); 92710464SAndreas.Sandberg@ARM.com 92810464SAndreas.Sandberg@ARM.com numCycles += delta; 92910464SAndreas.Sandberg@ARM.com 93010464SAndreas.Sandberg@ARM.com previousCycle = curCycle(); 93110464SAndreas.Sandberg@ARM.com} 93210464SAndreas.Sandberg@ARM.com 93310464SAndreas.Sandberg@ARM.comvoid 93410030SAli.Saidi@ARM.comTimingSimpleCPU::DcachePort::recvTimingSnoopReq(PacketPtr pkt) 93510030SAli.Saidi@ARM.com{ 93611148Smitch.hayenga@arm.com for (ThreadID tid = 0; tid < cpu->numThreads; tid++) { 93711148Smitch.hayenga@arm.com if (cpu->getCpuAddrMonitor(tid)->doMonitor(pkt)) { 93811151Smitch.hayenga@arm.com cpu->wakeup(tid); 93911148Smitch.hayenga@arm.com } 94010529Smorr@cs.wisc.edu } 94111147Smitch.hayenga@arm.com 94211356Skrinat01@arm.com // Making it uniform across all CPUs: 94311356Skrinat01@arm.com // The CPUs need to be woken up only on an invalidation packet (when using caches) 94411356Skrinat01@arm.com // or on an incoming write packet (when not using caches) 94511356Skrinat01@arm.com // It is not necessary to wake up the processor on all incoming packets 94611356Skrinat01@arm.com if (pkt->isInvalidate() || pkt->isWrite()) { 94711356Skrinat01@arm.com for (auto &t_info : cpu->threadInfo) { 94811356Skrinat01@arm.com TheISA::handleLockedSnoop(t_info->thread, pkt, cacheBlockMask); 94911356Skrinat01@arm.com } 95011147Smitch.hayenga@arm.com } 95110030SAli.Saidi@ARM.com} 95210030SAli.Saidi@ARM.com 95310529Smorr@cs.wisc.eduvoid 95410529Smorr@cs.wisc.eduTimingSimpleCPU::DcachePort::recvFunctionalSnoop(PacketPtr pkt) 95510529Smorr@cs.wisc.edu{ 95611148Smitch.hayenga@arm.com for (ThreadID tid = 0; tid < cpu->numThreads; tid++) { 95711321Ssteve.reinhardt@amd.com if (cpu->getCpuAddrMonitor(tid)->doMonitor(pkt)) { 95811151Smitch.hayenga@arm.com cpu->wakeup(tid); 95911148Smitch.hayenga@arm.com } 96010529Smorr@cs.wisc.edu } 96110529Smorr@cs.wisc.edu} 96210030SAli.Saidi@ARM.com 9632623SN/Abool 9648975Sandreas.hansson@arm.comTimingSimpleCPU::DcachePort::recvTimingResp(PacketPtr pkt) 9652623SN/A{ 96610669Sandreas.hansson@arm.com DPRINTF(SimpleCPU, "Received load/store response %#x\n", pkt->getAddr()); 9672948Ssaidi@eecs.umich.edu 96810669Sandreas.hansson@arm.com // The timing CPU is not really ticked, instead it relies on the 96910669Sandreas.hansson@arm.com // memory system (fetch and load/store) to set the pace. 97010669Sandreas.hansson@arm.com if (!tickEvent.scheduled()) { 97110669Sandreas.hansson@arm.com // Delay processing of returned data until next CPU clock edge 97210669Sandreas.hansson@arm.com tickEvent.schedule(pkt, cpu->clockEdge()); 97310669Sandreas.hansson@arm.com return true; 9749165Sandreas.hansson@arm.com } else { 97510669Sandreas.hansson@arm.com // In the case of a split transaction and a cache that is 97610669Sandreas.hansson@arm.com // faster than a CPU we could get two responses in the 97710669Sandreas.hansson@arm.com // same tick, delay the second one 97810713Sandreas.hansson@arm.com if (!retryRespEvent.scheduled()) 97910713Sandreas.hansson@arm.com cpu->schedule(retryRespEvent, cpu->clockEdge(Cycles(1))); 98010669Sandreas.hansson@arm.com return false; 9813310Srdreslin@umich.edu } 9822948Ssaidi@eecs.umich.edu} 9832948Ssaidi@eecs.umich.edu 9842948Ssaidi@eecs.umich.eduvoid 9852948Ssaidi@eecs.umich.eduTimingSimpleCPU::DcachePort::DTickEvent::process() 9862948Ssaidi@eecs.umich.edu{ 9872630SN/A cpu->completeDataAccess(pkt); 9882623SN/A} 9892623SN/A 9902657Ssaidi@eecs.umich.eduvoid 99110713Sandreas.hansson@arm.comTimingSimpleCPU::DcachePort::recvReqRetry() 9922623SN/A{ 9932623SN/A // we shouldn't get a retry unless we have a packet that we're 9942623SN/A // waiting to transmit 9952623SN/A assert(cpu->dcache_pkt != NULL); 9962623SN/A assert(cpu->_status == DcacheRetry); 9973349Sbinkertn@umich.edu PacketPtr tmp = cpu->dcache_pkt; 9985728Sgblack@eecs.umich.edu if (tmp->senderState) { 9995728Sgblack@eecs.umich.edu // This is a packet from a split access. 10005728Sgblack@eecs.umich.edu SplitFragmentSenderState * send_state = 10015728Sgblack@eecs.umich.edu dynamic_cast<SplitFragmentSenderState *>(tmp->senderState); 10025728Sgblack@eecs.umich.edu assert(send_state); 10035728Sgblack@eecs.umich.edu PacketPtr big_pkt = send_state->bigPkt; 100411320Ssteve.reinhardt@amd.com 10055728Sgblack@eecs.umich.edu SplitMainSenderState * main_send_state = 10065728Sgblack@eecs.umich.edu dynamic_cast<SplitMainSenderState *>(big_pkt->senderState); 10075728Sgblack@eecs.umich.edu assert(main_send_state); 10085728Sgblack@eecs.umich.edu 10098975Sandreas.hansson@arm.com if (sendTimingReq(tmp)) { 10105728Sgblack@eecs.umich.edu // If we were able to send without retrying, record that fact 10115728Sgblack@eecs.umich.edu // and try sending the other fragment. 10125728Sgblack@eecs.umich.edu send_state->clearFromParent(); 10135728Sgblack@eecs.umich.edu int other_index = main_send_state->getPendingFragment(); 10145728Sgblack@eecs.umich.edu if (other_index > 0) { 10155728Sgblack@eecs.umich.edu tmp = main_send_state->fragments[other_index]; 10165728Sgblack@eecs.umich.edu cpu->dcache_pkt = tmp; 10175728Sgblack@eecs.umich.edu if ((big_pkt->isRead() && cpu->handleReadPacket(tmp)) || 10185728Sgblack@eecs.umich.edu (big_pkt->isWrite() && cpu->handleWritePacket())) { 10195728Sgblack@eecs.umich.edu main_send_state->fragments[other_index] = NULL; 10205728Sgblack@eecs.umich.edu } 10215728Sgblack@eecs.umich.edu } else { 10225728Sgblack@eecs.umich.edu cpu->_status = DcacheWaitResponse; 10235728Sgblack@eecs.umich.edu // memory system takes ownership of packet 10245728Sgblack@eecs.umich.edu cpu->dcache_pkt = NULL; 10255728Sgblack@eecs.umich.edu } 10265728Sgblack@eecs.umich.edu } 10278975Sandreas.hansson@arm.com } else if (sendTimingReq(tmp)) { 10282657Ssaidi@eecs.umich.edu cpu->_status = DcacheWaitResponse; 10293170Sstever@eecs.umich.edu // memory system takes ownership of packet 10302657Ssaidi@eecs.umich.edu cpu->dcache_pkt = NULL; 10312657Ssaidi@eecs.umich.edu } 10322623SN/A} 10332623SN/A 10345606Snate@binkert.orgTimingSimpleCPU::IprEvent::IprEvent(Packet *_pkt, TimingSimpleCPU *_cpu, 10355606Snate@binkert.org Tick t) 10365606Snate@binkert.org : pkt(_pkt), cpu(_cpu) 10375103Ssaidi@eecs.umich.edu{ 10385606Snate@binkert.org cpu->schedule(this, t); 10395103Ssaidi@eecs.umich.edu} 10405103Ssaidi@eecs.umich.edu 10415103Ssaidi@eecs.umich.eduvoid 10425103Ssaidi@eecs.umich.eduTimingSimpleCPU::IprEvent::process() 10435103Ssaidi@eecs.umich.edu{ 10445103Ssaidi@eecs.umich.edu cpu->completeDataAccess(pkt); 10455103Ssaidi@eecs.umich.edu} 10465103Ssaidi@eecs.umich.edu 10475103Ssaidi@eecs.umich.educonst char * 10485336Shines@cs.fsu.eduTimingSimpleCPU::IprEvent::description() const 10495103Ssaidi@eecs.umich.edu{ 10505103Ssaidi@eecs.umich.edu return "Timing Simple CPU Delay IPR event"; 10515103Ssaidi@eecs.umich.edu} 10525103Ssaidi@eecs.umich.edu 10532623SN/A 10545315Sstever@gmail.comvoid 10555315Sstever@gmail.comTimingSimpleCPU::printAddr(Addr a) 10565315Sstever@gmail.com{ 10575315Sstever@gmail.com dcachePort.printAddr(a); 10585315Sstever@gmail.com} 10595315Sstever@gmail.com 10605315Sstever@gmail.com 10612623SN/A//////////////////////////////////////////////////////////////////////// 10622623SN/A// 10632623SN/A// TimingSimpleCPU Simulation Object 10642623SN/A// 10654762Snate@binkert.orgTimingSimpleCPU * 10664762Snate@binkert.orgTimingSimpleCPUParams::create() 10672623SN/A{ 10685529Snate@binkert.org return new TimingSimpleCPU(this); 10692623SN/A} 1070