timing.cc revision 12769
12623SN/A/* 22623SN/A * Copyright 2014 Google, Inc. 32623SN/A * Copyright (c) 2010-2013,2015,2017 ARM Limited 42623SN/A * All rights reserved 52623SN/A * 62623SN/A * The license below extends only to copyright in the software and shall 72623SN/A * not be construed as granting a license to any other intellectual 82623SN/A * property including but not limited to intellectual property relating 92623SN/A * to a hardware implementation of the functionality of the software 102623SN/A * licensed hereunder. You may use the software subject to the license 112623SN/A * terms below provided that you ensure that this notice is replicated 122623SN/A * unmodified and in its entirety in all distributions of the software, 132623SN/A * modified or unmodified, in source code or in binary form. 142623SN/A * 152623SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 162623SN/A * All rights reserved. 172623SN/A * 182623SN/A * Redistribution and use in source and binary forms, with or without 192623SN/A * modification, are permitted provided that the following conditions are 202623SN/A * met: redistributions of source code must retain the above copyright 212623SN/A * notice, this list of conditions and the following disclaimer; 222623SN/A * redistributions in binary form must reproduce the above copyright 232623SN/A * notice, this list of conditions and the following disclaimer in the 242623SN/A * documentation and/or other materials provided with the distribution; 252623SN/A * neither the name of the copyright holders nor the names of its 262623SN/A * contributors may be used to endorse or promote products derived from 272665Ssaidi@eecs.umich.edu * this software without specific prior written permission. 282665Ssaidi@eecs.umich.edu * 292623SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 302623SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 313170Sstever@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 325103Ssaidi@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 332623SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 344040Ssaidi@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 352623SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 362623SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 373348Sbinkertn@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 383348Sbinkertn@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 394762Snate@binkert.org * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402901Ssaidi@eecs.umich.edu * 412623SN/A * Authors: Steve Reinhardt 422623SN/A */ 432623SN/A 442623SN/A#include "cpu/simple/timing.hh" 452856Srdreslin@umich.edu 462856Srdreslin@umich.edu#include "arch/locked_mem.hh" 472856Srdreslin@umich.edu#include "arch/mmapped_ipr.hh" 482856Srdreslin@umich.edu#include "arch/utility.hh" 492856Srdreslin@umich.edu#include "config/the_isa.hh" 502856Srdreslin@umich.edu#include "cpu/exetrace.hh" 512856Srdreslin@umich.edu#include "debug/Config.hh" 522856Srdreslin@umich.edu#include "debug/Drain.hh" 532856Srdreslin@umich.edu#include "debug/ExecFaulting.hh" 542856Srdreslin@umich.edu#include "debug/Mwait.hh" 552623SN/A#include "debug/SimpleCPU.hh" 562623SN/A#include "mem/packet.hh" 572623SN/A#include "mem/packet_access.hh" 582623SN/A#include "params/TimingSimpleCPU.hh" 592623SN/A#include "sim/faults.hh" 602623SN/A#include "sim/full_system.hh" 612680Sktlim@umich.edu#include "sim/system.hh" 622680Sktlim@umich.edu 632623SN/Ausing namespace std; 642623SN/Ausing namespace TheISA; 655712Shsul@eecs.umich.edu 662623SN/Avoid 672623SN/ATimingSimpleCPU::init() 682623SN/A{ 692623SN/A BaseSimpleCPU::init(); 702623SN/A} 713349Sbinkertn@umich.edu 722623SN/Avoid 732623SN/ATimingSimpleCPU::TimingCPUPort::TickEvent::schedule(PacketPtr _pkt, Tick t) 742623SN/A{ 752623SN/A pkt = _pkt; 762623SN/A cpu->schedule(this, t); 772623SN/A} 783349Sbinkertn@umich.edu 792623SN/ATimingSimpleCPU::TimingSimpleCPU(TimingSimpleCPUParams *p) 803184Srdreslin@umich.edu : BaseSimpleCPU(p), fetchTranslation(this), icachePort(this), 813184Srdreslin@umich.edu dcachePort(this), ifetch_pkt(NULL), dcache_pkt(NULL), previousCycle(0), 822623SN/A fetchEvent([this]{ fetch(); }, name()) 832623SN/A{ 842623SN/A _status = Idle; 852623SN/A} 862623SN/A 873647Srdreslin@umich.edu 883647Srdreslin@umich.edu 893647Srdreslin@umich.eduTimingSimpleCPU::~TimingSimpleCPU() 903647Srdreslin@umich.edu{ 913647Srdreslin@umich.edu} 922631SN/A 933647Srdreslin@umich.eduDrainState 942631SN/ATimingSimpleCPU::drain() 952623SN/A{ 962623SN/A // Deschedule any power gating event (if any) 972623SN/A deschedulePowerGatingEvent(); 982948Ssaidi@eecs.umich.edu 992948Ssaidi@eecs.umich.edu if (switchedOut()) 1003349Sbinkertn@umich.edu return DrainState::Drained; 1012948Ssaidi@eecs.umich.edu 1022948Ssaidi@eecs.umich.edu if (_status == Idle || 1035606Snate@binkert.org (_status == BaseSimpleCPU::Running && isDrained())) { 1042948Ssaidi@eecs.umich.edu DPRINTF(Drain, "No need to drain.\n"); 1052948Ssaidi@eecs.umich.edu activeThreads.clear(); 1065529Snate@binkert.org return DrainState::Drained; 1075894Sgblack@eecs.umich.edu } else { 1085894Sgblack@eecs.umich.edu DPRINTF(Drain, "Requesting drain.\n"); 1092623SN/A 1102623SN/A // The fetch event can become descheduled if a drain didn't 1113647Srdreslin@umich.edu // succeed on the first attempt. We need to reschedule it if 1123647Srdreslin@umich.edu // the CPU is waiting for a microcode routine to complete. 1133647Srdreslin@umich.edu if (_status == BaseSimpleCPU::Running && !fetchEvent.scheduled()) 1143647Srdreslin@umich.edu schedule(fetchEvent, clockEdge()); 1152623SN/A 1162839Sktlim@umich.edu return DrainState::Draining; 1173222Sktlim@umich.edu } 1182901Ssaidi@eecs.umich.edu} 1192623SN/A 1202623SN/Avoid 1212623SN/ATimingSimpleCPU::drainResume() 1222623SN/A{ 1232623SN/A assert(!fetchEvent.scheduled()); 1242623SN/A if (switchedOut()) 1252623SN/A return; 1262623SN/A 1272623SN/A DPRINTF(SimpleCPU, "Resume\n"); 1282623SN/A verifyMemoryMode(); 1292915Sktlim@umich.edu 1302915Sktlim@umich.edu assert(!threadContexts.empty()); 1312623SN/A 1322623SN/A _status = BaseSimpleCPU::Idle; 1332623SN/A 1342623SN/A for (ThreadID tid = 0; tid < numThreads; tid++) { 1352623SN/A if (threadInfo[tid]->thread->status() == ThreadContext::Active) { 1362623SN/A threadInfo[tid]->notIdleFraction = 1; 1372915Sktlim@umich.edu 1382915Sktlim@umich.edu activeThreads.push_back(tid); 1392623SN/A 1402798Sktlim@umich.edu _status = BaseSimpleCPU::Running; 1412798Sktlim@umich.edu 1422901Ssaidi@eecs.umich.edu // Fetch if any threads active 1432839Sktlim@umich.edu if (!fetchEvent.scheduled()) { 1442798Sktlim@umich.edu schedule(fetchEvent, nextCycle()); 1452839Sktlim@umich.edu } 1462798Sktlim@umich.edu } else { 1475496Ssaidi@eecs.umich.edu threadInfo[tid]->notIdleFraction = 0; 1482901Ssaidi@eecs.umich.edu } 1492901Ssaidi@eecs.umich.edu } 1502798Sktlim@umich.edu 1512839Sktlim@umich.edu // Reschedule any power gating event (if any) 1522839Sktlim@umich.edu schedulePowerGatingEvent(); 1532901Ssaidi@eecs.umich.edu 1542798Sktlim@umich.edu system->totalNumInsts = 0; 1552623SN/A} 1562623SN/A 1572623SN/Abool 1582798Sktlim@umich.eduTimingSimpleCPU::tryCompleteDrain() 1592623SN/A{ 1605221Ssaidi@eecs.umich.edu if (drainState() != DrainState::Draining) 1612798Sktlim@umich.edu return false; 1624762Snate@binkert.org 1633201Shsul@eecs.umich.edu DPRINTF(Drain, "tryCompleteDrain.\n"); 1645710Scws3k@cs.virginia.edu if (!isDrained()) 1655710Scws3k@cs.virginia.edu return false; 1662915Sktlim@umich.edu 1675710Scws3k@cs.virginia.edu DPRINTF(Drain, "CPU done draining, processing drain event\n"); 1682623SN/A signalDrainDone(); 1692798Sktlim@umich.edu 1702901Ssaidi@eecs.umich.edu return true; 1712798Sktlim@umich.edu} 1722798Sktlim@umich.edu 1732798Sktlim@umich.eduvoid 1742798Sktlim@umich.eduTimingSimpleCPU::switchOut() 1752798Sktlim@umich.edu{ 1765496Ssaidi@eecs.umich.edu SimpleExecContext& t_info = *threadInfo[curThread]; 1772798Sktlim@umich.edu M5_VAR_USED SimpleThread* thread = t_info.thread; 1785099Ssaidi@eecs.umich.edu 1792867Sktlim@umich.edu BaseSimpleCPU::switchOut(); 1802867Sktlim@umich.edu 1812867Sktlim@umich.edu assert(!fetchEvent.scheduled()); 1825710Scws3k@cs.virginia.edu assert(_status == BaseSimpleCPU::Running || _status == Idle); 1835606Snate@binkert.org assert(!t_info.stayAtPC); 1842623SN/A assert(thread->microPC() == 0); 1852623SN/A 1862623SN/A updateCycleCounts(); 1872623SN/A updateCycleCounters(BaseCPU::CPU_STATE_ON); 1882623SN/A} 1892623SN/A 1904192Sktlim@umich.edu 1912623SN/Avoid 1922680Sktlim@umich.eduTimingSimpleCPU::takeOverFrom(BaseCPU *oldCPU) 1932623SN/A{ 1942680Sktlim@umich.edu BaseSimpleCPU::takeOverFrom(oldCPU); 1952680Sktlim@umich.edu 1962680Sktlim@umich.edu previousCycle = curCycle(); 1972623SN/A} 1982623SN/A 1992623SN/Avoid 2002623SN/ATimingSimpleCPU::verifyMemoryMode() const 2013201Shsul@eecs.umich.edu{ 2023201Shsul@eecs.umich.edu if (!system->isTimingMode()) { 2033201Shsul@eecs.umich.edu fatal("The timing CPU requires the memory system to be in " 2043201Shsul@eecs.umich.edu "'timing' mode.\n"); 2055169Ssaidi@eecs.umich.edu } 2065101Ssaidi@eecs.umich.edu} 2072623SN/A 2082623SN/Avoid 2092623SN/ATimingSimpleCPU::activateContext(ThreadID thread_num) 2102623SN/A{ 2112623SN/A DPRINTF(SimpleCPU, "ActivateContext %d\n", thread_num); 2122623SN/A 2135221Ssaidi@eecs.umich.edu assert(thread_num < numThreads); 2145221Ssaidi@eecs.umich.edu 2152623SN/A threadInfo[thread_num]->notIdleFraction = 1; 2162683Sktlim@umich.edu if (_status == BaseSimpleCPU::Idle) 2172623SN/A _status = BaseSimpleCPU::Running; 2182623SN/A 2192623SN/A // kick things off by initiating the fetch of the next instruction 2202623SN/A if (!fetchEvent.scheduled()) 2212623SN/A schedule(fetchEvent, clockEdge(Cycles(0))); 2223686Sktlim@umich.edu 2232623SN/A if (std::find(activeThreads.begin(), activeThreads.end(), thread_num) 2245606Snate@binkert.org == activeThreads.end()) { 2252623SN/A activeThreads.push_back(thread_num); 2262623SN/A } 2272623SN/A 2282623SN/A BaseCPU::activateContext(thread_num); 2292623SN/A} 2302623SN/A 2315221Ssaidi@eecs.umich.edu 2325221Ssaidi@eecs.umich.eduvoid 2332623SN/ATimingSimpleCPU::suspendContext(ThreadID thread_num) 2342683Sktlim@umich.edu{ 2352623SN/A DPRINTF(SimpleCPU, "SuspendContext %d\n", thread_num); 2362644Sstever@eecs.umich.edu 2372623SN/A assert(thread_num < numThreads); 2382644Sstever@eecs.umich.edu activeThreads.remove(thread_num); 2392644Sstever@eecs.umich.edu 2402623SN/A if (_status == Idle) 2412623SN/A return; 2422623SN/A 2432623SN/A assert(_status == BaseSimpleCPU::Running); 2442623SN/A 2455728Sgblack@eecs.umich.edu threadInfo[thread_num]->notIdleFraction = 0; 2465728Sgblack@eecs.umich.edu 2475728Sgblack@eecs.umich.edu if (activeThreads.empty()) { 2485728Sgblack@eecs.umich.edu _status = Idle; 2495728Sgblack@eecs.umich.edu 2505728Sgblack@eecs.umich.edu if (fetchEvent.scheduled()) { 2515728Sgblack@eecs.umich.edu deschedule(fetchEvent); 2525728Sgblack@eecs.umich.edu } 2535728Sgblack@eecs.umich.edu } 2545728Sgblack@eecs.umich.edu 2555728Sgblack@eecs.umich.edu BaseCPU::suspendContext(thread_num); 2565728Sgblack@eecs.umich.edu} 2575728Sgblack@eecs.umich.edu 2585728Sgblack@eecs.umich.edubool 2595728Sgblack@eecs.umich.eduTimingSimpleCPU::handleReadPacket(PacketPtr pkt) 2605728Sgblack@eecs.umich.edu{ 2615728Sgblack@eecs.umich.edu SimpleExecContext &t_info = *threadInfo[curThread]; 2625728Sgblack@eecs.umich.edu SimpleThread* thread = t_info.thread; 2635728Sgblack@eecs.umich.edu 2645728Sgblack@eecs.umich.edu const RequestPtr &req = pkt->req; 2652623SN/A 2665894Sgblack@eecs.umich.edu // We're about the issues a locked load, so tell the monitor 2675894Sgblack@eecs.umich.edu // to start caring about this address 2685894Sgblack@eecs.umich.edu if (pkt->isRead() && pkt->req->isLLSC()) { 2695744Sgblack@eecs.umich.edu TheISA::handleLockedRead(thread, pkt->req); 2705894Sgblack@eecs.umich.edu } 2715894Sgblack@eecs.umich.edu if (req->isMmappedIpr()) { 2725894Sgblack@eecs.umich.edu Cycles delay = TheISA::handleIprRead(thread->getTC(), pkt); 2735894Sgblack@eecs.umich.edu new IprEvent(pkt, this, clockEdge(delay)); 2745744Sgblack@eecs.umich.edu _status = DcacheWaitResponse; 2755894Sgblack@eecs.umich.edu dcache_pkt = NULL; 2765894Sgblack@eecs.umich.edu } else if (!dcachePort.sendTimingReq(pkt)) { 2775894Sgblack@eecs.umich.edu _status = DcacheRetry; 2785894Sgblack@eecs.umich.edu dcache_pkt = pkt; 2795894Sgblack@eecs.umich.edu } else { 2805894Sgblack@eecs.umich.edu _status = DcacheWaitResponse; 2815894Sgblack@eecs.umich.edu // memory system takes ownership of packet 2825894Sgblack@eecs.umich.edu dcache_pkt = NULL; 2835894Sgblack@eecs.umich.edu } 2845894Sgblack@eecs.umich.edu return dcache_pkt == NULL; 2855894Sgblack@eecs.umich.edu} 2865894Sgblack@eecs.umich.edu 2875894Sgblack@eecs.umich.eduvoid 2885894Sgblack@eecs.umich.eduTimingSimpleCPU::sendData(const RequestPtr &req, uint8_t *data, uint64_t *res, 2895894Sgblack@eecs.umich.edu bool read) 2905894Sgblack@eecs.umich.edu{ 2915894Sgblack@eecs.umich.edu SimpleExecContext &t_info = *threadInfo[curThread]; 2925894Sgblack@eecs.umich.edu SimpleThread* thread = t_info.thread; 2935894Sgblack@eecs.umich.edu 2945894Sgblack@eecs.umich.edu PacketPtr pkt = buildPacket(req, read); 2955894Sgblack@eecs.umich.edu pkt->dataDynamic<uint8_t>(data); 2965894Sgblack@eecs.umich.edu if (req->getFlags().isSet(Request::NO_ACCESS)) { 2975894Sgblack@eecs.umich.edu assert(!dcache_pkt); 2985894Sgblack@eecs.umich.edu pkt->makeResponse(); 2995894Sgblack@eecs.umich.edu completeDataAccess(pkt); 3005894Sgblack@eecs.umich.edu } else if (read) { 3015894Sgblack@eecs.umich.edu handleReadPacket(pkt); 3025894Sgblack@eecs.umich.edu } else { 3035894Sgblack@eecs.umich.edu bool do_access = true; // flag to suppress cache access 3045894Sgblack@eecs.umich.edu 3055894Sgblack@eecs.umich.edu if (req->isLLSC()) { 3065894Sgblack@eecs.umich.edu do_access = TheISA::handleLockedWrite(thread, req, dcachePort.cacheBlockMask); 3075894Sgblack@eecs.umich.edu } else if (req->isCondSwap()) { 3085894Sgblack@eecs.umich.edu assert(res); 3095894Sgblack@eecs.umich.edu req->setExtraData(*res); 3105894Sgblack@eecs.umich.edu } 3115894Sgblack@eecs.umich.edu 3125894Sgblack@eecs.umich.edu if (do_access) { 3135894Sgblack@eecs.umich.edu dcache_pkt = pkt; 3145894Sgblack@eecs.umich.edu handleWritePacket(); 3155890Sgblack@eecs.umich.edu threadSnoop(pkt, curThread); 3165894Sgblack@eecs.umich.edu } else { 3175894Sgblack@eecs.umich.edu _status = DcacheWaitResponse; 3185894Sgblack@eecs.umich.edu completeDataAccess(pkt); 3195894Sgblack@eecs.umich.edu } 3205894Sgblack@eecs.umich.edu } 3215894Sgblack@eecs.umich.edu} 3225894Sgblack@eecs.umich.edu 3235894Sgblack@eecs.umich.eduvoid 3245894Sgblack@eecs.umich.eduTimingSimpleCPU::sendSplitData(const RequestPtr &req1, const RequestPtr &req2, 3255894Sgblack@eecs.umich.edu const RequestPtr &req, uint8_t *data, bool read) 3265894Sgblack@eecs.umich.edu{ 3275894Sgblack@eecs.umich.edu PacketPtr pkt1, pkt2; 3285894Sgblack@eecs.umich.edu buildSplitPacket(pkt1, pkt2, req1, req2, req, data, read); 3295894Sgblack@eecs.umich.edu if (req->getFlags().isSet(Request::NO_ACCESS)) { 3305894Sgblack@eecs.umich.edu assert(!dcache_pkt); 3315894Sgblack@eecs.umich.edu pkt1->makeResponse(); 3325894Sgblack@eecs.umich.edu completeDataAccess(pkt1); 3335894Sgblack@eecs.umich.edu } else if (read) { 3345894Sgblack@eecs.umich.edu SplitFragmentSenderState * send_state = 3355894Sgblack@eecs.umich.edu dynamic_cast<SplitFragmentSenderState *>(pkt1->senderState); 3365894Sgblack@eecs.umich.edu if (handleReadPacket(pkt1)) { 3375894Sgblack@eecs.umich.edu send_state->clearFromParent(); 3385894Sgblack@eecs.umich.edu send_state = dynamic_cast<SplitFragmentSenderState *>( 3395894Sgblack@eecs.umich.edu pkt2->senderState); 3405894Sgblack@eecs.umich.edu if (handleReadPacket(pkt2)) { 3415894Sgblack@eecs.umich.edu send_state->clearFromParent(); 3425894Sgblack@eecs.umich.edu } 3435894Sgblack@eecs.umich.edu } 3445894Sgblack@eecs.umich.edu } else { 3455894Sgblack@eecs.umich.edu dcache_pkt = pkt1; 3465894Sgblack@eecs.umich.edu SplitFragmentSenderState * send_state = 3475894Sgblack@eecs.umich.edu dynamic_cast<SplitFragmentSenderState *>(pkt1->senderState); 3485894Sgblack@eecs.umich.edu if (handleWritePacket()) { 3495894Sgblack@eecs.umich.edu send_state->clearFromParent(); 3505894Sgblack@eecs.umich.edu dcache_pkt = pkt2; 3515894Sgblack@eecs.umich.edu send_state = dynamic_cast<SplitFragmentSenderState *>( 3525894Sgblack@eecs.umich.edu pkt2->senderState); 3535894Sgblack@eecs.umich.edu if (handleWritePacket()) { 3545894Sgblack@eecs.umich.edu send_state->clearFromParent(); 3555894Sgblack@eecs.umich.edu } 3565894Sgblack@eecs.umich.edu } 3575894Sgblack@eecs.umich.edu } 3585894Sgblack@eecs.umich.edu} 3595894Sgblack@eecs.umich.edu 3605894Sgblack@eecs.umich.eduvoid 3615894Sgblack@eecs.umich.eduTimingSimpleCPU::translationFault(const Fault &fault) 3625894Sgblack@eecs.umich.edu{ 3635894Sgblack@eecs.umich.edu // fault may be NoFault in cases where a fault is suppressed, 3645894Sgblack@eecs.umich.edu // for instance prefetches. 3655894Sgblack@eecs.umich.edu updateCycleCounts(); 3665744Sgblack@eecs.umich.edu updateCycleCounters(BaseCPU::CPU_STATE_ON); 3675744Sgblack@eecs.umich.edu 3685894Sgblack@eecs.umich.edu if (traceData) { 3695894Sgblack@eecs.umich.edu // Since there was a fault, we shouldn't trace this instruction. 3705894Sgblack@eecs.umich.edu delete traceData; 3715894Sgblack@eecs.umich.edu traceData = NULL; 3725894Sgblack@eecs.umich.edu } 3735894Sgblack@eecs.umich.edu 3745894Sgblack@eecs.umich.edu postExecute(); 3755894Sgblack@eecs.umich.edu 3765894Sgblack@eecs.umich.edu advanceInst(fault); 3775894Sgblack@eecs.umich.edu} 3785894Sgblack@eecs.umich.edu 3795894Sgblack@eecs.umich.eduPacketPtr 3805894Sgblack@eecs.umich.eduTimingSimpleCPU::buildPacket(const RequestPtr &req, bool read) 3815894Sgblack@eecs.umich.edu{ 3825894Sgblack@eecs.umich.edu return read ? Packet::createRead(req) : Packet::createWrite(req); 3835894Sgblack@eecs.umich.edu} 3845894Sgblack@eecs.umich.edu 3855894Sgblack@eecs.umich.eduvoid 3865894Sgblack@eecs.umich.eduTimingSimpleCPU::buildSplitPacket(PacketPtr &pkt1, PacketPtr &pkt2, 3875894Sgblack@eecs.umich.edu const RequestPtr &req1, const RequestPtr &req2, const RequestPtr &req, 3885894Sgblack@eecs.umich.edu uint8_t *data, bool read) 3895894Sgblack@eecs.umich.edu{ 3905894Sgblack@eecs.umich.edu pkt1 = pkt2 = NULL; 3915894Sgblack@eecs.umich.edu 3925894Sgblack@eecs.umich.edu assert(!req1->isMmappedIpr() && !req2->isMmappedIpr()); 3935894Sgblack@eecs.umich.edu 3945894Sgblack@eecs.umich.edu if (req->getFlags().isSet(Request::NO_ACCESS)) { 3955894Sgblack@eecs.umich.edu pkt1 = buildPacket(req, read); 3965894Sgblack@eecs.umich.edu return; 3975894Sgblack@eecs.umich.edu } 3985894Sgblack@eecs.umich.edu 3995894Sgblack@eecs.umich.edu pkt1 = buildPacket(req1, read); 4005894Sgblack@eecs.umich.edu pkt2 = buildPacket(req2, read); 4015894Sgblack@eecs.umich.edu 4025894Sgblack@eecs.umich.edu PacketPtr pkt = new Packet(req, pkt1->cmd.responseCommand()); 4035894Sgblack@eecs.umich.edu 4045744Sgblack@eecs.umich.edu pkt->dataDynamic<uint8_t>(data); 4055744Sgblack@eecs.umich.edu pkt1->dataStatic<uint8_t>(data); 4065894Sgblack@eecs.umich.edu pkt2->dataStatic<uint8_t>(data + req1->getSize()); 4075894Sgblack@eecs.umich.edu 4085894Sgblack@eecs.umich.edu SplitMainSenderState * main_send_state = new SplitMainSenderState; 4095894Sgblack@eecs.umich.edu pkt->senderState = main_send_state; 4105894Sgblack@eecs.umich.edu main_send_state->fragments[0] = pkt1; 4115894Sgblack@eecs.umich.edu main_send_state->fragments[1] = pkt2; 4125894Sgblack@eecs.umich.edu main_send_state->outstanding = 2; 4135894Sgblack@eecs.umich.edu pkt1->senderState = new SplitFragmentSenderState(pkt, 0); 4145744Sgblack@eecs.umich.edu pkt2->senderState = new SplitFragmentSenderState(pkt, 1); 4155744Sgblack@eecs.umich.edu} 4165744Sgblack@eecs.umich.edu 4175744Sgblack@eecs.umich.eduFault 4185744Sgblack@eecs.umich.eduTimingSimpleCPU::readMem(Addr addr, uint8_t *data, 4195744Sgblack@eecs.umich.edu unsigned size, Request::Flags flags) 4205744Sgblack@eecs.umich.edu{ 4215744Sgblack@eecs.umich.edu panic("readMem() is for atomic accesses, and should " 4225744Sgblack@eecs.umich.edu "never be called on TimingSimpleCPU.\n"); 4235744Sgblack@eecs.umich.edu} 4245744Sgblack@eecs.umich.edu 4255744Sgblack@eecs.umich.eduFault 4265744Sgblack@eecs.umich.eduTimingSimpleCPU::initiateMemRead(Addr addr, unsigned size, 4275744Sgblack@eecs.umich.edu Request::Flags flags) 4285744Sgblack@eecs.umich.edu{ 4295744Sgblack@eecs.umich.edu SimpleExecContext &t_info = *threadInfo[curThread]; 4305744Sgblack@eecs.umich.edu SimpleThread* thread = t_info.thread; 4312623SN/A 4322623SN/A Fault fault; 4332623SN/A const int asid = 0; 4342623SN/A const Addr pc = thread->instAddr(); 4355728Sgblack@eecs.umich.edu unsigned block_size = cacheLineSize(); 4365728Sgblack@eecs.umich.edu BaseTLB::Mode mode = BaseTLB::Read; 4375728Sgblack@eecs.umich.edu 4385728Sgblack@eecs.umich.edu if (traceData) 4395728Sgblack@eecs.umich.edu traceData->setMem(addr, size, flags); 4405728Sgblack@eecs.umich.edu 4412623SN/A RequestPtr req = std::make_shared<Request>( 4425744Sgblack@eecs.umich.edu asid, addr, size, flags, dataMasterId(), pc, 4435744Sgblack@eecs.umich.edu thread->contextId()); 4445728Sgblack@eecs.umich.edu 4455744Sgblack@eecs.umich.edu req->taskId(taskId()); 4465744Sgblack@eecs.umich.edu 4475728Sgblack@eecs.umich.edu Addr split_addr = roundDown(addr + size - 1, block_size); 4485894Sgblack@eecs.umich.edu assert(split_addr <= addr || split_addr - addr < block_size); 4495894Sgblack@eecs.umich.edu 4505744Sgblack@eecs.umich.edu _status = DTBWaitResponse; 4515894Sgblack@eecs.umich.edu if (split_addr > addr) { 4525894Sgblack@eecs.umich.edu RequestPtr req1, req2; 4535894Sgblack@eecs.umich.edu assert(!req->isLLSC() && !req->isSwap()); 4545894Sgblack@eecs.umich.edu req->splitOnVaddr(split_addr, req1, req2); 4555894Sgblack@eecs.umich.edu 4565894Sgblack@eecs.umich.edu WholeTranslationState *state = 4575894Sgblack@eecs.umich.edu new WholeTranslationState(req, req1, req2, new uint8_t[size], 4585894Sgblack@eecs.umich.edu NULL, mode); 4595894Sgblack@eecs.umich.edu DataTranslation<TimingSimpleCPU *> *trans1 = 4605894Sgblack@eecs.umich.edu new DataTranslation<TimingSimpleCPU *>(this, state, 0); 4615894Sgblack@eecs.umich.edu DataTranslation<TimingSimpleCPU *> *trans2 = 4625744Sgblack@eecs.umich.edu new DataTranslation<TimingSimpleCPU *>(this, state, 1); 4635894Sgblack@eecs.umich.edu 4645894Sgblack@eecs.umich.edu thread->dtb->translateTiming(req1, thread->getTC(), trans1, mode); 4655894Sgblack@eecs.umich.edu thread->dtb->translateTiming(req2, thread->getTC(), trans2, mode); 4662623SN/A } else { 4672623SN/A WholeTranslationState *state = 4685408Sgblack@eecs.umich.edu new WholeTranslationState(req, new uint8_t[size], NULL, mode); 4695408Sgblack@eecs.umich.edu DataTranslation<TimingSimpleCPU *> *translation 4705728Sgblack@eecs.umich.edu = new DataTranslation<TimingSimpleCPU *>(this, state); 4715408Sgblack@eecs.umich.edu thread->dtb->translateTiming(req, thread->getTC(), translation, mode); 4725728Sgblack@eecs.umich.edu } 4735728Sgblack@eecs.umich.edu 4745728Sgblack@eecs.umich.edu return NoFault; 4755728Sgblack@eecs.umich.edu} 4765728Sgblack@eecs.umich.edu 4775728Sgblack@eecs.umich.edubool 4782623SN/ATimingSimpleCPU::handleWritePacket() 4792623SN/A{ 4802623SN/A SimpleExecContext &t_info = *threadInfo[curThread]; 4812623SN/A SimpleThread* thread = t_info.thread; 4822623SN/A 4832623SN/A const RequestPtr &req = dcache_pkt->req; 4844040Ssaidi@eecs.umich.edu if (req->isMmappedIpr()) { 4854040Ssaidi@eecs.umich.edu Cycles delay = TheISA::handleIprWrite(thread->getTC(), dcache_pkt); 4864040Ssaidi@eecs.umich.edu new IprEvent(dcache_pkt, this, clockEdge(delay)); 4874040Ssaidi@eecs.umich.edu _status = DcacheWaitResponse; 4884115Ssaidi@eecs.umich.edu dcache_pkt = NULL; 4894115Ssaidi@eecs.umich.edu } else if (!dcachePort.sendTimingReq(dcache_pkt)) { 4904115Ssaidi@eecs.umich.edu _status = DcacheRetry; 4914115Ssaidi@eecs.umich.edu } else { 4922623SN/A _status = DcacheWaitResponse; 4932623SN/A // memory system takes ownership of packet 4942623SN/A dcache_pkt = NULL; 4952623SN/A } 4962623SN/A return dcache_pkt == NULL; 4972623SN/A} 4982623SN/A 4992623SN/AFault 5002623SN/ATimingSimpleCPU::writeMem(uint8_t *data, unsigned size, 5012623SN/A Addr addr, Request::Flags flags, uint64_t *res) 5022623SN/A{ 5032623SN/A SimpleExecContext &t_info = *threadInfo[curThread]; 5042623SN/A SimpleThread* thread = t_info.thread; 5052623SN/A 5062623SN/A uint8_t *newData = new uint8_t[size]; 5072623SN/A const int asid = 0; 5082623SN/A const Addr pc = thread->instAddr(); 5092623SN/A unsigned block_size = cacheLineSize(); 5102623SN/A BaseTLB::Mode mode = BaseTLB::Write; 5112623SN/A 5122623SN/A if (data == NULL) { 5132623SN/A assert(flags & Request::STORE_NO_DATA); 5142623SN/A // This must be a cache block cleaning request 5152623SN/A memset(newData, 0, size); 5162623SN/A } else { 5172623SN/A memcpy(newData, data, size); 5182623SN/A } 5192623SN/A 5202623SN/A if (traceData) 5212623SN/A traceData->setMem(addr, size, flags); 5222623SN/A 5232623SN/A RequestPtr req = std::make_shared<Request>( 5242623SN/A asid, addr, size, flags, dataMasterId(), pc, 5252623SN/A thread->contextId()); 5262623SN/A 5272623SN/A req->taskId(taskId()); 5282623SN/A 5292623SN/A Addr split_addr = roundDown(addr + size - 1, block_size); 5305728Sgblack@eecs.umich.edu assert(split_addr <= addr || split_addr - addr < block_size); 5315728Sgblack@eecs.umich.edu 5325728Sgblack@eecs.umich.edu _status = DTBWaitResponse; 5335728Sgblack@eecs.umich.edu if (split_addr > addr) { 5345728Sgblack@eecs.umich.edu RequestPtr req1, req2; 5355728Sgblack@eecs.umich.edu assert(!req->isLLSC() && !req->isSwap()); 5365728Sgblack@eecs.umich.edu req->splitOnVaddr(split_addr, req1, req2); 5375728Sgblack@eecs.umich.edu 5385728Sgblack@eecs.umich.edu WholeTranslationState *state = 5395728Sgblack@eecs.umich.edu new WholeTranslationState(req, req1, req2, newData, res, mode); 5405728Sgblack@eecs.umich.edu DataTranslation<TimingSimpleCPU *> *trans1 = 5415728Sgblack@eecs.umich.edu new DataTranslation<TimingSimpleCPU *>(this, state, 0); 5425728Sgblack@eecs.umich.edu DataTranslation<TimingSimpleCPU *> *trans2 = 5435728Sgblack@eecs.umich.edu new DataTranslation<TimingSimpleCPU *>(this, state, 1); 5445728Sgblack@eecs.umich.edu 5455728Sgblack@eecs.umich.edu thread->dtb->translateTiming(req1, thread->getTC(), trans1, mode); 5465728Sgblack@eecs.umich.edu thread->dtb->translateTiming(req2, thread->getTC(), trans2, mode); 5475728Sgblack@eecs.umich.edu } else { 5485728Sgblack@eecs.umich.edu WholeTranslationState *state = 5492623SN/A new WholeTranslationState(req, newData, res, mode); 5502623SN/A DataTranslation<TimingSimpleCPU *> *translation = 5512623SN/A new DataTranslation<TimingSimpleCPU *>(this, state); 5522623SN/A thread->dtb->translateTiming(req, thread->getTC(), translation, mode); 5532623SN/A } 5545728Sgblack@eecs.umich.edu 5555728Sgblack@eecs.umich.edu // Translation faults will be returned via finishTranslation() 5565728Sgblack@eecs.umich.edu return NoFault; 5575728Sgblack@eecs.umich.edu} 5585728Sgblack@eecs.umich.edu 5593169Sstever@eecs.umich.eduvoid 5605744Sgblack@eecs.umich.eduTimingSimpleCPU::threadSnoop(PacketPtr pkt, ThreadID sender) 5615744Sgblack@eecs.umich.edu{ 5625728Sgblack@eecs.umich.edu for (ThreadID tid = 0; tid < numThreads; tid++) { 5635744Sgblack@eecs.umich.edu if (tid != sender) { 5645744Sgblack@eecs.umich.edu if (getCpuAddrMonitor(tid)->doMonitor(pkt)) { 5655728Sgblack@eecs.umich.edu wakeup(tid); 5665894Sgblack@eecs.umich.edu } 5675894Sgblack@eecs.umich.edu TheISA::handleLockedSnoop(threadInfo[tid]->thread, pkt, 5685894Sgblack@eecs.umich.edu dcachePort.cacheBlockMask); 5695744Sgblack@eecs.umich.edu } 5705894Sgblack@eecs.umich.edu } 5715894Sgblack@eecs.umich.edu} 5725894Sgblack@eecs.umich.edu 5735894Sgblack@eecs.umich.eduvoid 5745894Sgblack@eecs.umich.eduTimingSimpleCPU::finishTranslation(WholeTranslationState *state) 5755894Sgblack@eecs.umich.edu{ 5765894Sgblack@eecs.umich.edu _status = BaseSimpleCPU::Running; 5775894Sgblack@eecs.umich.edu 5785894Sgblack@eecs.umich.edu if (state->getFault() != NoFault) { 5795894Sgblack@eecs.umich.edu if (state->isPrefetch()) { 5805894Sgblack@eecs.umich.edu state->setNoFault(); 5815744Sgblack@eecs.umich.edu } 5825894Sgblack@eecs.umich.edu delete [] state->data; 5835894Sgblack@eecs.umich.edu state->deleteReqs(); 5845894Sgblack@eecs.umich.edu translationFault(state->getFault()); 5852623SN/A } else { 5862623SN/A if (!state->isSplit) { 5875408Sgblack@eecs.umich.edu sendData(state->mainReq, state->data, state->res, 5885728Sgblack@eecs.umich.edu state->mode == BaseTLB::Read); 5895408Sgblack@eecs.umich.edu } else { 5905408Sgblack@eecs.umich.edu sendSplitData(state->sreqLow, state->sreqHigh, state->mainReq, 5912623SN/A state->data, state->mode == BaseTLB::Read); 5925728Sgblack@eecs.umich.edu } 5935728Sgblack@eecs.umich.edu } 5945728Sgblack@eecs.umich.edu 5955728Sgblack@eecs.umich.edu delete state; 5962623SN/A} 5972623SN/A 5985728Sgblack@eecs.umich.edu 5992623SN/Avoid 6002623SN/ATimingSimpleCPU::fetch() 6012623SN/A{ 6022623SN/A // Change thread if multi-threaded 6032623SN/A swapActiveThread(); 6042623SN/A 6054224Sgblack@eecs.umich.edu SimpleExecContext &t_info = *threadInfo[curThread]; 6064224Sgblack@eecs.umich.edu SimpleThread* thread = t_info.thread; 6074224Sgblack@eecs.umich.edu 6084224Sgblack@eecs.umich.edu DPRINTF(SimpleCPU, "Fetch\n"); 6094224Sgblack@eecs.umich.edu 6104224Sgblack@eecs.umich.edu if (!curStaticInst || !curStaticInst->isDelayedCommit()) { 6114224Sgblack@eecs.umich.edu checkForInterrupts(); 6124224Sgblack@eecs.umich.edu checkPcEventQueue(); 6134224Sgblack@eecs.umich.edu } 6144224Sgblack@eecs.umich.edu 6152623SN/A // We must have just got suspended by a PC event 6162623SN/A if (_status == Idle) 6172623SN/A return; 6182623SN/A 6192623SN/A TheISA::PCState pcState = thread->pcState(); 6202623SN/A bool needToFetch = !isRomMicroPC(pcState.microPC()) && 6212623SN/A !curMacroStaticInst; 6222623SN/A 6232623SN/A if (needToFetch) { 6242623SN/A _status = BaseSimpleCPU::Running; 6252623SN/A RequestPtr ifetch_req = std::make_shared<Request>(); 6262623SN/A ifetch_req->taskId(taskId()); 6272623SN/A ifetch_req->setContext(thread->contextId()); 6282623SN/A setupFetchRequest(ifetch_req); 6292623SN/A DPRINTF(SimpleCPU, "Translating address %#x\n", ifetch_req->getVaddr()); 6302623SN/A thread->itb->translateTiming(ifetch_req, thread->getTC(), 6312623SN/A &fetchTranslation, BaseTLB::Execute); 6322623SN/A } else { 6332623SN/A _status = IcacheWaitResponse; 6342623SN/A completeIfetch(NULL); 6352623SN/A 6362623SN/A updateCycleCounts(); 6372623SN/A updateCycleCounters(BaseCPU::CPU_STATE_ON); 6382623SN/A } 6392623SN/A} 6402623SN/A 6412623SN/A 6422623SN/Avoid 6432623SN/ATimingSimpleCPU::sendFetch(const Fault &fault, const RequestPtr &req, 6442623SN/A ThreadContext *tc) 6452623SN/A{ 6462623SN/A if (fault == NoFault) { 6472623SN/A DPRINTF(SimpleCPU, "Sending fetch for addr %#x(pa: %#x)\n", 6482623SN/A req->getVaddr(), req->getPaddr()); 6492623SN/A ifetch_pkt = new Packet(req, MemCmd::ReadReq); 6502623SN/A ifetch_pkt->dataStatic(&inst); 6512623SN/A DPRINTF(SimpleCPU, " -- pkt addr: %#x\n", ifetch_pkt->getAddr()); 6522623SN/A 6532623SN/A if (!icachePort.sendTimingReq(ifetch_pkt)) { 6542623SN/A // Need to wait for retry 6552623SN/A _status = IcacheRetry; 6562623SN/A } else { 6572623SN/A // Need to wait for cache to respond 6582623SN/A _status = IcacheWaitResponse; 6592623SN/A // ownership of packet transferred to memory system 6602623SN/A ifetch_pkt = NULL; 6615221Ssaidi@eecs.umich.edu } 6625221Ssaidi@eecs.umich.edu } else { 6633387Sgblack@eecs.umich.edu DPRINTF(SimpleCPU, "Translation of addr %#x faulted\n", req->getVaddr()); 6643387Sgblack@eecs.umich.edu // fetch fault: advance directly to next instruction (fault handler) 6652631SN/A _status = BaseSimpleCPU::Running; 6665348Ssaidi@eecs.umich.edu advanceInst(fault); 6675348Ssaidi@eecs.umich.edu } 6685669Sgblack@eecs.umich.edu 6692623SN/A updateCycleCounts(); 6705669Sgblack@eecs.umich.edu updateCycleCounters(BaseCPU::CPU_STATE_ON); 6715669Sgblack@eecs.umich.edu} 6725712Shsul@eecs.umich.edu 6735894Sgblack@eecs.umich.edu 6745894Sgblack@eecs.umich.eduvoid 6755894Sgblack@eecs.umich.eduTimingSimpleCPU::advanceInst(const Fault &fault) 6762623SN/A{ 6775669Sgblack@eecs.umich.edu SimpleExecContext &t_info = *threadInfo[curThread]; 6785669Sgblack@eecs.umich.edu 6795894Sgblack@eecs.umich.edu if (_status == Faulting) 6805894Sgblack@eecs.umich.edu return; 6815894Sgblack@eecs.umich.edu 6825894Sgblack@eecs.umich.edu if (fault != NoFault) { 6835894Sgblack@eecs.umich.edu DPRINTF(SimpleCPU, "Fault occured. Handling the fault\n"); 6845894Sgblack@eecs.umich.edu 6855894Sgblack@eecs.umich.edu advancePC(fault); 6865894Sgblack@eecs.umich.edu 6875894Sgblack@eecs.umich.edu // A syscall fault could suspend this CPU (e.g., futex_wait) 6885894Sgblack@eecs.umich.edu // If the _status is not Idle, schedule an event to fetch the next 6895894Sgblack@eecs.umich.edu // instruction after 'stall' ticks. 6905894Sgblack@eecs.umich.edu // If the cpu has been suspended (i.e., _status == Idle), another 6915894Sgblack@eecs.umich.edu // cpu will wake this cpu up later. 6925894Sgblack@eecs.umich.edu if (_status != Idle) { 6935894Sgblack@eecs.umich.edu DPRINTF(SimpleCPU, "Scheduling fetch event after the Fault\n"); 6945894Sgblack@eecs.umich.edu 6955894Sgblack@eecs.umich.edu Tick stall = dynamic_pointer_cast<SyscallRetryFault>(fault) ? 6965894Sgblack@eecs.umich.edu clockEdge(syscallRetryLatency) : clockEdge(); 6975894Sgblack@eecs.umich.edu reschedule(fetchEvent, stall, true); 6985894Sgblack@eecs.umich.edu _status = Faulting; 6995894Sgblack@eecs.umich.edu } 7005894Sgblack@eecs.umich.edu 7015894Sgblack@eecs.umich.edu return; 7025894Sgblack@eecs.umich.edu } 7035894Sgblack@eecs.umich.edu 7045894Sgblack@eecs.umich.edu if (!t_info.stayAtPC) 7055894Sgblack@eecs.umich.edu advancePC(fault); 7062623SN/A 7073222Sktlim@umich.edu if (tryCompleteDrain()) 7085099Ssaidi@eecs.umich.edu return; 7093222Sktlim@umich.edu 7102623SN/A if (_status == BaseSimpleCPU::Running) { 7112623SN/A // kick off fetch of next instruction... callback from icache 7122623SN/A // response will cause that instruction to be executed, 7132623SN/A // keeping the CPU running. 7142644Sstever@eecs.umich.edu fetch(); 7152623SN/A } 7165726Sgblack@eecs.umich.edu} 7175726Sgblack@eecs.umich.edu 7182623SN/A 7192631SN/Avoid 7202631SN/ATimingSimpleCPU::completeIfetch(PacketPtr pkt) 7212631SN/A{ 7222631SN/A SimpleExecContext& t_info = *threadInfo[curThread]; 7232631SN/A 7242631SN/A DPRINTF(SimpleCPU, "Complete ICache Fetch for addr %#x\n", pkt ? 7252623SN/A pkt->getAddr() : 0); 7262623SN/A 7272623SN/A // received a response from the icache: execute the received 7282623SN/A // instruction 7293349Sbinkertn@umich.edu assert(!pkt || !pkt->isError()); 7302623SN/A assert(_status == IcacheWaitResponse); 7315221Ssaidi@eecs.umich.edu 7325221Ssaidi@eecs.umich.edu _status = BaseSimpleCPU::Running; 7332623SN/A 7342623SN/A updateCycleCounts(); 7355669Sgblack@eecs.umich.edu updateCycleCounters(BaseCPU::CPU_STATE_ON); 7365669Sgblack@eecs.umich.edu 7372623SN/A if (pkt) 7382798Sktlim@umich.edu pkt->req->setAccessLatency(); 7392623SN/A 7402644Sstever@eecs.umich.edu 7415099Ssaidi@eecs.umich.edu preExecute(); 7423222Sktlim@umich.edu if (curStaticInst && curStaticInst->isMemRef()) { 7433222Sktlim@umich.edu // load or store: just send to dcache 7442839Sktlim@umich.edu Fault fault = curStaticInst->initiateAcc(&t_info, traceData); 7455669Sgblack@eecs.umich.edu 7465669Sgblack@eecs.umich.edu // If we're not running now the instruction will complete in a dcache 7475669Sgblack@eecs.umich.edu // response callback or the instruction faulted and has started an 7485669Sgblack@eecs.umich.edu // ifetch 7493658Sktlim@umich.edu if (_status == BaseSimpleCPU::Running) { 7502839Sktlim@umich.edu if (fault != NoFault && traceData) { 7512798Sktlim@umich.edu // If there was a fault, we shouldn't trace this instruction. 7522798Sktlim@umich.edu delete traceData; 7532798Sktlim@umich.edu traceData = NULL; 7542623SN/A } 7555726Sgblack@eecs.umich.edu 7565726Sgblack@eecs.umich.edu postExecute(); 7572623SN/A // @todo remove me after debugging with legion done 7582623SN/A if (curStaticInst && (!curStaticInst->isMicroop() || 7593170Sstever@eecs.umich.edu curStaticInst->isFirstMicroop())) 7603170Sstever@eecs.umich.edu instCnt++; 7615894Sgblack@eecs.umich.edu advanceInst(fault); 7625894Sgblack@eecs.umich.edu } 7633170Sstever@eecs.umich.edu } else if (curStaticInst) { 7642644Sstever@eecs.umich.edu // non-memory instruction: execute completely now 7655894Sgblack@eecs.umich.edu Fault fault = curStaticInst->execute(&t_info, traceData); 7665001Sgblack@eecs.umich.edu 7675001Sgblack@eecs.umich.edu // keep an instruction count 7685001Sgblack@eecs.umich.edu if (fault == NoFault) 7693170Sstever@eecs.umich.edu countInst(); 7704998Sgblack@eecs.umich.edu else if (traceData && !DTRACE(ExecFaulting)) { 7712644Sstever@eecs.umich.edu delete traceData; 7725103Ssaidi@eecs.umich.edu traceData = NULL; 7735103Ssaidi@eecs.umich.edu } 7745103Ssaidi@eecs.umich.edu 7755103Ssaidi@eecs.umich.edu postExecute(); 7762644Sstever@eecs.umich.edu // @todo remove me after debugging with legion done 7772644Sstever@eecs.umich.edu if (curStaticInst && (!curStaticInst->isMicroop() || 7785726Sgblack@eecs.umich.edu curStaticInst->isFirstMicroop())) 7792623SN/A instCnt++; 7802623SN/A advanceInst(fault); 7814998Sgblack@eecs.umich.edu } else { 7824998Sgblack@eecs.umich.edu advanceInst(NoFault); 7834998Sgblack@eecs.umich.edu } 7844998Sgblack@eecs.umich.edu 7855001Sgblack@eecs.umich.edu if (pkt) { 7865001Sgblack@eecs.umich.edu delete pkt; 7875001Sgblack@eecs.umich.edu } 7885001Sgblack@eecs.umich.edu} 7895001Sgblack@eecs.umich.edu 7904998Sgblack@eecs.umich.eduvoid 7912644Sstever@eecs.umich.eduTimingSimpleCPU::IcachePort::ITickEvent::process() 7925103Ssaidi@eecs.umich.edu{ 7935103Ssaidi@eecs.umich.edu cpu->completeIfetch(pkt); 7945103Ssaidi@eecs.umich.edu} 7955103Ssaidi@eecs.umich.edu 7962644Sstever@eecs.umich.edubool 7975726Sgblack@eecs.umich.eduTimingSimpleCPU::IcachePort::recvTimingResp(PacketPtr pkt) 7985726Sgblack@eecs.umich.edu{ 7992623SN/A DPRINTF(SimpleCPU, "Received fetch response %#x\n", pkt->getAddr()); 8003658Sktlim@umich.edu // we should only ever see one response per cycle since we only 8015669Sgblack@eecs.umich.edu // issue a new request once this response is sunk 8025669Sgblack@eecs.umich.edu assert(!tickEvent.scheduled()); 8035669Sgblack@eecs.umich.edu // delay processing of returned data until next CPU clock edge 8045669Sgblack@eecs.umich.edu tickEvent.schedule(pkt, cpu->clockEdge()); 8052623SN/A 8062623SN/A return true; 8072948Ssaidi@eecs.umich.edu} 8082948Ssaidi@eecs.umich.edu 8092948Ssaidi@eecs.umich.eduvoid 8102948Ssaidi@eecs.umich.eduTimingSimpleCPU::IcachePort::recvReqRetry() 8112948Ssaidi@eecs.umich.edu{ 8122623SN/A // we shouldn't get a retry unless we have a packet that we're 8132623SN/A // waiting to transmit 8143349Sbinkertn@umich.edu assert(cpu->ifetch_pkt != NULL); 8152623SN/A assert(cpu->_status == IcacheRetry); 8164986Ssaidi@eecs.umich.edu PacketPtr tmp = cpu->ifetch_pkt; 8173310Srdreslin@umich.edu if (sendTimingReq(tmp)) { 8184584Ssaidi@eecs.umich.edu cpu->_status = IcacheWaitResponse; 8192948Ssaidi@eecs.umich.edu cpu->ifetch_pkt = NULL; 8203495Sktlim@umich.edu } 8213310Srdreslin@umich.edu} 8223310Srdreslin@umich.edu 8233495Sktlim@umich.eduvoid 8242948Ssaidi@eecs.umich.eduTimingSimpleCPU::completeDataAccess(PacketPtr pkt) 8253310Srdreslin@umich.edu{ 8263310Srdreslin@umich.edu // received a response from the dcache: complete the load or store 8274870Sstever@eecs.umich.edu // instruction 8284433Ssaidi@eecs.umich.edu assert(!pkt->isError()); 8294433Ssaidi@eecs.umich.edu assert(_status == DcacheWaitResponse || _status == DTBWaitResponse || 8304433Ssaidi@eecs.umich.edu pkt->req->getFlags().isSet(Request::NO_ACCESS)); 8314433Ssaidi@eecs.umich.edu 8324433Ssaidi@eecs.umich.edu pkt->req->setAccessLatency(); 8334433Ssaidi@eecs.umich.edu 8343310Srdreslin@umich.edu updateCycleCounts(); 8354433Ssaidi@eecs.umich.edu updateCycleCounters(BaseCPU::CPU_STATE_ON); 8364433Ssaidi@eecs.umich.edu 8372623SN/A if (pkt->senderState) { 8382623SN/A SplitFragmentSenderState * send_state = 8392657Ssaidi@eecs.umich.edu dynamic_cast<SplitFragmentSenderState *>(pkt->senderState); 8402623SN/A assert(send_state); 8412623SN/A delete pkt; 8422623SN/A PacketPtr big_pkt = send_state->bigPkt; 8432623SN/A delete send_state; 8442623SN/A 8452623SN/A SplitMainSenderState * main_send_state = 8463349Sbinkertn@umich.edu dynamic_cast<SplitMainSenderState *>(big_pkt->senderState); 8472657Ssaidi@eecs.umich.edu assert(main_send_state); 8482657Ssaidi@eecs.umich.edu // Record the fact that this packet is no longer outstanding. 8492657Ssaidi@eecs.umich.edu assert(main_send_state->outstanding != 0); 8502657Ssaidi@eecs.umich.edu main_send_state->outstanding--; 8512623SN/A 8522623SN/A if (main_send_state->outstanding) { 8532623SN/A return; 8543349Sbinkertn@umich.edu } else { 8552623SN/A delete main_send_state; 8562623SN/A big_pkt->senderState = NULL; 8572623SN/A pkt = big_pkt; 8584870Sstever@eecs.umich.edu } 8592623SN/A } 8605099Ssaidi@eecs.umich.edu 8613222Sktlim@umich.edu _status = BaseSimpleCPU::Running; 8623184Srdreslin@umich.edu 8635728Sgblack@eecs.umich.edu Fault fault = curStaticInst->completeAcc(pkt, threadInfo[curThread], 8645728Sgblack@eecs.umich.edu traceData); 8655728Sgblack@eecs.umich.edu 8665728Sgblack@eecs.umich.edu // keep an instruction count 8675728Sgblack@eecs.umich.edu if (fault == NoFault) 8685728Sgblack@eecs.umich.edu countInst(); 8695728Sgblack@eecs.umich.edu else if (traceData) { 8705728Sgblack@eecs.umich.edu // If there was a fault, we shouldn't trace this instruction. 8715728Sgblack@eecs.umich.edu delete traceData; 8725728Sgblack@eecs.umich.edu traceData = NULL; 8735728Sgblack@eecs.umich.edu } 8745728Sgblack@eecs.umich.edu 8755728Sgblack@eecs.umich.edu delete pkt; 8765728Sgblack@eecs.umich.edu 8775728Sgblack@eecs.umich.edu postExecute(); 8785728Sgblack@eecs.umich.edu 8795728Sgblack@eecs.umich.edu advanceInst(fault); 8805728Sgblack@eecs.umich.edu} 8815728Sgblack@eecs.umich.edu 8825728Sgblack@eecs.umich.eduvoid 8835728Sgblack@eecs.umich.eduTimingSimpleCPU::updateCycleCounts() 8845728Sgblack@eecs.umich.edu{ 8855728Sgblack@eecs.umich.edu const Cycles delta(curCycle() - previousCycle); 8865728Sgblack@eecs.umich.edu 8875728Sgblack@eecs.umich.edu numCycles += delta; 8885894Sgblack@eecs.umich.edu 8895728Sgblack@eecs.umich.edu previousCycle = curCycle(); 8905728Sgblack@eecs.umich.edu} 8912623SN/A 8922623SN/Avoid 8934998Sgblack@eecs.umich.eduTimingSimpleCPU::DcachePort::recvTimingSnoopReq(PacketPtr pkt) 8944998Sgblack@eecs.umich.edu{ 8954998Sgblack@eecs.umich.edu for (ThreadID tid = 0; tid < cpu->numThreads; tid++) { 8965001Sgblack@eecs.umich.edu if (cpu->getCpuAddrMonitor(tid)->doMonitor(pkt)) { 8975001Sgblack@eecs.umich.edu cpu->wakeup(tid); 8985001Sgblack@eecs.umich.edu } 8995001Sgblack@eecs.umich.edu } 9005001Sgblack@eecs.umich.edu 9014998Sgblack@eecs.umich.edu // Making it uniform across all CPUs: 9025507Sstever@gmail.com // The CPUs need to be woken up only on an invalidation packet (when using caches) 9035507Sstever@gmail.com // or on an incoming write packet (when not using caches) 9045507Sstever@gmail.com // It is not necessary to wake up the processor on all incoming packets 9053170Sstever@eecs.umich.edu if (pkt->isInvalidate() || pkt->isWrite()) { 9063170Sstever@eecs.umich.edu for (auto &t_info : cpu->threadInfo) { 9073170Sstever@eecs.umich.edu TheISA::handleLockedSnoop(t_info->thread, pkt, cacheBlockMask); 9082644Sstever@eecs.umich.edu } 9092644Sstever@eecs.umich.edu } 9102644Sstever@eecs.umich.edu} 9113184Srdreslin@umich.edu 9123227Sktlim@umich.eduvoid 9133201Shsul@eecs.umich.eduTimingSimpleCPU::DcachePort::recvFunctionalSnoop(PacketPtr pkt) 9143201Shsul@eecs.umich.edu{ 9153201Shsul@eecs.umich.edu for (ThreadID tid = 0; tid < cpu->numThreads; tid++) { 9163201Shsul@eecs.umich.edu if (cpu->getCpuAddrMonitor(tid)->doMonitor(pkt)) { 9173201Shsul@eecs.umich.edu cpu->wakeup(tid); 9183201Shsul@eecs.umich.edu } 9193201Shsul@eecs.umich.edu } 9202644Sstever@eecs.umich.edu} 9212623SN/A 9222623SN/Abool 9232623SN/ATimingSimpleCPU::DcachePort::recvTimingResp(PacketPtr pkt) 9242798Sktlim@umich.edu{ 9252839Sktlim@umich.edu DPRINTF(SimpleCPU, "Received load/store response %#x\n", pkt->getAddr()); 9262798Sktlim@umich.edu 9272839Sktlim@umich.edu // The timing CPU is not really ticked, instead it relies on the 9282901Ssaidi@eecs.umich.edu // memory system (fetch and load/store) to set the pace. 9292839Sktlim@umich.edu if (!tickEvent.scheduled()) { 9302798Sktlim@umich.edu // Delay processing of returned data until next CPU clock edge 9312623SN/A tickEvent.schedule(pkt, cpu->clockEdge()); 9324192Sktlim@umich.edu return true; 9334192Sktlim@umich.edu } else { 9344192Sktlim@umich.edu // In the case of a split transaction and a cache that is 9354192Sktlim@umich.edu // faster than a CPU we could get two responses in the 9364192Sktlim@umich.edu // same tick, delay the second one 9374192Sktlim@umich.edu if (!retryRespEvent.scheduled()) 9384192Sktlim@umich.edu cpu->schedule(retryRespEvent, cpu->clockEdge(Cycles(1))); 9394192Sktlim@umich.edu return false; 9405497Ssaidi@eecs.umich.edu } 9414192Sktlim@umich.edu} 9424192Sktlim@umich.edu 9434192Sktlim@umich.eduvoid 9442623SN/ATimingSimpleCPU::DcachePort::DTickEvent::process() 9453349Sbinkertn@umich.edu{ 9462623SN/A cpu->completeDataAccess(pkt); 9474986Ssaidi@eecs.umich.edu} 9483310Srdreslin@umich.edu 9494584Ssaidi@eecs.umich.eduvoid 9502948Ssaidi@eecs.umich.eduTimingSimpleCPU::DcachePort::recvReqRetry() 9515728Sgblack@eecs.umich.edu{ 9523310Srdreslin@umich.edu // we shouldn't get a retry unless we have a packet that we're 9535728Sgblack@eecs.umich.edu // waiting to transmit 9543495Sktlim@umich.edu assert(cpu->dcache_pkt != NULL); 9555728Sgblack@eecs.umich.edu assert(cpu->_status == DcacheRetry); 9562948Ssaidi@eecs.umich.edu PacketPtr tmp = cpu->dcache_pkt; 9573310Srdreslin@umich.edu if (tmp->senderState) { 9583310Srdreslin@umich.edu // This is a packet from a split access. 9594870Sstever@eecs.umich.edu SplitFragmentSenderState * send_state = 9604433Ssaidi@eecs.umich.edu dynamic_cast<SplitFragmentSenderState *>(tmp->senderState); 9614433Ssaidi@eecs.umich.edu assert(send_state); 9624433Ssaidi@eecs.umich.edu PacketPtr big_pkt = send_state->bigPkt; 9634433Ssaidi@eecs.umich.edu 9644433Ssaidi@eecs.umich.edu SplitMainSenderState * main_send_state = 9654433Ssaidi@eecs.umich.edu dynamic_cast<SplitMainSenderState *>(big_pkt->senderState); 9663310Srdreslin@umich.edu assert(main_send_state); 9674433Ssaidi@eecs.umich.edu 9684433Ssaidi@eecs.umich.edu if (sendTimingReq(tmp)) { 9692948Ssaidi@eecs.umich.edu // If we were able to send without retrying, record that fact 9702948Ssaidi@eecs.umich.edu // and try sending the other fragment. 9712948Ssaidi@eecs.umich.edu send_state->clearFromParent(); 9722948Ssaidi@eecs.umich.edu int other_index = main_send_state->getPendingFragment(); 9732948Ssaidi@eecs.umich.edu if (other_index > 0) { 9742630SN/A tmp = main_send_state->fragments[other_index]; 9752623SN/A cpu->dcache_pkt = tmp; 9762623SN/A if ((big_pkt->isRead() && cpu->handleReadPacket(tmp)) || 9772657Ssaidi@eecs.umich.edu (big_pkt->isWrite() && cpu->handleWritePacket())) { 9782623SN/A main_send_state->fragments[other_index] = NULL; 9792623SN/A } 9802623SN/A } else { 9812623SN/A cpu->_status = DcacheWaitResponse; 9822623SN/A // memory system takes ownership of packet 9832623SN/A cpu->dcache_pkt = NULL; 9843349Sbinkertn@umich.edu } 9855728Sgblack@eecs.umich.edu } 9865728Sgblack@eecs.umich.edu } else if (sendTimingReq(tmp)) { 9875728Sgblack@eecs.umich.edu cpu->_status = DcacheWaitResponse; 9885728Sgblack@eecs.umich.edu // memory system takes ownership of packet 9895728Sgblack@eecs.umich.edu cpu->dcache_pkt = NULL; 9905728Sgblack@eecs.umich.edu } 9915728Sgblack@eecs.umich.edu} 9925728Sgblack@eecs.umich.edu 9935728Sgblack@eecs.umich.eduTimingSimpleCPU::IprEvent::IprEvent(Packet *_pkt, TimingSimpleCPU *_cpu, 9945728Sgblack@eecs.umich.edu Tick t) 9955728Sgblack@eecs.umich.edu : pkt(_pkt), cpu(_cpu) 9965728Sgblack@eecs.umich.edu{ 9975728Sgblack@eecs.umich.edu cpu->schedule(this, t); 9985728Sgblack@eecs.umich.edu} 9995728Sgblack@eecs.umich.edu 10005728Sgblack@eecs.umich.eduvoid 10015728Sgblack@eecs.umich.eduTimingSimpleCPU::IprEvent::process() 10025728Sgblack@eecs.umich.edu{ 10035728Sgblack@eecs.umich.edu cpu->completeDataAccess(pkt); 10045728Sgblack@eecs.umich.edu} 10055728Sgblack@eecs.umich.edu 10065728Sgblack@eecs.umich.educonst char * 10075728Sgblack@eecs.umich.eduTimingSimpleCPU::IprEvent::description() const 10085728Sgblack@eecs.umich.edu{ 10095728Sgblack@eecs.umich.edu return "Timing Simple CPU Delay IPR event"; 10105728Sgblack@eecs.umich.edu} 10115728Sgblack@eecs.umich.edu 10125728Sgblack@eecs.umich.edu 10135728Sgblack@eecs.umich.eduvoid 10145728Sgblack@eecs.umich.eduTimingSimpleCPU::printAddr(Addr a) 10152657Ssaidi@eecs.umich.edu{ 10163170Sstever@eecs.umich.edu dcachePort.printAddr(a); 10172657Ssaidi@eecs.umich.edu} 10182657Ssaidi@eecs.umich.edu 10192623SN/A 10202623SN/A//////////////////////////////////////////////////////////////////////// 10215606Snate@binkert.org// 10225606Snate@binkert.org// TimingSimpleCPU Simulation Object 10235606Snate@binkert.org// 10245103Ssaidi@eecs.umich.eduTimingSimpleCPU * 10255606Snate@binkert.orgTimingSimpleCPUParams::create() 10265103Ssaidi@eecs.umich.edu{ 10275103Ssaidi@eecs.umich.edu return new TimingSimpleCPU(this); 10285103Ssaidi@eecs.umich.edu} 10295103Ssaidi@eecs.umich.edu