timing.cc revision 12749
12623SN/A/* 210596Sgabeblack@google.com * Copyright 2014 Google, Inc. 312276Sanouk.vanlaer@arm.com * Copyright (c) 2010-2013,2015,2017 ARM Limited 47725SAli.Saidi@ARM.com * All rights reserved 57725SAli.Saidi@ARM.com * 67725SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall 77725SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 87725SAli.Saidi@ARM.com * property including but not limited to intellectual property relating 97725SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software 107725SAli.Saidi@ARM.com * licensed hereunder. You may use the software subject to the license 117725SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated 127725SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software, 137725SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form. 147725SAli.Saidi@ARM.com * 152623SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 162623SN/A * All rights reserved. 172623SN/A * 182623SN/A * Redistribution and use in source and binary forms, with or without 192623SN/A * modification, are permitted provided that the following conditions are 202623SN/A * met: redistributions of source code must retain the above copyright 212623SN/A * notice, this list of conditions and the following disclaimer; 222623SN/A * redistributions in binary form must reproduce the above copyright 232623SN/A * notice, this list of conditions and the following disclaimer in the 242623SN/A * documentation and/or other materials provided with the distribution; 252623SN/A * neither the name of the copyright holders nor the names of its 262623SN/A * contributors may be used to endorse or promote products derived from 272623SN/A * this software without specific prior written permission. 282623SN/A * 292623SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 302623SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 312623SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 322623SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 332623SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 342623SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 352623SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 362623SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 372623SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 382623SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 392623SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402665Ssaidi@eecs.umich.edu * 412665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 422623SN/A */ 432623SN/A 4411793Sbrandon.potter@amd.com#include "cpu/simple/timing.hh" 4511793Sbrandon.potter@amd.com 463170Sstever@eecs.umich.edu#include "arch/locked_mem.hh" 478105Sgblack@eecs.umich.edu#include "arch/mmapped_ipr.hh" 482623SN/A#include "arch/utility.hh" 496658Snate@binkert.org#include "config/the_isa.hh" 502623SN/A#include "cpu/exetrace.hh" 518232Snate@binkert.org#include "debug/Config.hh" 529152Satgutier@umich.edu#include "debug/Drain.hh" 538232Snate@binkert.org#include "debug/ExecFaulting.hh" 5411793Sbrandon.potter@amd.com#include "debug/Mwait.hh" 558232Snate@binkert.org#include "debug/SimpleCPU.hh" 563348Sbinkertn@umich.edu#include "mem/packet.hh" 573348Sbinkertn@umich.edu#include "mem/packet_access.hh" 584762Snate@binkert.org#include "params/TimingSimpleCPU.hh" 597678Sgblack@eecs.umich.edu#include "sim/faults.hh" 608779Sgblack@eecs.umich.edu#include "sim/full_system.hh" 612901Ssaidi@eecs.umich.edu#include "sim/system.hh" 622623SN/A 632623SN/Ausing namespace std; 642623SN/Ausing namespace TheISA; 652623SN/A 662623SN/Avoid 672623SN/ATimingSimpleCPU::init() 682623SN/A{ 6911147Smitch.hayenga@arm.com BaseSimpleCPU::init(); 702623SN/A} 712623SN/A 722623SN/Avoid 738707Sandreas.hansson@arm.comTimingSimpleCPU::TimingCPUPort::TickEvent::schedule(PacketPtr _pkt, Tick t) 742948Ssaidi@eecs.umich.edu{ 752948Ssaidi@eecs.umich.edu pkt = _pkt; 765606Snate@binkert.org cpu->schedule(this, t); 772948Ssaidi@eecs.umich.edu} 782948Ssaidi@eecs.umich.edu 795529Snate@binkert.orgTimingSimpleCPU::TimingSimpleCPU(TimingSimpleCPUParams *p) 808707Sandreas.hansson@arm.com : BaseSimpleCPU(p), fetchTranslation(this), icachePort(this), 819179Sandreas.hansson@arm.com dcachePort(this), ifetch_pkt(NULL), dcache_pkt(NULL), previousCycle(0), 8212085Sspwilson2@wisc.edu fetchEvent([this]{ fetch(); }, name()) 832623SN/A{ 842623SN/A _status = Idle; 852623SN/A} 862623SN/A 872623SN/A 8810030SAli.Saidi@ARM.com 892623SN/ATimingSimpleCPU::~TimingSimpleCPU() 902623SN/A{ 912623SN/A} 922623SN/A 9310913Sandreas.sandberg@arm.comDrainState 9410913Sandreas.sandberg@arm.comTimingSimpleCPU::drain() 952798Sktlim@umich.edu{ 9612276Sanouk.vanlaer@arm.com // Deschedule any power gating event (if any) 9712276Sanouk.vanlaer@arm.com deschedulePowerGatingEvent(); 9812276Sanouk.vanlaer@arm.com 999448SAndreas.Sandberg@ARM.com if (switchedOut()) 10010913Sandreas.sandberg@arm.com return DrainState::Drained; 1019448SAndreas.Sandberg@ARM.com 1029342SAndreas.Sandberg@arm.com if (_status == Idle || 1039448SAndreas.Sandberg@ARM.com (_status == BaseSimpleCPU::Running && isDrained())) { 1049442SAndreas.Sandberg@ARM.com DPRINTF(Drain, "No need to drain.\n"); 10511147Smitch.hayenga@arm.com activeThreads.clear(); 10610913Sandreas.sandberg@arm.com return DrainState::Drained; 1072798Sktlim@umich.edu } else { 10811147Smitch.hayenga@arm.com DPRINTF(Drain, "Requesting drain.\n"); 1099442SAndreas.Sandberg@ARM.com 1109442SAndreas.Sandberg@ARM.com // The fetch event can become descheduled if a drain didn't 1119442SAndreas.Sandberg@ARM.com // succeed on the first attempt. We need to reschedule it if 1129442SAndreas.Sandberg@ARM.com // the CPU is waiting for a microcode routine to complete. 1139448SAndreas.Sandberg@ARM.com if (_status == BaseSimpleCPU::Running && !fetchEvent.scheduled()) 1149648Sdam.sunwoo@arm.com schedule(fetchEvent, clockEdge()); 1159442SAndreas.Sandberg@ARM.com 11610913Sandreas.sandberg@arm.com return DrainState::Draining; 1172798Sktlim@umich.edu } 1182623SN/A} 1192623SN/A 1202623SN/Avoid 1219342SAndreas.Sandberg@arm.comTimingSimpleCPU::drainResume() 1222623SN/A{ 1239442SAndreas.Sandberg@ARM.com assert(!fetchEvent.scheduled()); 1249448SAndreas.Sandberg@ARM.com if (switchedOut()) 1259448SAndreas.Sandberg@ARM.com return; 1269442SAndreas.Sandberg@ARM.com 1275221Ssaidi@eecs.umich.edu DPRINTF(SimpleCPU, "Resume\n"); 1289523SAndreas.Sandberg@ARM.com verifyMemoryMode(); 1293201Shsul@eecs.umich.edu 1309448SAndreas.Sandberg@ARM.com assert(!threadContexts.empty()); 1319448SAndreas.Sandberg@ARM.com 13211147Smitch.hayenga@arm.com _status = BaseSimpleCPU::Idle; 13311147Smitch.hayenga@arm.com 13411147Smitch.hayenga@arm.com for (ThreadID tid = 0; tid < numThreads; tid++) { 13511147Smitch.hayenga@arm.com if (threadInfo[tid]->thread->status() == ThreadContext::Active) { 13611147Smitch.hayenga@arm.com threadInfo[tid]->notIdleFraction = 1; 13711147Smitch.hayenga@arm.com 13811147Smitch.hayenga@arm.com activeThreads.push_back(tid); 13911147Smitch.hayenga@arm.com 14011147Smitch.hayenga@arm.com _status = BaseSimpleCPU::Running; 14111147Smitch.hayenga@arm.com 14211147Smitch.hayenga@arm.com // Fetch if any threads active 14311147Smitch.hayenga@arm.com if (!fetchEvent.scheduled()) { 14411147Smitch.hayenga@arm.com schedule(fetchEvent, nextCycle()); 14511147Smitch.hayenga@arm.com } 14611147Smitch.hayenga@arm.com } else { 14711147Smitch.hayenga@arm.com threadInfo[tid]->notIdleFraction = 0; 14811147Smitch.hayenga@arm.com } 1492623SN/A } 15011147Smitch.hayenga@arm.com 15112276Sanouk.vanlaer@arm.com // Reschedule any power gating event (if any) 15212276Sanouk.vanlaer@arm.com schedulePowerGatingEvent(); 15312276Sanouk.vanlaer@arm.com 15411147Smitch.hayenga@arm.com system->totalNumInsts = 0; 1559442SAndreas.Sandberg@ARM.com} 1562798Sktlim@umich.edu 1579442SAndreas.Sandberg@ARM.combool 1589442SAndreas.Sandberg@ARM.comTimingSimpleCPU::tryCompleteDrain() 1599442SAndreas.Sandberg@ARM.com{ 16010913Sandreas.sandberg@arm.com if (drainState() != DrainState::Draining) 1619442SAndreas.Sandberg@ARM.com return false; 1629442SAndreas.Sandberg@ARM.com 16311147Smitch.hayenga@arm.com DPRINTF(Drain, "tryCompleteDrain.\n"); 1649442SAndreas.Sandberg@ARM.com if (!isDrained()) 1659442SAndreas.Sandberg@ARM.com return false; 1669442SAndreas.Sandberg@ARM.com 1679442SAndreas.Sandberg@ARM.com DPRINTF(Drain, "CPU done draining, processing drain event\n"); 16810913Sandreas.sandberg@arm.com signalDrainDone(); 1699442SAndreas.Sandberg@ARM.com 1709442SAndreas.Sandberg@ARM.com return true; 1712798Sktlim@umich.edu} 1722798Sktlim@umich.edu 1732798Sktlim@umich.eduvoid 1742798Sktlim@umich.eduTimingSimpleCPU::switchOut() 1752798Sktlim@umich.edu{ 17611147Smitch.hayenga@arm.com SimpleExecContext& t_info = *threadInfo[curThread]; 17711147Smitch.hayenga@arm.com M5_VAR_USED SimpleThread* thread = t_info.thread; 17811147Smitch.hayenga@arm.com 1799429SAndreas.Sandberg@ARM.com BaseSimpleCPU::switchOut(); 1809429SAndreas.Sandberg@ARM.com 1819442SAndreas.Sandberg@ARM.com assert(!fetchEvent.scheduled()); 1829342SAndreas.Sandberg@arm.com assert(_status == BaseSimpleCPU::Running || _status == Idle); 18311147Smitch.hayenga@arm.com assert(!t_info.stayAtPC); 18411147Smitch.hayenga@arm.com assert(thread->microPC() == 0); 1859442SAndreas.Sandberg@ARM.com 18610464SAndreas.Sandberg@ARM.com updateCycleCounts(); 18712284Sjose.marinho@arm.com updateCycleCounters(BaseCPU::CPU_STATE_ON); 1882623SN/A} 1892623SN/A 1902623SN/A 1912623SN/Avoid 1922623SN/ATimingSimpleCPU::takeOverFrom(BaseCPU *oldCPU) 1932623SN/A{ 1949429SAndreas.Sandberg@ARM.com BaseSimpleCPU::takeOverFrom(oldCPU); 1952623SN/A 1969179Sandreas.hansson@arm.com previousCycle = curCycle(); 1972623SN/A} 1982623SN/A 1999523SAndreas.Sandberg@ARM.comvoid 2009523SAndreas.Sandberg@ARM.comTimingSimpleCPU::verifyMemoryMode() const 2019523SAndreas.Sandberg@ARM.com{ 2029524SAndreas.Sandberg@ARM.com if (!system->isTimingMode()) { 2039523SAndreas.Sandberg@ARM.com fatal("The timing CPU requires the memory system to be in " 2049523SAndreas.Sandberg@ARM.com "'timing' mode.\n"); 2059523SAndreas.Sandberg@ARM.com } 2069523SAndreas.Sandberg@ARM.com} 2072623SN/A 2082623SN/Avoid 20910407Smitch.hayenga@arm.comTimingSimpleCPU::activateContext(ThreadID thread_num) 2102623SN/A{ 21110407Smitch.hayenga@arm.com DPRINTF(SimpleCPU, "ActivateContext %d\n", thread_num); 2125221Ssaidi@eecs.umich.edu 21311147Smitch.hayenga@arm.com assert(thread_num < numThreads); 2142623SN/A 21511147Smitch.hayenga@arm.com threadInfo[thread_num]->notIdleFraction = 1; 21611147Smitch.hayenga@arm.com if (_status == BaseSimpleCPU::Idle) 21711147Smitch.hayenga@arm.com _status = BaseSimpleCPU::Running; 2183686Sktlim@umich.edu 2192623SN/A // kick things off by initiating the fetch of the next instruction 22011147Smitch.hayenga@arm.com if (!fetchEvent.scheduled()) 22111147Smitch.hayenga@arm.com schedule(fetchEvent, clockEdge(Cycles(0))); 22211147Smitch.hayenga@arm.com 22311147Smitch.hayenga@arm.com if (std::find(activeThreads.begin(), activeThreads.end(), thread_num) 22411147Smitch.hayenga@arm.com == activeThreads.end()) { 22511147Smitch.hayenga@arm.com activeThreads.push_back(thread_num); 22611147Smitch.hayenga@arm.com } 22711526Sdavid.guillen@arm.com 22811526Sdavid.guillen@arm.com BaseCPU::activateContext(thread_num); 2292623SN/A} 2302623SN/A 2312623SN/A 2322623SN/Avoid 2338737Skoansin.tan@gmail.comTimingSimpleCPU::suspendContext(ThreadID thread_num) 2342623SN/A{ 2355221Ssaidi@eecs.umich.edu DPRINTF(SimpleCPU, "SuspendContext %d\n", thread_num); 2365221Ssaidi@eecs.umich.edu 23711147Smitch.hayenga@arm.com assert(thread_num < numThreads); 23811147Smitch.hayenga@arm.com activeThreads.remove(thread_num); 2392623SN/A 2406043Sgblack@eecs.umich.edu if (_status == Idle) 2416043Sgblack@eecs.umich.edu return; 2426043Sgblack@eecs.umich.edu 2439342SAndreas.Sandberg@arm.com assert(_status == BaseSimpleCPU::Running); 2442623SN/A 24511147Smitch.hayenga@arm.com threadInfo[thread_num]->notIdleFraction = 0; 2462623SN/A 24711147Smitch.hayenga@arm.com if (activeThreads.empty()) { 24811147Smitch.hayenga@arm.com _status = Idle; 24911147Smitch.hayenga@arm.com 25011147Smitch.hayenga@arm.com if (fetchEvent.scheduled()) { 25111147Smitch.hayenga@arm.com deschedule(fetchEvent); 25211147Smitch.hayenga@arm.com } 25311147Smitch.hayenga@arm.com } 25411526Sdavid.guillen@arm.com 25511526Sdavid.guillen@arm.com BaseCPU::suspendContext(thread_num); 2562623SN/A} 2572623SN/A 2585728Sgblack@eecs.umich.edubool 2595728Sgblack@eecs.umich.eduTimingSimpleCPU::handleReadPacket(PacketPtr pkt) 2605728Sgblack@eecs.umich.edu{ 26111147Smitch.hayenga@arm.com SimpleExecContext &t_info = *threadInfo[curThread]; 26211147Smitch.hayenga@arm.com SimpleThread* thread = t_info.thread; 26311147Smitch.hayenga@arm.com 26412749Sgiacomo.travaglini@arm.com const RequestPtr &req = pkt->req; 26510533Sali.saidi@arm.com 26610533Sali.saidi@arm.com // We're about the issues a locked load, so tell the monitor 26710533Sali.saidi@arm.com // to start caring about this address 26810533Sali.saidi@arm.com if (pkt->isRead() && pkt->req->isLLSC()) { 26910533Sali.saidi@arm.com TheISA::handleLockedRead(thread, pkt->req); 27010533Sali.saidi@arm.com } 2718105Sgblack@eecs.umich.edu if (req->isMmappedIpr()) { 2729180Sandreas.hansson@arm.com Cycles delay = TheISA::handleIprRead(thread->getTC(), pkt); 2739179Sandreas.hansson@arm.com new IprEvent(pkt, this, clockEdge(delay)); 2745728Sgblack@eecs.umich.edu _status = DcacheWaitResponse; 2755728Sgblack@eecs.umich.edu dcache_pkt = NULL; 2768975Sandreas.hansson@arm.com } else if (!dcachePort.sendTimingReq(pkt)) { 2775728Sgblack@eecs.umich.edu _status = DcacheRetry; 2785728Sgblack@eecs.umich.edu dcache_pkt = pkt; 2795728Sgblack@eecs.umich.edu } else { 2805728Sgblack@eecs.umich.edu _status = DcacheWaitResponse; 2815728Sgblack@eecs.umich.edu // memory system takes ownership of packet 2825728Sgblack@eecs.umich.edu dcache_pkt = NULL; 2835728Sgblack@eecs.umich.edu } 2845728Sgblack@eecs.umich.edu return dcache_pkt == NULL; 2855728Sgblack@eecs.umich.edu} 2862623SN/A 2875894Sgblack@eecs.umich.eduvoid 28812749Sgiacomo.travaglini@arm.comTimingSimpleCPU::sendData(const RequestPtr &req, uint8_t *data, uint64_t *res, 2896973Stjones1@inf.ed.ac.uk bool read) 2905744Sgblack@eecs.umich.edu{ 29111147Smitch.hayenga@arm.com SimpleExecContext &t_info = *threadInfo[curThread]; 29211147Smitch.hayenga@arm.com SimpleThread* thread = t_info.thread; 29311147Smitch.hayenga@arm.com 29410653Sandreas.hansson@arm.com PacketPtr pkt = buildPacket(req, read); 29510566Sandreas.hansson@arm.com pkt->dataDynamic<uint8_t>(data); 2965894Sgblack@eecs.umich.edu if (req->getFlags().isSet(Request::NO_ACCESS)) { 2975894Sgblack@eecs.umich.edu assert(!dcache_pkt); 2985894Sgblack@eecs.umich.edu pkt->makeResponse(); 2995894Sgblack@eecs.umich.edu completeDataAccess(pkt); 3005894Sgblack@eecs.umich.edu } else if (read) { 3015894Sgblack@eecs.umich.edu handleReadPacket(pkt); 3025894Sgblack@eecs.umich.edu } else { 3035894Sgblack@eecs.umich.edu bool do_access = true; // flag to suppress cache access 3045894Sgblack@eecs.umich.edu 3056102Sgblack@eecs.umich.edu if (req->isLLSC()) { 30610030SAli.Saidi@ARM.com do_access = TheISA::handleLockedWrite(thread, req, dcachePort.cacheBlockMask); 3075894Sgblack@eecs.umich.edu } else if (req->isCondSwap()) { 3085894Sgblack@eecs.umich.edu assert(res); 3095894Sgblack@eecs.umich.edu req->setExtraData(*res); 3105894Sgblack@eecs.umich.edu } 3115894Sgblack@eecs.umich.edu 3125894Sgblack@eecs.umich.edu if (do_access) { 3135894Sgblack@eecs.umich.edu dcache_pkt = pkt; 3145894Sgblack@eecs.umich.edu handleWritePacket(); 31511148Smitch.hayenga@arm.com threadSnoop(pkt, curThread); 3165894Sgblack@eecs.umich.edu } else { 3175894Sgblack@eecs.umich.edu _status = DcacheWaitResponse; 3185894Sgblack@eecs.umich.edu completeDataAccess(pkt); 3195894Sgblack@eecs.umich.edu } 3205894Sgblack@eecs.umich.edu } 3215894Sgblack@eecs.umich.edu} 3225894Sgblack@eecs.umich.edu 3235894Sgblack@eecs.umich.eduvoid 32412749Sgiacomo.travaglini@arm.comTimingSimpleCPU::sendSplitData(const RequestPtr &req1, const RequestPtr &req2, 32512749Sgiacomo.travaglini@arm.com const RequestPtr &req, uint8_t *data, bool read) 3265894Sgblack@eecs.umich.edu{ 3275894Sgblack@eecs.umich.edu PacketPtr pkt1, pkt2; 3285894Sgblack@eecs.umich.edu buildSplitPacket(pkt1, pkt2, req1, req2, req, data, read); 3295894Sgblack@eecs.umich.edu if (req->getFlags().isSet(Request::NO_ACCESS)) { 3305894Sgblack@eecs.umich.edu assert(!dcache_pkt); 3315894Sgblack@eecs.umich.edu pkt1->makeResponse(); 3325894Sgblack@eecs.umich.edu completeDataAccess(pkt1); 3335894Sgblack@eecs.umich.edu } else if (read) { 3347911Shestness@cs.utexas.edu SplitFragmentSenderState * send_state = 3357911Shestness@cs.utexas.edu dynamic_cast<SplitFragmentSenderState *>(pkt1->senderState); 3365894Sgblack@eecs.umich.edu if (handleReadPacket(pkt1)) { 3375894Sgblack@eecs.umich.edu send_state->clearFromParent(); 3387911Shestness@cs.utexas.edu send_state = dynamic_cast<SplitFragmentSenderState *>( 3397911Shestness@cs.utexas.edu pkt2->senderState); 3405894Sgblack@eecs.umich.edu if (handleReadPacket(pkt2)) { 3415894Sgblack@eecs.umich.edu send_state->clearFromParent(); 3425894Sgblack@eecs.umich.edu } 3435894Sgblack@eecs.umich.edu } 3445894Sgblack@eecs.umich.edu } else { 3455894Sgblack@eecs.umich.edu dcache_pkt = pkt1; 3467911Shestness@cs.utexas.edu SplitFragmentSenderState * send_state = 3477911Shestness@cs.utexas.edu dynamic_cast<SplitFragmentSenderState *>(pkt1->senderState); 3485894Sgblack@eecs.umich.edu if (handleWritePacket()) { 3495894Sgblack@eecs.umich.edu send_state->clearFromParent(); 3505894Sgblack@eecs.umich.edu dcache_pkt = pkt2; 3517911Shestness@cs.utexas.edu send_state = dynamic_cast<SplitFragmentSenderState *>( 3527911Shestness@cs.utexas.edu pkt2->senderState); 3535894Sgblack@eecs.umich.edu if (handleWritePacket()) { 3545894Sgblack@eecs.umich.edu send_state->clearFromParent(); 3555894Sgblack@eecs.umich.edu } 3565894Sgblack@eecs.umich.edu } 3575894Sgblack@eecs.umich.edu } 3585894Sgblack@eecs.umich.edu} 3595894Sgblack@eecs.umich.edu 3605894Sgblack@eecs.umich.eduvoid 36110379Sandreas.hansson@arm.comTimingSimpleCPU::translationFault(const Fault &fault) 3625894Sgblack@eecs.umich.edu{ 3636739Sgblack@eecs.umich.edu // fault may be NoFault in cases where a fault is suppressed, 3646739Sgblack@eecs.umich.edu // for instance prefetches. 36510464SAndreas.Sandberg@ARM.com updateCycleCounts(); 36612284Sjose.marinho@arm.com updateCycleCounters(BaseCPU::CPU_STATE_ON); 3675894Sgblack@eecs.umich.edu 3685894Sgblack@eecs.umich.edu if (traceData) { 3695894Sgblack@eecs.umich.edu // Since there was a fault, we shouldn't trace this instruction. 3705894Sgblack@eecs.umich.edu delete traceData; 3715894Sgblack@eecs.umich.edu traceData = NULL; 3725744Sgblack@eecs.umich.edu } 3735744Sgblack@eecs.umich.edu 3745894Sgblack@eecs.umich.edu postExecute(); 3755894Sgblack@eecs.umich.edu 3769442SAndreas.Sandberg@ARM.com advanceInst(fault); 3775894Sgblack@eecs.umich.edu} 3785894Sgblack@eecs.umich.edu 37910653Sandreas.hansson@arm.comPacketPtr 38012749Sgiacomo.travaglini@arm.comTimingSimpleCPU::buildPacket(const RequestPtr &req, bool read) 3815894Sgblack@eecs.umich.edu{ 38210653Sandreas.hansson@arm.com return read ? Packet::createRead(req) : Packet::createWrite(req); 3835894Sgblack@eecs.umich.edu} 3845894Sgblack@eecs.umich.edu 3855894Sgblack@eecs.umich.eduvoid 3865894Sgblack@eecs.umich.eduTimingSimpleCPU::buildSplitPacket(PacketPtr &pkt1, PacketPtr &pkt2, 38712749Sgiacomo.travaglini@arm.com const RequestPtr &req1, const RequestPtr &req2, const RequestPtr &req, 3885894Sgblack@eecs.umich.edu uint8_t *data, bool read) 3895894Sgblack@eecs.umich.edu{ 3905894Sgblack@eecs.umich.edu pkt1 = pkt2 = NULL; 3915894Sgblack@eecs.umich.edu 3928105Sgblack@eecs.umich.edu assert(!req1->isMmappedIpr() && !req2->isMmappedIpr()); 3935744Sgblack@eecs.umich.edu 3945894Sgblack@eecs.umich.edu if (req->getFlags().isSet(Request::NO_ACCESS)) { 39510653Sandreas.hansson@arm.com pkt1 = buildPacket(req, read); 3965894Sgblack@eecs.umich.edu return; 3975894Sgblack@eecs.umich.edu } 3985894Sgblack@eecs.umich.edu 39910653Sandreas.hansson@arm.com pkt1 = buildPacket(req1, read); 40010653Sandreas.hansson@arm.com pkt2 = buildPacket(req2, read); 4015894Sgblack@eecs.umich.edu 4028949Sandreas.hansson@arm.com PacketPtr pkt = new Packet(req, pkt1->cmd.responseCommand()); 4035744Sgblack@eecs.umich.edu 40410566Sandreas.hansson@arm.com pkt->dataDynamic<uint8_t>(data); 4055744Sgblack@eecs.umich.edu pkt1->dataStatic<uint8_t>(data); 4065744Sgblack@eecs.umich.edu pkt2->dataStatic<uint8_t>(data + req1->getSize()); 4075744Sgblack@eecs.umich.edu 4085744Sgblack@eecs.umich.edu SplitMainSenderState * main_send_state = new SplitMainSenderState; 4095744Sgblack@eecs.umich.edu pkt->senderState = main_send_state; 4105744Sgblack@eecs.umich.edu main_send_state->fragments[0] = pkt1; 4115744Sgblack@eecs.umich.edu main_send_state->fragments[1] = pkt2; 4125744Sgblack@eecs.umich.edu main_send_state->outstanding = 2; 4135744Sgblack@eecs.umich.edu pkt1->senderState = new SplitFragmentSenderState(pkt, 0); 4145744Sgblack@eecs.umich.edu pkt2->senderState = new SplitFragmentSenderState(pkt, 1); 4155744Sgblack@eecs.umich.edu} 4165744Sgblack@eecs.umich.edu 4172623SN/AFault 4188444Sgblack@eecs.umich.eduTimingSimpleCPU::readMem(Addr addr, uint8_t *data, 41911608Snikos.nikoleris@arm.com unsigned size, Request::Flags flags) 4202623SN/A{ 42111303Ssteve.reinhardt@amd.com panic("readMem() is for atomic accesses, and should " 42211303Ssteve.reinhardt@amd.com "never be called on TimingSimpleCPU.\n"); 42311303Ssteve.reinhardt@amd.com} 42411303Ssteve.reinhardt@amd.com 42511303Ssteve.reinhardt@amd.comFault 42611608Snikos.nikoleris@arm.comTimingSimpleCPU::initiateMemRead(Addr addr, unsigned size, 42711608Snikos.nikoleris@arm.com Request::Flags flags) 42811303Ssteve.reinhardt@amd.com{ 42911147Smitch.hayenga@arm.com SimpleExecContext &t_info = *threadInfo[curThread]; 43011147Smitch.hayenga@arm.com SimpleThread* thread = t_info.thread; 43111147Smitch.hayenga@arm.com 4325728Sgblack@eecs.umich.edu Fault fault; 4335728Sgblack@eecs.umich.edu const int asid = 0; 4347720Sgblack@eecs.umich.edu const Addr pc = thread->instAddr(); 4359814Sandreas.hansson@arm.com unsigned block_size = cacheLineSize(); 4366973Stjones1@inf.ed.ac.uk BaseTLB::Mode mode = BaseTLB::Read; 4372623SN/A 43810665SAli.Saidi@ARM.com if (traceData) 43910665SAli.Saidi@ARM.com traceData->setMem(addr, size, flags); 4407045Ssteve.reinhardt@amd.com 44112749Sgiacomo.travaglini@arm.com RequestPtr req = std::make_shared<Request>( 44212749Sgiacomo.travaglini@arm.com asid, addr, size, flags, dataMasterId(), pc, 44312749Sgiacomo.travaglini@arm.com thread->contextId()); 4445728Sgblack@eecs.umich.edu 44510024Sdam.sunwoo@arm.com req->taskId(taskId()); 44610024Sdam.sunwoo@arm.com 4477520Sgblack@eecs.umich.edu Addr split_addr = roundDown(addr + size - 1, block_size); 4485744Sgblack@eecs.umich.edu assert(split_addr <= addr || split_addr - addr < block_size); 4495728Sgblack@eecs.umich.edu 4505894Sgblack@eecs.umich.edu _status = DTBWaitResponse; 4515744Sgblack@eecs.umich.edu if (split_addr > addr) { 4525894Sgblack@eecs.umich.edu RequestPtr req1, req2; 4536102Sgblack@eecs.umich.edu assert(!req->isLLSC() && !req->isSwap()); 4545894Sgblack@eecs.umich.edu req->splitOnVaddr(split_addr, req1, req2); 4555894Sgblack@eecs.umich.edu 4566973Stjones1@inf.ed.ac.uk WholeTranslationState *state = 4577520Sgblack@eecs.umich.edu new WholeTranslationState(req, req1, req2, new uint8_t[size], 4586973Stjones1@inf.ed.ac.uk NULL, mode); 4598486Sgblack@eecs.umich.edu DataTranslation<TimingSimpleCPU *> *trans1 = 4608486Sgblack@eecs.umich.edu new DataTranslation<TimingSimpleCPU *>(this, state, 0); 4618486Sgblack@eecs.umich.edu DataTranslation<TimingSimpleCPU *> *trans2 = 4628486Sgblack@eecs.umich.edu new DataTranslation<TimingSimpleCPU *>(this, state, 1); 4636973Stjones1@inf.ed.ac.uk 46411147Smitch.hayenga@arm.com thread->dtb->translateTiming(req1, thread->getTC(), trans1, mode); 46511147Smitch.hayenga@arm.com thread->dtb->translateTiming(req2, thread->getTC(), trans2, mode); 4665744Sgblack@eecs.umich.edu } else { 4676973Stjones1@inf.ed.ac.uk WholeTranslationState *state = 4687520Sgblack@eecs.umich.edu new WholeTranslationState(req, new uint8_t[size], NULL, mode); 4698486Sgblack@eecs.umich.edu DataTranslation<TimingSimpleCPU *> *translation 4708486Sgblack@eecs.umich.edu = new DataTranslation<TimingSimpleCPU *>(this, state); 47111147Smitch.hayenga@arm.com thread->dtb->translateTiming(req, thread->getTC(), translation, mode); 4722623SN/A } 4732623SN/A 4745728Sgblack@eecs.umich.edu return NoFault; 4752623SN/A} 4762623SN/A 4775728Sgblack@eecs.umich.edubool 4785728Sgblack@eecs.umich.eduTimingSimpleCPU::handleWritePacket() 4795728Sgblack@eecs.umich.edu{ 48011147Smitch.hayenga@arm.com SimpleExecContext &t_info = *threadInfo[curThread]; 48111147Smitch.hayenga@arm.com SimpleThread* thread = t_info.thread; 48211147Smitch.hayenga@arm.com 48312749Sgiacomo.travaglini@arm.com const RequestPtr &req = dcache_pkt->req; 4848105Sgblack@eecs.umich.edu if (req->isMmappedIpr()) { 4859180Sandreas.hansson@arm.com Cycles delay = TheISA::handleIprWrite(thread->getTC(), dcache_pkt); 4869179Sandreas.hansson@arm.com new IprEvent(dcache_pkt, this, clockEdge(delay)); 4875728Sgblack@eecs.umich.edu _status = DcacheWaitResponse; 4885728Sgblack@eecs.umich.edu dcache_pkt = NULL; 4898975Sandreas.hansson@arm.com } else if (!dcachePort.sendTimingReq(dcache_pkt)) { 4905728Sgblack@eecs.umich.edu _status = DcacheRetry; 4915728Sgblack@eecs.umich.edu } else { 4925728Sgblack@eecs.umich.edu _status = DcacheWaitResponse; 4935728Sgblack@eecs.umich.edu // memory system takes ownership of packet 4945728Sgblack@eecs.umich.edu dcache_pkt = NULL; 4955728Sgblack@eecs.umich.edu } 4965728Sgblack@eecs.umich.edu return dcache_pkt == NULL; 4975728Sgblack@eecs.umich.edu} 4982623SN/A 4992623SN/AFault 5008444Sgblack@eecs.umich.eduTimingSimpleCPU::writeMem(uint8_t *data, unsigned size, 50111608Snikos.nikoleris@arm.com Addr addr, Request::Flags flags, uint64_t *res) 5022623SN/A{ 50311147Smitch.hayenga@arm.com SimpleExecContext &t_info = *threadInfo[curThread]; 50411147Smitch.hayenga@arm.com SimpleThread* thread = t_info.thread; 50511147Smitch.hayenga@arm.com 5068443Sgblack@eecs.umich.edu uint8_t *newData = new uint8_t[size]; 5075728Sgblack@eecs.umich.edu const int asid = 0; 5087720Sgblack@eecs.umich.edu const Addr pc = thread->instAddr(); 5099814Sandreas.hansson@arm.com unsigned block_size = cacheLineSize(); 5106973Stjones1@inf.ed.ac.uk BaseTLB::Mode mode = BaseTLB::Write; 5113169Sstever@eecs.umich.edu 51210031SAli.Saidi@ARM.com if (data == NULL) { 51312355Snikos.nikoleris@arm.com assert(flags & Request::STORE_NO_DATA); 51410031SAli.Saidi@ARM.com // This must be a cache block cleaning request 51510031SAli.Saidi@ARM.com memset(newData, 0, size); 51610031SAli.Saidi@ARM.com } else { 51710031SAli.Saidi@ARM.com memcpy(newData, data, size); 51810031SAli.Saidi@ARM.com } 51910031SAli.Saidi@ARM.com 52010665SAli.Saidi@ARM.com if (traceData) 52110665SAli.Saidi@ARM.com traceData->setMem(addr, size, flags); 5227045Ssteve.reinhardt@amd.com 52312749Sgiacomo.travaglini@arm.com RequestPtr req = std::make_shared<Request>( 52412749Sgiacomo.travaglini@arm.com asid, addr, size, flags, dataMasterId(), pc, 52512749Sgiacomo.travaglini@arm.com thread->contextId()); 5265728Sgblack@eecs.umich.edu 52710024Sdam.sunwoo@arm.com req->taskId(taskId()); 52810024Sdam.sunwoo@arm.com 5297520Sgblack@eecs.umich.edu Addr split_addr = roundDown(addr + size - 1, block_size); 5305744Sgblack@eecs.umich.edu assert(split_addr <= addr || split_addr - addr < block_size); 5315728Sgblack@eecs.umich.edu 5325894Sgblack@eecs.umich.edu _status = DTBWaitResponse; 5335744Sgblack@eecs.umich.edu if (split_addr > addr) { 5345894Sgblack@eecs.umich.edu RequestPtr req1, req2; 5356102Sgblack@eecs.umich.edu assert(!req->isLLSC() && !req->isSwap()); 5365894Sgblack@eecs.umich.edu req->splitOnVaddr(split_addr, req1, req2); 5375894Sgblack@eecs.umich.edu 5386973Stjones1@inf.ed.ac.uk WholeTranslationState *state = 5398443Sgblack@eecs.umich.edu new WholeTranslationState(req, req1, req2, newData, res, mode); 5408486Sgblack@eecs.umich.edu DataTranslation<TimingSimpleCPU *> *trans1 = 5418486Sgblack@eecs.umich.edu new DataTranslation<TimingSimpleCPU *>(this, state, 0); 5428486Sgblack@eecs.umich.edu DataTranslation<TimingSimpleCPU *> *trans2 = 5438486Sgblack@eecs.umich.edu new DataTranslation<TimingSimpleCPU *>(this, state, 1); 5446973Stjones1@inf.ed.ac.uk 54511147Smitch.hayenga@arm.com thread->dtb->translateTiming(req1, thread->getTC(), trans1, mode); 54611147Smitch.hayenga@arm.com thread->dtb->translateTiming(req2, thread->getTC(), trans2, mode); 5475744Sgblack@eecs.umich.edu } else { 5486973Stjones1@inf.ed.ac.uk WholeTranslationState *state = 5498443Sgblack@eecs.umich.edu new WholeTranslationState(req, newData, res, mode); 5508486Sgblack@eecs.umich.edu DataTranslation<TimingSimpleCPU *> *translation = 5518486Sgblack@eecs.umich.edu new DataTranslation<TimingSimpleCPU *>(this, state); 55211147Smitch.hayenga@arm.com thread->dtb->translateTiming(req, thread->getTC(), translation, mode); 5532623SN/A } 5542623SN/A 5557045Ssteve.reinhardt@amd.com // Translation faults will be returned via finishTranslation() 5565728Sgblack@eecs.umich.edu return NoFault; 5572623SN/A} 5582623SN/A 55911148Smitch.hayenga@arm.comvoid 56011148Smitch.hayenga@arm.comTimingSimpleCPU::threadSnoop(PacketPtr pkt, ThreadID sender) 56111148Smitch.hayenga@arm.com{ 56211148Smitch.hayenga@arm.com for (ThreadID tid = 0; tid < numThreads; tid++) { 56311148Smitch.hayenga@arm.com if (tid != sender) { 56411321Ssteve.reinhardt@amd.com if (getCpuAddrMonitor(tid)->doMonitor(pkt)) { 56511151Smitch.hayenga@arm.com wakeup(tid); 56611148Smitch.hayenga@arm.com } 56711148Smitch.hayenga@arm.com TheISA::handleLockedSnoop(threadInfo[tid]->thread, pkt, 56811148Smitch.hayenga@arm.com dcachePort.cacheBlockMask); 56911148Smitch.hayenga@arm.com } 57011148Smitch.hayenga@arm.com } 57111148Smitch.hayenga@arm.com} 5722623SN/A 5732623SN/Avoid 5746973Stjones1@inf.ed.ac.ukTimingSimpleCPU::finishTranslation(WholeTranslationState *state) 5756973Stjones1@inf.ed.ac.uk{ 5769342SAndreas.Sandberg@arm.com _status = BaseSimpleCPU::Running; 5776973Stjones1@inf.ed.ac.uk 5786973Stjones1@inf.ed.ac.uk if (state->getFault() != NoFault) { 5796973Stjones1@inf.ed.ac.uk if (state->isPrefetch()) { 5806973Stjones1@inf.ed.ac.uk state->setNoFault(); 5816973Stjones1@inf.ed.ac.uk } 5827691SAli.Saidi@ARM.com delete [] state->data; 5836973Stjones1@inf.ed.ac.uk state->deleteReqs(); 5846973Stjones1@inf.ed.ac.uk translationFault(state->getFault()); 5856973Stjones1@inf.ed.ac.uk } else { 5866973Stjones1@inf.ed.ac.uk if (!state->isSplit) { 5876973Stjones1@inf.ed.ac.uk sendData(state->mainReq, state->data, state->res, 5886973Stjones1@inf.ed.ac.uk state->mode == BaseTLB::Read); 5896973Stjones1@inf.ed.ac.uk } else { 5906973Stjones1@inf.ed.ac.uk sendSplitData(state->sreqLow, state->sreqHigh, state->mainReq, 5916973Stjones1@inf.ed.ac.uk state->data, state->mode == BaseTLB::Read); 5926973Stjones1@inf.ed.ac.uk } 5936973Stjones1@inf.ed.ac.uk } 5946973Stjones1@inf.ed.ac.uk 5956973Stjones1@inf.ed.ac.uk delete state; 5966973Stjones1@inf.ed.ac.uk} 5976973Stjones1@inf.ed.ac.uk 5986973Stjones1@inf.ed.ac.uk 5996973Stjones1@inf.ed.ac.ukvoid 6002623SN/ATimingSimpleCPU::fetch() 6012623SN/A{ 60211147Smitch.hayenga@arm.com // Change thread if multi-threaded 60311147Smitch.hayenga@arm.com swapActiveThread(); 60411147Smitch.hayenga@arm.com 60511147Smitch.hayenga@arm.com SimpleExecContext &t_info = *threadInfo[curThread]; 60611147Smitch.hayenga@arm.com SimpleThread* thread = t_info.thread; 60711147Smitch.hayenga@arm.com 6085221Ssaidi@eecs.umich.edu DPRINTF(SimpleCPU, "Fetch\n"); 6095221Ssaidi@eecs.umich.edu 61010596Sgabeblack@google.com if (!curStaticInst || !curStaticInst->isDelayedCommit()) { 6113387Sgblack@eecs.umich.edu checkForInterrupts(); 61210596Sgabeblack@google.com checkPcEventQueue(); 61310596Sgabeblack@google.com } 6145348Ssaidi@eecs.umich.edu 6158143SAli.Saidi@ARM.com // We must have just got suspended by a PC event 6168143SAli.Saidi@ARM.com if (_status == Idle) 6178143SAli.Saidi@ARM.com return; 6188143SAli.Saidi@ARM.com 6197720Sgblack@eecs.umich.edu TheISA::PCState pcState = thread->pcState(); 62011147Smitch.hayenga@arm.com bool needToFetch = !isRomMicroPC(pcState.microPC()) && 62111147Smitch.hayenga@arm.com !curMacroStaticInst; 6222623SN/A 6237720Sgblack@eecs.umich.edu if (needToFetch) { 6249342SAndreas.Sandberg@arm.com _status = BaseSimpleCPU::Running; 62512749Sgiacomo.travaglini@arm.com RequestPtr ifetch_req = std::make_shared<Request>(); 62610024Sdam.sunwoo@arm.com ifetch_req->taskId(taskId()); 62711435Smitch.hayenga@arm.com ifetch_req->setContext(thread->contextId()); 6285894Sgblack@eecs.umich.edu setupFetchRequest(ifetch_req); 6298277SAli.Saidi@ARM.com DPRINTF(SimpleCPU, "Translating address %#x\n", ifetch_req->getVaddr()); 63011147Smitch.hayenga@arm.com thread->itb->translateTiming(ifetch_req, thread->getTC(), 63111147Smitch.hayenga@arm.com &fetchTranslation, BaseTLB::Execute); 6322623SN/A } else { 6335669Sgblack@eecs.umich.edu _status = IcacheWaitResponse; 6345669Sgblack@eecs.umich.edu completeIfetch(NULL); 6355894Sgblack@eecs.umich.edu 63610464SAndreas.Sandberg@ARM.com updateCycleCounts(); 63712284Sjose.marinho@arm.com updateCycleCounters(BaseCPU::CPU_STATE_ON); 6385894Sgblack@eecs.umich.edu } 6395894Sgblack@eecs.umich.edu} 6405894Sgblack@eecs.umich.edu 6415894Sgblack@eecs.umich.edu 6425894Sgblack@eecs.umich.eduvoid 64312749Sgiacomo.travaglini@arm.comTimingSimpleCPU::sendFetch(const Fault &fault, const RequestPtr &req, 64410379Sandreas.hansson@arm.com ThreadContext *tc) 6455894Sgblack@eecs.umich.edu{ 6465894Sgblack@eecs.umich.edu if (fault == NoFault) { 6478277SAli.Saidi@ARM.com DPRINTF(SimpleCPU, "Sending fetch for addr %#x(pa: %#x)\n", 6488277SAli.Saidi@ARM.com req->getVaddr(), req->getPaddr()); 6498949Sandreas.hansson@arm.com ifetch_pkt = new Packet(req, MemCmd::ReadReq); 6505894Sgblack@eecs.umich.edu ifetch_pkt->dataStatic(&inst); 6518277SAli.Saidi@ARM.com DPRINTF(SimpleCPU, " -- pkt addr: %#x\n", ifetch_pkt->getAddr()); 6525894Sgblack@eecs.umich.edu 6538975Sandreas.hansson@arm.com if (!icachePort.sendTimingReq(ifetch_pkt)) { 6545894Sgblack@eecs.umich.edu // Need to wait for retry 6555894Sgblack@eecs.umich.edu _status = IcacheRetry; 6565894Sgblack@eecs.umich.edu } else { 6575894Sgblack@eecs.umich.edu // Need to wait for cache to respond 6585894Sgblack@eecs.umich.edu _status = IcacheWaitResponse; 6595894Sgblack@eecs.umich.edu // ownership of packet transferred to memory system 6605894Sgblack@eecs.umich.edu ifetch_pkt = NULL; 6615894Sgblack@eecs.umich.edu } 6625894Sgblack@eecs.umich.edu } else { 6638277SAli.Saidi@ARM.com DPRINTF(SimpleCPU, "Translation of addr %#x faulted\n", req->getVaddr()); 6645894Sgblack@eecs.umich.edu // fetch fault: advance directly to next instruction (fault handler) 6659342SAndreas.Sandberg@arm.com _status = BaseSimpleCPU::Running; 6665894Sgblack@eecs.umich.edu advanceInst(fault); 6672623SN/A } 6683222Sktlim@umich.edu 66910464SAndreas.Sandberg@ARM.com updateCycleCounts(); 67012284Sjose.marinho@arm.com updateCycleCounters(BaseCPU::CPU_STATE_ON); 6712623SN/A} 6722623SN/A 6732623SN/A 6742623SN/Avoid 67510379Sandreas.hansson@arm.comTimingSimpleCPU::advanceInst(const Fault &fault) 6762623SN/A{ 67711147Smitch.hayenga@arm.com SimpleExecContext &t_info = *threadInfo[curThread]; 67811147Smitch.hayenga@arm.com 6798276SAli.Saidi@ARM.com if (_status == Faulting) 6808276SAli.Saidi@ARM.com return; 6818276SAli.Saidi@ARM.com 6828276SAli.Saidi@ARM.com if (fault != NoFault) { 68311877Sbrandon.potter@amd.com DPRINTF(SimpleCPU, "Fault occured, scheduling fetch event\n"); 68411877Sbrandon.potter@amd.com 6858276SAli.Saidi@ARM.com advancePC(fault); 68611877Sbrandon.potter@amd.com 68711877Sbrandon.potter@amd.com Tick stall = dynamic_pointer_cast<SyscallRetryFault>(fault) ? 68811877Sbrandon.potter@amd.com clockEdge(syscallRetryLatency) : clockEdge(); 68911877Sbrandon.potter@amd.com 69011877Sbrandon.potter@amd.com reschedule(fetchEvent, stall, true); 69111877Sbrandon.potter@amd.com 6928276SAli.Saidi@ARM.com _status = Faulting; 6938276SAli.Saidi@ARM.com return; 6948276SAli.Saidi@ARM.com } 6958276SAli.Saidi@ARM.com 6968276SAli.Saidi@ARM.com 69711147Smitch.hayenga@arm.com if (!t_info.stayAtPC) 6985726Sgblack@eecs.umich.edu advancePC(fault); 6992623SN/A 7009442SAndreas.Sandberg@ARM.com if (tryCompleteDrain()) 7019442SAndreas.Sandberg@ARM.com return; 7029442SAndreas.Sandberg@ARM.com 7039342SAndreas.Sandberg@arm.com if (_status == BaseSimpleCPU::Running) { 7042631SN/A // kick off fetch of next instruction... callback from icache 7052631SN/A // response will cause that instruction to be executed, 7062631SN/A // keeping the CPU running. 7072631SN/A fetch(); 7082631SN/A } 7092623SN/A} 7102623SN/A 7112623SN/A 7122623SN/Avoid 7133349Sbinkertn@umich.eduTimingSimpleCPU::completeIfetch(PacketPtr pkt) 7142623SN/A{ 71511147Smitch.hayenga@arm.com SimpleExecContext& t_info = *threadInfo[curThread]; 71611147Smitch.hayenga@arm.com 7178277SAli.Saidi@ARM.com DPRINTF(SimpleCPU, "Complete ICache Fetch for addr %#x\n", pkt ? 7188277SAli.Saidi@ARM.com pkt->getAddr() : 0); 7198277SAli.Saidi@ARM.com 7202623SN/A // received a response from the icache: execute the received 7212623SN/A // instruction 7225669Sgblack@eecs.umich.edu assert(!pkt || !pkt->isError()); 7232623SN/A assert(_status == IcacheWaitResponse); 7242798Sktlim@umich.edu 7259342SAndreas.Sandberg@arm.com _status = BaseSimpleCPU::Running; 7262644Sstever@eecs.umich.edu 72710464SAndreas.Sandberg@ARM.com updateCycleCounts(); 72812284Sjose.marinho@arm.com updateCycleCounters(BaseCPU::CPU_STATE_ON); 7293222Sktlim@umich.edu 73010020Smatt.horsnell@ARM.com if (pkt) 73110020Smatt.horsnell@ARM.com pkt->req->setAccessLatency(); 73210020Smatt.horsnell@ARM.com 73310020Smatt.horsnell@ARM.com 7342623SN/A preExecute(); 7357725SAli.Saidi@ARM.com if (curStaticInst && curStaticInst->isMemRef()) { 7362623SN/A // load or store: just send to dcache 73711147Smitch.hayenga@arm.com Fault fault = curStaticInst->initiateAcc(&t_info, traceData); 7387945SAli.Saidi@ARM.com 7397945SAli.Saidi@ARM.com // If we're not running now the instruction will complete in a dcache 7407945SAli.Saidi@ARM.com // response callback or the instruction faulted and has started an 7417945SAli.Saidi@ARM.com // ifetch 7429342SAndreas.Sandberg@arm.com if (_status == BaseSimpleCPU::Running) { 7435894Sgblack@eecs.umich.edu if (fault != NoFault && traceData) { 7445001Sgblack@eecs.umich.edu // If there was a fault, we shouldn't trace this instruction. 7455001Sgblack@eecs.umich.edu delete traceData; 7465001Sgblack@eecs.umich.edu traceData = NULL; 7473170Sstever@eecs.umich.edu } 7484998Sgblack@eecs.umich.edu 7492644Sstever@eecs.umich.edu postExecute(); 7505103Ssaidi@eecs.umich.edu // @todo remove me after debugging with legion done 7515103Ssaidi@eecs.umich.edu if (curStaticInst && (!curStaticInst->isMicroop() || 7525103Ssaidi@eecs.umich.edu curStaticInst->isFirstMicroop())) 7535103Ssaidi@eecs.umich.edu instCnt++; 7542644Sstever@eecs.umich.edu advanceInst(fault); 7552644Sstever@eecs.umich.edu } 7565726Sgblack@eecs.umich.edu } else if (curStaticInst) { 7572623SN/A // non-memory instruction: execute completely now 75811147Smitch.hayenga@arm.com Fault fault = curStaticInst->execute(&t_info, traceData); 7594998Sgblack@eecs.umich.edu 7604998Sgblack@eecs.umich.edu // keep an instruction count 7614998Sgblack@eecs.umich.edu if (fault == NoFault) 7624998Sgblack@eecs.umich.edu countInst(); 7637655Sali.saidi@arm.com else if (traceData && !DTRACE(ExecFaulting)) { 7645001Sgblack@eecs.umich.edu delete traceData; 7655001Sgblack@eecs.umich.edu traceData = NULL; 7665001Sgblack@eecs.umich.edu } 7674998Sgblack@eecs.umich.edu 7682644Sstever@eecs.umich.edu postExecute(); 7695103Ssaidi@eecs.umich.edu // @todo remove me after debugging with legion done 7705103Ssaidi@eecs.umich.edu if (curStaticInst && (!curStaticInst->isMicroop() || 77111147Smitch.hayenga@arm.com curStaticInst->isFirstMicroop())) 7725103Ssaidi@eecs.umich.edu instCnt++; 7732644Sstever@eecs.umich.edu advanceInst(fault); 7745726Sgblack@eecs.umich.edu } else { 7755726Sgblack@eecs.umich.edu advanceInst(NoFault); 7762623SN/A } 7773658Sktlim@umich.edu 7785669Sgblack@eecs.umich.edu if (pkt) { 7795669Sgblack@eecs.umich.edu delete pkt; 7805669Sgblack@eecs.umich.edu } 7812623SN/A} 7822623SN/A 7832948Ssaidi@eecs.umich.eduvoid 7842948Ssaidi@eecs.umich.eduTimingSimpleCPU::IcachePort::ITickEvent::process() 7852948Ssaidi@eecs.umich.edu{ 7862948Ssaidi@eecs.umich.edu cpu->completeIfetch(pkt); 7872948Ssaidi@eecs.umich.edu} 7882623SN/A 7892623SN/Abool 7908975Sandreas.hansson@arm.comTimingSimpleCPU::IcachePort::recvTimingResp(PacketPtr pkt) 7912623SN/A{ 79210669Sandreas.hansson@arm.com DPRINTF(SimpleCPU, "Received fetch response %#x\n", pkt->getAddr()); 79310669Sandreas.hansson@arm.com // we should only ever see one response per cycle since we only 79410669Sandreas.hansson@arm.com // issue a new request once this response is sunk 79510669Sandreas.hansson@arm.com assert(!tickEvent.scheduled()); 7969165Sandreas.hansson@arm.com // delay processing of returned data until next CPU clock edge 79710669Sandreas.hansson@arm.com tickEvent.schedule(pkt, cpu->clockEdge()); 7988948Sandreas.hansson@arm.com 7994433Ssaidi@eecs.umich.edu return true; 8002623SN/A} 8012623SN/A 8022657Ssaidi@eecs.umich.eduvoid 80310713Sandreas.hansson@arm.comTimingSimpleCPU::IcachePort::recvReqRetry() 8042623SN/A{ 8052623SN/A // we shouldn't get a retry unless we have a packet that we're 8062623SN/A // waiting to transmit 8072623SN/A assert(cpu->ifetch_pkt != NULL); 8082623SN/A assert(cpu->_status == IcacheRetry); 8093349Sbinkertn@umich.edu PacketPtr tmp = cpu->ifetch_pkt; 8108975Sandreas.hansson@arm.com if (sendTimingReq(tmp)) { 8112657Ssaidi@eecs.umich.edu cpu->_status = IcacheWaitResponse; 8122657Ssaidi@eecs.umich.edu cpu->ifetch_pkt = NULL; 8132657Ssaidi@eecs.umich.edu } 8142623SN/A} 8152623SN/A 8162623SN/Avoid 8173349Sbinkertn@umich.eduTimingSimpleCPU::completeDataAccess(PacketPtr pkt) 8182623SN/A{ 8192623SN/A // received a response from the dcache: complete the load or store 8202623SN/A // instruction 8214870Sstever@eecs.umich.edu assert(!pkt->isError()); 8227516Shestness@cs.utexas.edu assert(_status == DcacheWaitResponse || _status == DTBWaitResponse || 8237516Shestness@cs.utexas.edu pkt->req->getFlags().isSet(Request::NO_ACCESS)); 8242623SN/A 82510020Smatt.horsnell@ARM.com pkt->req->setAccessLatency(); 82610464SAndreas.Sandberg@ARM.com 82710464SAndreas.Sandberg@ARM.com updateCycleCounts(); 82812284Sjose.marinho@arm.com updateCycleCounters(BaseCPU::CPU_STATE_ON); 8293184Srdreslin@umich.edu 8305728Sgblack@eecs.umich.edu if (pkt->senderState) { 8315728Sgblack@eecs.umich.edu SplitFragmentSenderState * send_state = 8325728Sgblack@eecs.umich.edu dynamic_cast<SplitFragmentSenderState *>(pkt->senderState); 8335728Sgblack@eecs.umich.edu assert(send_state); 8345728Sgblack@eecs.umich.edu delete pkt; 8355728Sgblack@eecs.umich.edu PacketPtr big_pkt = send_state->bigPkt; 8365728Sgblack@eecs.umich.edu delete send_state; 83711320Ssteve.reinhardt@amd.com 8385728Sgblack@eecs.umich.edu SplitMainSenderState * main_send_state = 8395728Sgblack@eecs.umich.edu dynamic_cast<SplitMainSenderState *>(big_pkt->senderState); 8405728Sgblack@eecs.umich.edu assert(main_send_state); 8415728Sgblack@eecs.umich.edu // Record the fact that this packet is no longer outstanding. 8425728Sgblack@eecs.umich.edu assert(main_send_state->outstanding != 0); 8435728Sgblack@eecs.umich.edu main_send_state->outstanding--; 8445728Sgblack@eecs.umich.edu 8455728Sgblack@eecs.umich.edu if (main_send_state->outstanding) { 8465728Sgblack@eecs.umich.edu return; 8475728Sgblack@eecs.umich.edu } else { 8485728Sgblack@eecs.umich.edu delete main_send_state; 8495728Sgblack@eecs.umich.edu big_pkt->senderState = NULL; 8505728Sgblack@eecs.umich.edu pkt = big_pkt; 8515728Sgblack@eecs.umich.edu } 8525728Sgblack@eecs.umich.edu } 8535728Sgblack@eecs.umich.edu 8549342SAndreas.Sandberg@arm.com _status = BaseSimpleCPU::Running; 8555728Sgblack@eecs.umich.edu 85611147Smitch.hayenga@arm.com Fault fault = curStaticInst->completeAcc(pkt, threadInfo[curThread], 85711147Smitch.hayenga@arm.com traceData); 8582623SN/A 8594998Sgblack@eecs.umich.edu // keep an instruction count 8604998Sgblack@eecs.umich.edu if (fault == NoFault) 8614998Sgblack@eecs.umich.edu countInst(); 8625001Sgblack@eecs.umich.edu else if (traceData) { 8635001Sgblack@eecs.umich.edu // If there was a fault, we shouldn't trace this instruction. 8645001Sgblack@eecs.umich.edu delete traceData; 8655001Sgblack@eecs.umich.edu traceData = NULL; 8665001Sgblack@eecs.umich.edu } 8674998Sgblack@eecs.umich.edu 8682644Sstever@eecs.umich.edu delete pkt; 8692644Sstever@eecs.umich.edu 8703184Srdreslin@umich.edu postExecute(); 8713227Sktlim@umich.edu 8722644Sstever@eecs.umich.edu advanceInst(fault); 8732623SN/A} 8742623SN/A 87510030SAli.Saidi@ARM.comvoid 87610464SAndreas.Sandberg@ARM.comTimingSimpleCPU::updateCycleCounts() 87710464SAndreas.Sandberg@ARM.com{ 87810464SAndreas.Sandberg@ARM.com const Cycles delta(curCycle() - previousCycle); 87910464SAndreas.Sandberg@ARM.com 88010464SAndreas.Sandberg@ARM.com numCycles += delta; 88110464SAndreas.Sandberg@ARM.com 88210464SAndreas.Sandberg@ARM.com previousCycle = curCycle(); 88310464SAndreas.Sandberg@ARM.com} 88410464SAndreas.Sandberg@ARM.com 88510464SAndreas.Sandberg@ARM.comvoid 88610030SAli.Saidi@ARM.comTimingSimpleCPU::DcachePort::recvTimingSnoopReq(PacketPtr pkt) 88710030SAli.Saidi@ARM.com{ 88811148Smitch.hayenga@arm.com for (ThreadID tid = 0; tid < cpu->numThreads; tid++) { 88911148Smitch.hayenga@arm.com if (cpu->getCpuAddrMonitor(tid)->doMonitor(pkt)) { 89011151Smitch.hayenga@arm.com cpu->wakeup(tid); 89111148Smitch.hayenga@arm.com } 89210529Smorr@cs.wisc.edu } 89311147Smitch.hayenga@arm.com 89411356Skrinat01@arm.com // Making it uniform across all CPUs: 89511356Skrinat01@arm.com // The CPUs need to be woken up only on an invalidation packet (when using caches) 89611356Skrinat01@arm.com // or on an incoming write packet (when not using caches) 89711356Skrinat01@arm.com // It is not necessary to wake up the processor on all incoming packets 89811356Skrinat01@arm.com if (pkt->isInvalidate() || pkt->isWrite()) { 89911356Skrinat01@arm.com for (auto &t_info : cpu->threadInfo) { 90011356Skrinat01@arm.com TheISA::handleLockedSnoop(t_info->thread, pkt, cacheBlockMask); 90111356Skrinat01@arm.com } 90211147Smitch.hayenga@arm.com } 90310030SAli.Saidi@ARM.com} 90410030SAli.Saidi@ARM.com 90510529Smorr@cs.wisc.eduvoid 90610529Smorr@cs.wisc.eduTimingSimpleCPU::DcachePort::recvFunctionalSnoop(PacketPtr pkt) 90710529Smorr@cs.wisc.edu{ 90811148Smitch.hayenga@arm.com for (ThreadID tid = 0; tid < cpu->numThreads; tid++) { 90911321Ssteve.reinhardt@amd.com if (cpu->getCpuAddrMonitor(tid)->doMonitor(pkt)) { 91011151Smitch.hayenga@arm.com cpu->wakeup(tid); 91111148Smitch.hayenga@arm.com } 91210529Smorr@cs.wisc.edu } 91310529Smorr@cs.wisc.edu} 91410030SAli.Saidi@ARM.com 9152623SN/Abool 9168975Sandreas.hansson@arm.comTimingSimpleCPU::DcachePort::recvTimingResp(PacketPtr pkt) 9172623SN/A{ 91810669Sandreas.hansson@arm.com DPRINTF(SimpleCPU, "Received load/store response %#x\n", pkt->getAddr()); 9192948Ssaidi@eecs.umich.edu 92010669Sandreas.hansson@arm.com // The timing CPU is not really ticked, instead it relies on the 92110669Sandreas.hansson@arm.com // memory system (fetch and load/store) to set the pace. 92210669Sandreas.hansson@arm.com if (!tickEvent.scheduled()) { 92310669Sandreas.hansson@arm.com // Delay processing of returned data until next CPU clock edge 92410669Sandreas.hansson@arm.com tickEvent.schedule(pkt, cpu->clockEdge()); 92510669Sandreas.hansson@arm.com return true; 9269165Sandreas.hansson@arm.com } else { 92710669Sandreas.hansson@arm.com // In the case of a split transaction and a cache that is 92810669Sandreas.hansson@arm.com // faster than a CPU we could get two responses in the 92910669Sandreas.hansson@arm.com // same tick, delay the second one 93010713Sandreas.hansson@arm.com if (!retryRespEvent.scheduled()) 93110713Sandreas.hansson@arm.com cpu->schedule(retryRespEvent, cpu->clockEdge(Cycles(1))); 93210669Sandreas.hansson@arm.com return false; 9333310Srdreslin@umich.edu } 9342948Ssaidi@eecs.umich.edu} 9352948Ssaidi@eecs.umich.edu 9362948Ssaidi@eecs.umich.eduvoid 9372948Ssaidi@eecs.umich.eduTimingSimpleCPU::DcachePort::DTickEvent::process() 9382948Ssaidi@eecs.umich.edu{ 9392630SN/A cpu->completeDataAccess(pkt); 9402623SN/A} 9412623SN/A 9422657Ssaidi@eecs.umich.eduvoid 94310713Sandreas.hansson@arm.comTimingSimpleCPU::DcachePort::recvReqRetry() 9442623SN/A{ 9452623SN/A // we shouldn't get a retry unless we have a packet that we're 9462623SN/A // waiting to transmit 9472623SN/A assert(cpu->dcache_pkt != NULL); 9482623SN/A assert(cpu->_status == DcacheRetry); 9493349Sbinkertn@umich.edu PacketPtr tmp = cpu->dcache_pkt; 9505728Sgblack@eecs.umich.edu if (tmp->senderState) { 9515728Sgblack@eecs.umich.edu // This is a packet from a split access. 9525728Sgblack@eecs.umich.edu SplitFragmentSenderState * send_state = 9535728Sgblack@eecs.umich.edu dynamic_cast<SplitFragmentSenderState *>(tmp->senderState); 9545728Sgblack@eecs.umich.edu assert(send_state); 9555728Sgblack@eecs.umich.edu PacketPtr big_pkt = send_state->bigPkt; 95611320Ssteve.reinhardt@amd.com 9575728Sgblack@eecs.umich.edu SplitMainSenderState * main_send_state = 9585728Sgblack@eecs.umich.edu dynamic_cast<SplitMainSenderState *>(big_pkt->senderState); 9595728Sgblack@eecs.umich.edu assert(main_send_state); 9605728Sgblack@eecs.umich.edu 9618975Sandreas.hansson@arm.com if (sendTimingReq(tmp)) { 9625728Sgblack@eecs.umich.edu // If we were able to send without retrying, record that fact 9635728Sgblack@eecs.umich.edu // and try sending the other fragment. 9645728Sgblack@eecs.umich.edu send_state->clearFromParent(); 9655728Sgblack@eecs.umich.edu int other_index = main_send_state->getPendingFragment(); 9665728Sgblack@eecs.umich.edu if (other_index > 0) { 9675728Sgblack@eecs.umich.edu tmp = main_send_state->fragments[other_index]; 9685728Sgblack@eecs.umich.edu cpu->dcache_pkt = tmp; 9695728Sgblack@eecs.umich.edu if ((big_pkt->isRead() && cpu->handleReadPacket(tmp)) || 9705728Sgblack@eecs.umich.edu (big_pkt->isWrite() && cpu->handleWritePacket())) { 9715728Sgblack@eecs.umich.edu main_send_state->fragments[other_index] = NULL; 9725728Sgblack@eecs.umich.edu } 9735728Sgblack@eecs.umich.edu } else { 9745728Sgblack@eecs.umich.edu cpu->_status = DcacheWaitResponse; 9755728Sgblack@eecs.umich.edu // memory system takes ownership of packet 9765728Sgblack@eecs.umich.edu cpu->dcache_pkt = NULL; 9775728Sgblack@eecs.umich.edu } 9785728Sgblack@eecs.umich.edu } 9798975Sandreas.hansson@arm.com } else if (sendTimingReq(tmp)) { 9802657Ssaidi@eecs.umich.edu cpu->_status = DcacheWaitResponse; 9813170Sstever@eecs.umich.edu // memory system takes ownership of packet 9822657Ssaidi@eecs.umich.edu cpu->dcache_pkt = NULL; 9832657Ssaidi@eecs.umich.edu } 9842623SN/A} 9852623SN/A 9865606Snate@binkert.orgTimingSimpleCPU::IprEvent::IprEvent(Packet *_pkt, TimingSimpleCPU *_cpu, 9875606Snate@binkert.org Tick t) 9885606Snate@binkert.org : pkt(_pkt), cpu(_cpu) 9895103Ssaidi@eecs.umich.edu{ 9905606Snate@binkert.org cpu->schedule(this, t); 9915103Ssaidi@eecs.umich.edu} 9925103Ssaidi@eecs.umich.edu 9935103Ssaidi@eecs.umich.eduvoid 9945103Ssaidi@eecs.umich.eduTimingSimpleCPU::IprEvent::process() 9955103Ssaidi@eecs.umich.edu{ 9965103Ssaidi@eecs.umich.edu cpu->completeDataAccess(pkt); 9975103Ssaidi@eecs.umich.edu} 9985103Ssaidi@eecs.umich.edu 9995103Ssaidi@eecs.umich.educonst char * 10005336Shines@cs.fsu.eduTimingSimpleCPU::IprEvent::description() const 10015103Ssaidi@eecs.umich.edu{ 10025103Ssaidi@eecs.umich.edu return "Timing Simple CPU Delay IPR event"; 10035103Ssaidi@eecs.umich.edu} 10045103Ssaidi@eecs.umich.edu 10052623SN/A 10065315Sstever@gmail.comvoid 10075315Sstever@gmail.comTimingSimpleCPU::printAddr(Addr a) 10085315Sstever@gmail.com{ 10095315Sstever@gmail.com dcachePort.printAddr(a); 10105315Sstever@gmail.com} 10115315Sstever@gmail.com 10125315Sstever@gmail.com 10132623SN/A//////////////////////////////////////////////////////////////////////// 10142623SN/A// 10152623SN/A// TimingSimpleCPU Simulation Object 10162623SN/A// 10174762Snate@binkert.orgTimingSimpleCPU * 10184762Snate@binkert.orgTimingSimpleCPUParams::create() 10192623SN/A{ 10205529Snate@binkert.org return new TimingSimpleCPU(this); 10212623SN/A} 1022