timing.cc revision 12276
12623SN/A/* 210596Sgabeblack@google.com * Copyright 2014 Google, Inc. 312276Sanouk.vanlaer@arm.com * Copyright (c) 2010-2013,2015,2017 ARM Limited 47725SAli.Saidi@ARM.com * All rights reserved 57725SAli.Saidi@ARM.com * 67725SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall 77725SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 87725SAli.Saidi@ARM.com * property including but not limited to intellectual property relating 97725SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software 107725SAli.Saidi@ARM.com * licensed hereunder. You may use the software subject to the license 117725SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated 127725SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software, 137725SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form. 147725SAli.Saidi@ARM.com * 152623SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 162623SN/A * All rights reserved. 172623SN/A * 182623SN/A * Redistribution and use in source and binary forms, with or without 192623SN/A * modification, are permitted provided that the following conditions are 202623SN/A * met: redistributions of source code must retain the above copyright 212623SN/A * notice, this list of conditions and the following disclaimer; 222623SN/A * redistributions in binary form must reproduce the above copyright 232623SN/A * notice, this list of conditions and the following disclaimer in the 242623SN/A * documentation and/or other materials provided with the distribution; 252623SN/A * neither the name of the copyright holders nor the names of its 262623SN/A * contributors may be used to endorse or promote products derived from 272623SN/A * this software without specific prior written permission. 282623SN/A * 292623SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 302623SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 312623SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 322623SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 332623SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 342623SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 352623SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 362623SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 372623SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 382623SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 392623SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402665Ssaidi@eecs.umich.edu * 412665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 422623SN/A */ 432623SN/A 4411793Sbrandon.potter@amd.com#include "cpu/simple/timing.hh" 4511793Sbrandon.potter@amd.com 463170Sstever@eecs.umich.edu#include "arch/locked_mem.hh" 478105Sgblack@eecs.umich.edu#include "arch/mmapped_ipr.hh" 482623SN/A#include "arch/utility.hh" 494040Ssaidi@eecs.umich.edu#include "base/bigint.hh" 506658Snate@binkert.org#include "config/the_isa.hh" 512623SN/A#include "cpu/exetrace.hh" 528232Snate@binkert.org#include "debug/Config.hh" 539152Satgutier@umich.edu#include "debug/Drain.hh" 548232Snate@binkert.org#include "debug/ExecFaulting.hh" 5511793Sbrandon.potter@amd.com#include "debug/Mwait.hh" 568232Snate@binkert.org#include "debug/SimpleCPU.hh" 573348Sbinkertn@umich.edu#include "mem/packet.hh" 583348Sbinkertn@umich.edu#include "mem/packet_access.hh" 594762Snate@binkert.org#include "params/TimingSimpleCPU.hh" 607678Sgblack@eecs.umich.edu#include "sim/faults.hh" 618779Sgblack@eecs.umich.edu#include "sim/full_system.hh" 622901Ssaidi@eecs.umich.edu#include "sim/system.hh" 632623SN/A 642623SN/Ausing namespace std; 652623SN/Ausing namespace TheISA; 662623SN/A 672623SN/Avoid 682623SN/ATimingSimpleCPU::init() 692623SN/A{ 7011147Smitch.hayenga@arm.com BaseSimpleCPU::init(); 712623SN/A} 722623SN/A 732623SN/Avoid 748707Sandreas.hansson@arm.comTimingSimpleCPU::TimingCPUPort::TickEvent::schedule(PacketPtr _pkt, Tick t) 752948Ssaidi@eecs.umich.edu{ 762948Ssaidi@eecs.umich.edu pkt = _pkt; 775606Snate@binkert.org cpu->schedule(this, t); 782948Ssaidi@eecs.umich.edu} 792948Ssaidi@eecs.umich.edu 805529Snate@binkert.orgTimingSimpleCPU::TimingSimpleCPU(TimingSimpleCPUParams *p) 818707Sandreas.hansson@arm.com : BaseSimpleCPU(p), fetchTranslation(this), icachePort(this), 829179Sandreas.hansson@arm.com dcachePort(this), ifetch_pkt(NULL), dcache_pkt(NULL), previousCycle(0), 8312085Sspwilson2@wisc.edu fetchEvent([this]{ fetch(); }, name()) 842623SN/A{ 852623SN/A _status = Idle; 862623SN/A} 872623SN/A 882623SN/A 8910030SAli.Saidi@ARM.com 902623SN/ATimingSimpleCPU::~TimingSimpleCPU() 912623SN/A{ 922623SN/A} 932623SN/A 9410913Sandreas.sandberg@arm.comDrainState 9510913Sandreas.sandberg@arm.comTimingSimpleCPU::drain() 962798Sktlim@umich.edu{ 9712276Sanouk.vanlaer@arm.com // Deschedule any power gating event (if any) 9812276Sanouk.vanlaer@arm.com deschedulePowerGatingEvent(); 9912276Sanouk.vanlaer@arm.com 1009448SAndreas.Sandberg@ARM.com if (switchedOut()) 10110913Sandreas.sandberg@arm.com return DrainState::Drained; 1029448SAndreas.Sandberg@ARM.com 1039342SAndreas.Sandberg@arm.com if (_status == Idle || 1049448SAndreas.Sandberg@ARM.com (_status == BaseSimpleCPU::Running && isDrained())) { 1059442SAndreas.Sandberg@ARM.com DPRINTF(Drain, "No need to drain.\n"); 10611147Smitch.hayenga@arm.com activeThreads.clear(); 10710913Sandreas.sandberg@arm.com return DrainState::Drained; 1082798Sktlim@umich.edu } else { 10911147Smitch.hayenga@arm.com DPRINTF(Drain, "Requesting drain.\n"); 1109442SAndreas.Sandberg@ARM.com 1119442SAndreas.Sandberg@ARM.com // The fetch event can become descheduled if a drain didn't 1129442SAndreas.Sandberg@ARM.com // succeed on the first attempt. We need to reschedule it if 1139442SAndreas.Sandberg@ARM.com // the CPU is waiting for a microcode routine to complete. 1149448SAndreas.Sandberg@ARM.com if (_status == BaseSimpleCPU::Running && !fetchEvent.scheduled()) 1159648Sdam.sunwoo@arm.com schedule(fetchEvent, clockEdge()); 1169442SAndreas.Sandberg@ARM.com 11710913Sandreas.sandberg@arm.com return DrainState::Draining; 1182798Sktlim@umich.edu } 1192623SN/A} 1202623SN/A 1212623SN/Avoid 1229342SAndreas.Sandberg@arm.comTimingSimpleCPU::drainResume() 1232623SN/A{ 1249442SAndreas.Sandberg@ARM.com assert(!fetchEvent.scheduled()); 1259448SAndreas.Sandberg@ARM.com if (switchedOut()) 1269448SAndreas.Sandberg@ARM.com return; 1279442SAndreas.Sandberg@ARM.com 1285221Ssaidi@eecs.umich.edu DPRINTF(SimpleCPU, "Resume\n"); 1299523SAndreas.Sandberg@ARM.com verifyMemoryMode(); 1303201Shsul@eecs.umich.edu 1319448SAndreas.Sandberg@ARM.com assert(!threadContexts.empty()); 1329448SAndreas.Sandberg@ARM.com 13311147Smitch.hayenga@arm.com _status = BaseSimpleCPU::Idle; 13411147Smitch.hayenga@arm.com 13511147Smitch.hayenga@arm.com for (ThreadID tid = 0; tid < numThreads; tid++) { 13611147Smitch.hayenga@arm.com if (threadInfo[tid]->thread->status() == ThreadContext::Active) { 13711147Smitch.hayenga@arm.com threadInfo[tid]->notIdleFraction = 1; 13811147Smitch.hayenga@arm.com 13911147Smitch.hayenga@arm.com activeThreads.push_back(tid); 14011147Smitch.hayenga@arm.com 14111147Smitch.hayenga@arm.com _status = BaseSimpleCPU::Running; 14211147Smitch.hayenga@arm.com 14311147Smitch.hayenga@arm.com // Fetch if any threads active 14411147Smitch.hayenga@arm.com if (!fetchEvent.scheduled()) { 14511147Smitch.hayenga@arm.com schedule(fetchEvent, nextCycle()); 14611147Smitch.hayenga@arm.com } 14711147Smitch.hayenga@arm.com } else { 14811147Smitch.hayenga@arm.com threadInfo[tid]->notIdleFraction = 0; 14911147Smitch.hayenga@arm.com } 1502623SN/A } 15111147Smitch.hayenga@arm.com 15212276Sanouk.vanlaer@arm.com // Reschedule any power gating event (if any) 15312276Sanouk.vanlaer@arm.com schedulePowerGatingEvent(); 15412276Sanouk.vanlaer@arm.com 15511147Smitch.hayenga@arm.com system->totalNumInsts = 0; 1569442SAndreas.Sandberg@ARM.com} 1572798Sktlim@umich.edu 1589442SAndreas.Sandberg@ARM.combool 1599442SAndreas.Sandberg@ARM.comTimingSimpleCPU::tryCompleteDrain() 1609442SAndreas.Sandberg@ARM.com{ 16110913Sandreas.sandberg@arm.com if (drainState() != DrainState::Draining) 1629442SAndreas.Sandberg@ARM.com return false; 1639442SAndreas.Sandberg@ARM.com 16411147Smitch.hayenga@arm.com DPRINTF(Drain, "tryCompleteDrain.\n"); 1659442SAndreas.Sandberg@ARM.com if (!isDrained()) 1669442SAndreas.Sandberg@ARM.com return false; 1679442SAndreas.Sandberg@ARM.com 1689442SAndreas.Sandberg@ARM.com DPRINTF(Drain, "CPU done draining, processing drain event\n"); 16910913Sandreas.sandberg@arm.com signalDrainDone(); 1709442SAndreas.Sandberg@ARM.com 1719442SAndreas.Sandberg@ARM.com return true; 1722798Sktlim@umich.edu} 1732798Sktlim@umich.edu 1742798Sktlim@umich.eduvoid 1752798Sktlim@umich.eduTimingSimpleCPU::switchOut() 1762798Sktlim@umich.edu{ 17711147Smitch.hayenga@arm.com SimpleExecContext& t_info = *threadInfo[curThread]; 17811147Smitch.hayenga@arm.com M5_VAR_USED SimpleThread* thread = t_info.thread; 17911147Smitch.hayenga@arm.com 1809429SAndreas.Sandberg@ARM.com BaseSimpleCPU::switchOut(); 1819429SAndreas.Sandberg@ARM.com 1829442SAndreas.Sandberg@ARM.com assert(!fetchEvent.scheduled()); 1839342SAndreas.Sandberg@arm.com assert(_status == BaseSimpleCPU::Running || _status == Idle); 18411147Smitch.hayenga@arm.com assert(!t_info.stayAtPC); 18511147Smitch.hayenga@arm.com assert(thread->microPC() == 0); 1869442SAndreas.Sandberg@ARM.com 18710464SAndreas.Sandberg@ARM.com updateCycleCounts(); 1882623SN/A} 1892623SN/A 1902623SN/A 1912623SN/Avoid 1922623SN/ATimingSimpleCPU::takeOverFrom(BaseCPU *oldCPU) 1932623SN/A{ 1949429SAndreas.Sandberg@ARM.com BaseSimpleCPU::takeOverFrom(oldCPU); 1952623SN/A 1969179Sandreas.hansson@arm.com previousCycle = curCycle(); 1972623SN/A} 1982623SN/A 1999523SAndreas.Sandberg@ARM.comvoid 2009523SAndreas.Sandberg@ARM.comTimingSimpleCPU::verifyMemoryMode() const 2019523SAndreas.Sandberg@ARM.com{ 2029524SAndreas.Sandberg@ARM.com if (!system->isTimingMode()) { 2039523SAndreas.Sandberg@ARM.com fatal("The timing CPU requires the memory system to be in " 2049523SAndreas.Sandberg@ARM.com "'timing' mode.\n"); 2059523SAndreas.Sandberg@ARM.com } 2069523SAndreas.Sandberg@ARM.com} 2072623SN/A 2082623SN/Avoid 20910407Smitch.hayenga@arm.comTimingSimpleCPU::activateContext(ThreadID thread_num) 2102623SN/A{ 21110407Smitch.hayenga@arm.com DPRINTF(SimpleCPU, "ActivateContext %d\n", thread_num); 2125221Ssaidi@eecs.umich.edu 21311147Smitch.hayenga@arm.com assert(thread_num < numThreads); 2142623SN/A 21511147Smitch.hayenga@arm.com threadInfo[thread_num]->notIdleFraction = 1; 21611147Smitch.hayenga@arm.com if (_status == BaseSimpleCPU::Idle) 21711147Smitch.hayenga@arm.com _status = BaseSimpleCPU::Running; 2183686Sktlim@umich.edu 2192623SN/A // kick things off by initiating the fetch of the next instruction 22011147Smitch.hayenga@arm.com if (!fetchEvent.scheduled()) 22111147Smitch.hayenga@arm.com schedule(fetchEvent, clockEdge(Cycles(0))); 22211147Smitch.hayenga@arm.com 22311147Smitch.hayenga@arm.com if (std::find(activeThreads.begin(), activeThreads.end(), thread_num) 22411147Smitch.hayenga@arm.com == activeThreads.end()) { 22511147Smitch.hayenga@arm.com activeThreads.push_back(thread_num); 22611147Smitch.hayenga@arm.com } 22711526Sdavid.guillen@arm.com 22811526Sdavid.guillen@arm.com BaseCPU::activateContext(thread_num); 2292623SN/A} 2302623SN/A 2312623SN/A 2322623SN/Avoid 2338737Skoansin.tan@gmail.comTimingSimpleCPU::suspendContext(ThreadID thread_num) 2342623SN/A{ 2355221Ssaidi@eecs.umich.edu DPRINTF(SimpleCPU, "SuspendContext %d\n", thread_num); 2365221Ssaidi@eecs.umich.edu 23711147Smitch.hayenga@arm.com assert(thread_num < numThreads); 23811147Smitch.hayenga@arm.com activeThreads.remove(thread_num); 2392623SN/A 2406043Sgblack@eecs.umich.edu if (_status == Idle) 2416043Sgblack@eecs.umich.edu return; 2426043Sgblack@eecs.umich.edu 2439342SAndreas.Sandberg@arm.com assert(_status == BaseSimpleCPU::Running); 2442623SN/A 24511147Smitch.hayenga@arm.com threadInfo[thread_num]->notIdleFraction = 0; 2462623SN/A 24711147Smitch.hayenga@arm.com if (activeThreads.empty()) { 24811147Smitch.hayenga@arm.com _status = Idle; 24911147Smitch.hayenga@arm.com 25011147Smitch.hayenga@arm.com if (fetchEvent.scheduled()) { 25111147Smitch.hayenga@arm.com deschedule(fetchEvent); 25211147Smitch.hayenga@arm.com } 25311147Smitch.hayenga@arm.com } 25411526Sdavid.guillen@arm.com 25511526Sdavid.guillen@arm.com BaseCPU::suspendContext(thread_num); 2562623SN/A} 2572623SN/A 2585728Sgblack@eecs.umich.edubool 2595728Sgblack@eecs.umich.eduTimingSimpleCPU::handleReadPacket(PacketPtr pkt) 2605728Sgblack@eecs.umich.edu{ 26111147Smitch.hayenga@arm.com SimpleExecContext &t_info = *threadInfo[curThread]; 26211147Smitch.hayenga@arm.com SimpleThread* thread = t_info.thread; 26311147Smitch.hayenga@arm.com 2645728Sgblack@eecs.umich.edu RequestPtr req = pkt->req; 26510533Sali.saidi@arm.com 26610533Sali.saidi@arm.com // We're about the issues a locked load, so tell the monitor 26710533Sali.saidi@arm.com // to start caring about this address 26810533Sali.saidi@arm.com if (pkt->isRead() && pkt->req->isLLSC()) { 26910533Sali.saidi@arm.com TheISA::handleLockedRead(thread, pkt->req); 27010533Sali.saidi@arm.com } 2718105Sgblack@eecs.umich.edu if (req->isMmappedIpr()) { 2729180Sandreas.hansson@arm.com Cycles delay = TheISA::handleIprRead(thread->getTC(), pkt); 2739179Sandreas.hansson@arm.com new IprEvent(pkt, this, clockEdge(delay)); 2745728Sgblack@eecs.umich.edu _status = DcacheWaitResponse; 2755728Sgblack@eecs.umich.edu dcache_pkt = NULL; 2768975Sandreas.hansson@arm.com } else if (!dcachePort.sendTimingReq(pkt)) { 2775728Sgblack@eecs.umich.edu _status = DcacheRetry; 2785728Sgblack@eecs.umich.edu dcache_pkt = pkt; 2795728Sgblack@eecs.umich.edu } else { 2805728Sgblack@eecs.umich.edu _status = DcacheWaitResponse; 2815728Sgblack@eecs.umich.edu // memory system takes ownership of packet 2825728Sgblack@eecs.umich.edu dcache_pkt = NULL; 2835728Sgblack@eecs.umich.edu } 2845728Sgblack@eecs.umich.edu return dcache_pkt == NULL; 2855728Sgblack@eecs.umich.edu} 2862623SN/A 2875894Sgblack@eecs.umich.eduvoid 2886973Stjones1@inf.ed.ac.ukTimingSimpleCPU::sendData(RequestPtr req, uint8_t *data, uint64_t *res, 2896973Stjones1@inf.ed.ac.uk bool read) 2905744Sgblack@eecs.umich.edu{ 29111147Smitch.hayenga@arm.com SimpleExecContext &t_info = *threadInfo[curThread]; 29211147Smitch.hayenga@arm.com SimpleThread* thread = t_info.thread; 29311147Smitch.hayenga@arm.com 29410653Sandreas.hansson@arm.com PacketPtr pkt = buildPacket(req, read); 29510566Sandreas.hansson@arm.com pkt->dataDynamic<uint8_t>(data); 2965894Sgblack@eecs.umich.edu if (req->getFlags().isSet(Request::NO_ACCESS)) { 2975894Sgblack@eecs.umich.edu assert(!dcache_pkt); 2985894Sgblack@eecs.umich.edu pkt->makeResponse(); 2995894Sgblack@eecs.umich.edu completeDataAccess(pkt); 3005894Sgblack@eecs.umich.edu } else if (read) { 3015894Sgblack@eecs.umich.edu handleReadPacket(pkt); 3025894Sgblack@eecs.umich.edu } else { 3035894Sgblack@eecs.umich.edu bool do_access = true; // flag to suppress cache access 3045894Sgblack@eecs.umich.edu 3056102Sgblack@eecs.umich.edu if (req->isLLSC()) { 30610030SAli.Saidi@ARM.com do_access = TheISA::handleLockedWrite(thread, req, dcachePort.cacheBlockMask); 3075894Sgblack@eecs.umich.edu } else if (req->isCondSwap()) { 3085894Sgblack@eecs.umich.edu assert(res); 3095894Sgblack@eecs.umich.edu req->setExtraData(*res); 3105894Sgblack@eecs.umich.edu } 3115894Sgblack@eecs.umich.edu 3125894Sgblack@eecs.umich.edu if (do_access) { 3135894Sgblack@eecs.umich.edu dcache_pkt = pkt; 3145894Sgblack@eecs.umich.edu handleWritePacket(); 31511148Smitch.hayenga@arm.com threadSnoop(pkt, curThread); 3165894Sgblack@eecs.umich.edu } else { 3175894Sgblack@eecs.umich.edu _status = DcacheWaitResponse; 3185894Sgblack@eecs.umich.edu completeDataAccess(pkt); 3195894Sgblack@eecs.umich.edu } 3205894Sgblack@eecs.umich.edu } 3215894Sgblack@eecs.umich.edu} 3225894Sgblack@eecs.umich.edu 3235894Sgblack@eecs.umich.eduvoid 3246973Stjones1@inf.ed.ac.ukTimingSimpleCPU::sendSplitData(RequestPtr req1, RequestPtr req2, 3256973Stjones1@inf.ed.ac.uk RequestPtr req, uint8_t *data, bool read) 3265894Sgblack@eecs.umich.edu{ 3275894Sgblack@eecs.umich.edu PacketPtr pkt1, pkt2; 3285894Sgblack@eecs.umich.edu buildSplitPacket(pkt1, pkt2, req1, req2, req, data, read); 3295894Sgblack@eecs.umich.edu if (req->getFlags().isSet(Request::NO_ACCESS)) { 3305894Sgblack@eecs.umich.edu assert(!dcache_pkt); 3315894Sgblack@eecs.umich.edu pkt1->makeResponse(); 3325894Sgblack@eecs.umich.edu completeDataAccess(pkt1); 3335894Sgblack@eecs.umich.edu } else if (read) { 3347911Shestness@cs.utexas.edu SplitFragmentSenderState * send_state = 3357911Shestness@cs.utexas.edu dynamic_cast<SplitFragmentSenderState *>(pkt1->senderState); 3365894Sgblack@eecs.umich.edu if (handleReadPacket(pkt1)) { 3375894Sgblack@eecs.umich.edu send_state->clearFromParent(); 3387911Shestness@cs.utexas.edu send_state = dynamic_cast<SplitFragmentSenderState *>( 3397911Shestness@cs.utexas.edu pkt2->senderState); 3405894Sgblack@eecs.umich.edu if (handleReadPacket(pkt2)) { 3415894Sgblack@eecs.umich.edu send_state->clearFromParent(); 3425894Sgblack@eecs.umich.edu } 3435894Sgblack@eecs.umich.edu } 3445894Sgblack@eecs.umich.edu } else { 3455894Sgblack@eecs.umich.edu dcache_pkt = pkt1; 3467911Shestness@cs.utexas.edu SplitFragmentSenderState * send_state = 3477911Shestness@cs.utexas.edu dynamic_cast<SplitFragmentSenderState *>(pkt1->senderState); 3485894Sgblack@eecs.umich.edu if (handleWritePacket()) { 3495894Sgblack@eecs.umich.edu send_state->clearFromParent(); 3505894Sgblack@eecs.umich.edu dcache_pkt = pkt2; 3517911Shestness@cs.utexas.edu send_state = dynamic_cast<SplitFragmentSenderState *>( 3527911Shestness@cs.utexas.edu pkt2->senderState); 3535894Sgblack@eecs.umich.edu if (handleWritePacket()) { 3545894Sgblack@eecs.umich.edu send_state->clearFromParent(); 3555894Sgblack@eecs.umich.edu } 3565894Sgblack@eecs.umich.edu } 3575894Sgblack@eecs.umich.edu } 3585894Sgblack@eecs.umich.edu} 3595894Sgblack@eecs.umich.edu 3605894Sgblack@eecs.umich.eduvoid 36110379Sandreas.hansson@arm.comTimingSimpleCPU::translationFault(const Fault &fault) 3625894Sgblack@eecs.umich.edu{ 3636739Sgblack@eecs.umich.edu // fault may be NoFault in cases where a fault is suppressed, 3646739Sgblack@eecs.umich.edu // for instance prefetches. 36510464SAndreas.Sandberg@ARM.com updateCycleCounts(); 3665894Sgblack@eecs.umich.edu 3675894Sgblack@eecs.umich.edu if (traceData) { 3685894Sgblack@eecs.umich.edu // Since there was a fault, we shouldn't trace this instruction. 3695894Sgblack@eecs.umich.edu delete traceData; 3705894Sgblack@eecs.umich.edu traceData = NULL; 3715744Sgblack@eecs.umich.edu } 3725744Sgblack@eecs.umich.edu 3735894Sgblack@eecs.umich.edu postExecute(); 3745894Sgblack@eecs.umich.edu 3759442SAndreas.Sandberg@ARM.com advanceInst(fault); 3765894Sgblack@eecs.umich.edu} 3775894Sgblack@eecs.umich.edu 37810653Sandreas.hansson@arm.comPacketPtr 37910653Sandreas.hansson@arm.comTimingSimpleCPU::buildPacket(RequestPtr req, bool read) 3805894Sgblack@eecs.umich.edu{ 38110653Sandreas.hansson@arm.com return read ? Packet::createRead(req) : Packet::createWrite(req); 3825894Sgblack@eecs.umich.edu} 3835894Sgblack@eecs.umich.edu 3845894Sgblack@eecs.umich.eduvoid 3855894Sgblack@eecs.umich.eduTimingSimpleCPU::buildSplitPacket(PacketPtr &pkt1, PacketPtr &pkt2, 3865894Sgblack@eecs.umich.edu RequestPtr req1, RequestPtr req2, RequestPtr req, 3875894Sgblack@eecs.umich.edu uint8_t *data, bool read) 3885894Sgblack@eecs.umich.edu{ 3895894Sgblack@eecs.umich.edu pkt1 = pkt2 = NULL; 3905894Sgblack@eecs.umich.edu 3918105Sgblack@eecs.umich.edu assert(!req1->isMmappedIpr() && !req2->isMmappedIpr()); 3925744Sgblack@eecs.umich.edu 3935894Sgblack@eecs.umich.edu if (req->getFlags().isSet(Request::NO_ACCESS)) { 39410653Sandreas.hansson@arm.com pkt1 = buildPacket(req, read); 3955894Sgblack@eecs.umich.edu return; 3965894Sgblack@eecs.umich.edu } 3975894Sgblack@eecs.umich.edu 39810653Sandreas.hansson@arm.com pkt1 = buildPacket(req1, read); 39910653Sandreas.hansson@arm.com pkt2 = buildPacket(req2, read); 4005894Sgblack@eecs.umich.edu 4018949Sandreas.hansson@arm.com PacketPtr pkt = new Packet(req, pkt1->cmd.responseCommand()); 4025744Sgblack@eecs.umich.edu 40310566Sandreas.hansson@arm.com pkt->dataDynamic<uint8_t>(data); 4045744Sgblack@eecs.umich.edu pkt1->dataStatic<uint8_t>(data); 4055744Sgblack@eecs.umich.edu pkt2->dataStatic<uint8_t>(data + req1->getSize()); 4065744Sgblack@eecs.umich.edu 4075744Sgblack@eecs.umich.edu SplitMainSenderState * main_send_state = new SplitMainSenderState; 4085744Sgblack@eecs.umich.edu pkt->senderState = main_send_state; 4095744Sgblack@eecs.umich.edu main_send_state->fragments[0] = pkt1; 4105744Sgblack@eecs.umich.edu main_send_state->fragments[1] = pkt2; 4115744Sgblack@eecs.umich.edu main_send_state->outstanding = 2; 4125744Sgblack@eecs.umich.edu pkt1->senderState = new SplitFragmentSenderState(pkt, 0); 4135744Sgblack@eecs.umich.edu pkt2->senderState = new SplitFragmentSenderState(pkt, 1); 4145744Sgblack@eecs.umich.edu} 4155744Sgblack@eecs.umich.edu 4162623SN/AFault 4178444Sgblack@eecs.umich.eduTimingSimpleCPU::readMem(Addr addr, uint8_t *data, 41811608Snikos.nikoleris@arm.com unsigned size, Request::Flags flags) 4192623SN/A{ 42011303Ssteve.reinhardt@amd.com panic("readMem() is for atomic accesses, and should " 42111303Ssteve.reinhardt@amd.com "never be called on TimingSimpleCPU.\n"); 42211303Ssteve.reinhardt@amd.com} 42311303Ssteve.reinhardt@amd.com 42411303Ssteve.reinhardt@amd.comFault 42511608Snikos.nikoleris@arm.comTimingSimpleCPU::initiateMemRead(Addr addr, unsigned size, 42611608Snikos.nikoleris@arm.com Request::Flags flags) 42711303Ssteve.reinhardt@amd.com{ 42811147Smitch.hayenga@arm.com SimpleExecContext &t_info = *threadInfo[curThread]; 42911147Smitch.hayenga@arm.com SimpleThread* thread = t_info.thread; 43011147Smitch.hayenga@arm.com 4315728Sgblack@eecs.umich.edu Fault fault; 4325728Sgblack@eecs.umich.edu const int asid = 0; 4337720Sgblack@eecs.umich.edu const Addr pc = thread->instAddr(); 4349814Sandreas.hansson@arm.com unsigned block_size = cacheLineSize(); 4356973Stjones1@inf.ed.ac.uk BaseTLB::Mode mode = BaseTLB::Read; 4362623SN/A 43710665SAli.Saidi@ARM.com if (traceData) 43810665SAli.Saidi@ARM.com traceData->setMem(addr, size, flags); 4397045Ssteve.reinhardt@amd.com 44011435Smitch.hayenga@arm.com RequestPtr req = new Request(asid, addr, size, flags, dataMasterId(), pc, 44111435Smitch.hayenga@arm.com thread->contextId()); 4425728Sgblack@eecs.umich.edu 44310024Sdam.sunwoo@arm.com req->taskId(taskId()); 44410024Sdam.sunwoo@arm.com 4457520Sgblack@eecs.umich.edu Addr split_addr = roundDown(addr + size - 1, block_size); 4465744Sgblack@eecs.umich.edu assert(split_addr <= addr || split_addr - addr < block_size); 4475728Sgblack@eecs.umich.edu 4485894Sgblack@eecs.umich.edu _status = DTBWaitResponse; 4495744Sgblack@eecs.umich.edu if (split_addr > addr) { 4505894Sgblack@eecs.umich.edu RequestPtr req1, req2; 4516102Sgblack@eecs.umich.edu assert(!req->isLLSC() && !req->isSwap()); 4525894Sgblack@eecs.umich.edu req->splitOnVaddr(split_addr, req1, req2); 4535894Sgblack@eecs.umich.edu 4546973Stjones1@inf.ed.ac.uk WholeTranslationState *state = 4557520Sgblack@eecs.umich.edu new WholeTranslationState(req, req1, req2, new uint8_t[size], 4566973Stjones1@inf.ed.ac.uk NULL, mode); 4578486Sgblack@eecs.umich.edu DataTranslation<TimingSimpleCPU *> *trans1 = 4588486Sgblack@eecs.umich.edu new DataTranslation<TimingSimpleCPU *>(this, state, 0); 4598486Sgblack@eecs.umich.edu DataTranslation<TimingSimpleCPU *> *trans2 = 4608486Sgblack@eecs.umich.edu new DataTranslation<TimingSimpleCPU *>(this, state, 1); 4616973Stjones1@inf.ed.ac.uk 46211147Smitch.hayenga@arm.com thread->dtb->translateTiming(req1, thread->getTC(), trans1, mode); 46311147Smitch.hayenga@arm.com thread->dtb->translateTiming(req2, thread->getTC(), trans2, mode); 4645744Sgblack@eecs.umich.edu } else { 4656973Stjones1@inf.ed.ac.uk WholeTranslationState *state = 4667520Sgblack@eecs.umich.edu new WholeTranslationState(req, new uint8_t[size], NULL, mode); 4678486Sgblack@eecs.umich.edu DataTranslation<TimingSimpleCPU *> *translation 4688486Sgblack@eecs.umich.edu = new DataTranslation<TimingSimpleCPU *>(this, state); 46911147Smitch.hayenga@arm.com thread->dtb->translateTiming(req, thread->getTC(), translation, mode); 4702623SN/A } 4712623SN/A 4725728Sgblack@eecs.umich.edu return NoFault; 4732623SN/A} 4742623SN/A 4755728Sgblack@eecs.umich.edubool 4765728Sgblack@eecs.umich.eduTimingSimpleCPU::handleWritePacket() 4775728Sgblack@eecs.umich.edu{ 47811147Smitch.hayenga@arm.com SimpleExecContext &t_info = *threadInfo[curThread]; 47911147Smitch.hayenga@arm.com SimpleThread* thread = t_info.thread; 48011147Smitch.hayenga@arm.com 4815728Sgblack@eecs.umich.edu RequestPtr req = dcache_pkt->req; 4828105Sgblack@eecs.umich.edu if (req->isMmappedIpr()) { 4839180Sandreas.hansson@arm.com Cycles delay = TheISA::handleIprWrite(thread->getTC(), dcache_pkt); 4849179Sandreas.hansson@arm.com new IprEvent(dcache_pkt, this, clockEdge(delay)); 4855728Sgblack@eecs.umich.edu _status = DcacheWaitResponse; 4865728Sgblack@eecs.umich.edu dcache_pkt = NULL; 4878975Sandreas.hansson@arm.com } else if (!dcachePort.sendTimingReq(dcache_pkt)) { 4885728Sgblack@eecs.umich.edu _status = DcacheRetry; 4895728Sgblack@eecs.umich.edu } else { 4905728Sgblack@eecs.umich.edu _status = DcacheWaitResponse; 4915728Sgblack@eecs.umich.edu // memory system takes ownership of packet 4925728Sgblack@eecs.umich.edu dcache_pkt = NULL; 4935728Sgblack@eecs.umich.edu } 4945728Sgblack@eecs.umich.edu return dcache_pkt == NULL; 4955728Sgblack@eecs.umich.edu} 4962623SN/A 4972623SN/AFault 4988444Sgblack@eecs.umich.eduTimingSimpleCPU::writeMem(uint8_t *data, unsigned size, 49911608Snikos.nikoleris@arm.com Addr addr, Request::Flags flags, uint64_t *res) 5002623SN/A{ 50111147Smitch.hayenga@arm.com SimpleExecContext &t_info = *threadInfo[curThread]; 50211147Smitch.hayenga@arm.com SimpleThread* thread = t_info.thread; 50311147Smitch.hayenga@arm.com 5048443Sgblack@eecs.umich.edu uint8_t *newData = new uint8_t[size]; 5055728Sgblack@eecs.umich.edu const int asid = 0; 5067720Sgblack@eecs.umich.edu const Addr pc = thread->instAddr(); 5079814Sandreas.hansson@arm.com unsigned block_size = cacheLineSize(); 5086973Stjones1@inf.ed.ac.uk BaseTLB::Mode mode = BaseTLB::Write; 5093169Sstever@eecs.umich.edu 51010031SAli.Saidi@ARM.com if (data == NULL) { 51110031SAli.Saidi@ARM.com assert(flags & Request::CACHE_BLOCK_ZERO); 51210031SAli.Saidi@ARM.com // This must be a cache block cleaning request 51310031SAli.Saidi@ARM.com memset(newData, 0, size); 51410031SAli.Saidi@ARM.com } else { 51510031SAli.Saidi@ARM.com memcpy(newData, data, size); 51610031SAli.Saidi@ARM.com } 51710031SAli.Saidi@ARM.com 51810665SAli.Saidi@ARM.com if (traceData) 51910665SAli.Saidi@ARM.com traceData->setMem(addr, size, flags); 5207045Ssteve.reinhardt@amd.com 52111435Smitch.hayenga@arm.com RequestPtr req = new Request(asid, addr, size, flags, dataMasterId(), pc, 52211435Smitch.hayenga@arm.com thread->contextId()); 5235728Sgblack@eecs.umich.edu 52410024Sdam.sunwoo@arm.com req->taskId(taskId()); 52510024Sdam.sunwoo@arm.com 5267520Sgblack@eecs.umich.edu Addr split_addr = roundDown(addr + size - 1, block_size); 5275744Sgblack@eecs.umich.edu assert(split_addr <= addr || split_addr - addr < block_size); 5285728Sgblack@eecs.umich.edu 5295894Sgblack@eecs.umich.edu _status = DTBWaitResponse; 5305744Sgblack@eecs.umich.edu if (split_addr > addr) { 5315894Sgblack@eecs.umich.edu RequestPtr req1, req2; 5326102Sgblack@eecs.umich.edu assert(!req->isLLSC() && !req->isSwap()); 5335894Sgblack@eecs.umich.edu req->splitOnVaddr(split_addr, req1, req2); 5345894Sgblack@eecs.umich.edu 5356973Stjones1@inf.ed.ac.uk WholeTranslationState *state = 5368443Sgblack@eecs.umich.edu new WholeTranslationState(req, req1, req2, newData, res, mode); 5378486Sgblack@eecs.umich.edu DataTranslation<TimingSimpleCPU *> *trans1 = 5388486Sgblack@eecs.umich.edu new DataTranslation<TimingSimpleCPU *>(this, state, 0); 5398486Sgblack@eecs.umich.edu DataTranslation<TimingSimpleCPU *> *trans2 = 5408486Sgblack@eecs.umich.edu new DataTranslation<TimingSimpleCPU *>(this, state, 1); 5416973Stjones1@inf.ed.ac.uk 54211147Smitch.hayenga@arm.com thread->dtb->translateTiming(req1, thread->getTC(), trans1, mode); 54311147Smitch.hayenga@arm.com thread->dtb->translateTiming(req2, thread->getTC(), trans2, mode); 5445744Sgblack@eecs.umich.edu } else { 5456973Stjones1@inf.ed.ac.uk WholeTranslationState *state = 5468443Sgblack@eecs.umich.edu new WholeTranslationState(req, newData, res, mode); 5478486Sgblack@eecs.umich.edu DataTranslation<TimingSimpleCPU *> *translation = 5488486Sgblack@eecs.umich.edu new DataTranslation<TimingSimpleCPU *>(this, state); 54911147Smitch.hayenga@arm.com thread->dtb->translateTiming(req, thread->getTC(), translation, mode); 5502623SN/A } 5512623SN/A 5527045Ssteve.reinhardt@amd.com // Translation faults will be returned via finishTranslation() 5535728Sgblack@eecs.umich.edu return NoFault; 5542623SN/A} 5552623SN/A 55611148Smitch.hayenga@arm.comvoid 55711148Smitch.hayenga@arm.comTimingSimpleCPU::threadSnoop(PacketPtr pkt, ThreadID sender) 55811148Smitch.hayenga@arm.com{ 55911148Smitch.hayenga@arm.com for (ThreadID tid = 0; tid < numThreads; tid++) { 56011148Smitch.hayenga@arm.com if (tid != sender) { 56111321Ssteve.reinhardt@amd.com if (getCpuAddrMonitor(tid)->doMonitor(pkt)) { 56211151Smitch.hayenga@arm.com wakeup(tid); 56311148Smitch.hayenga@arm.com } 56411148Smitch.hayenga@arm.com TheISA::handleLockedSnoop(threadInfo[tid]->thread, pkt, 56511148Smitch.hayenga@arm.com dcachePort.cacheBlockMask); 56611148Smitch.hayenga@arm.com } 56711148Smitch.hayenga@arm.com } 56811148Smitch.hayenga@arm.com} 5692623SN/A 5702623SN/Avoid 5716973Stjones1@inf.ed.ac.ukTimingSimpleCPU::finishTranslation(WholeTranslationState *state) 5726973Stjones1@inf.ed.ac.uk{ 5739342SAndreas.Sandberg@arm.com _status = BaseSimpleCPU::Running; 5746973Stjones1@inf.ed.ac.uk 5756973Stjones1@inf.ed.ac.uk if (state->getFault() != NoFault) { 5766973Stjones1@inf.ed.ac.uk if (state->isPrefetch()) { 5776973Stjones1@inf.ed.ac.uk state->setNoFault(); 5786973Stjones1@inf.ed.ac.uk } 5797691SAli.Saidi@ARM.com delete [] state->data; 5806973Stjones1@inf.ed.ac.uk state->deleteReqs(); 5816973Stjones1@inf.ed.ac.uk translationFault(state->getFault()); 5826973Stjones1@inf.ed.ac.uk } else { 5836973Stjones1@inf.ed.ac.uk if (!state->isSplit) { 5846973Stjones1@inf.ed.ac.uk sendData(state->mainReq, state->data, state->res, 5856973Stjones1@inf.ed.ac.uk state->mode == BaseTLB::Read); 5866973Stjones1@inf.ed.ac.uk } else { 5876973Stjones1@inf.ed.ac.uk sendSplitData(state->sreqLow, state->sreqHigh, state->mainReq, 5886973Stjones1@inf.ed.ac.uk state->data, state->mode == BaseTLB::Read); 5896973Stjones1@inf.ed.ac.uk } 5906973Stjones1@inf.ed.ac.uk } 5916973Stjones1@inf.ed.ac.uk 5926973Stjones1@inf.ed.ac.uk delete state; 5936973Stjones1@inf.ed.ac.uk} 5946973Stjones1@inf.ed.ac.uk 5956973Stjones1@inf.ed.ac.uk 5966973Stjones1@inf.ed.ac.ukvoid 5972623SN/ATimingSimpleCPU::fetch() 5982623SN/A{ 59911147Smitch.hayenga@arm.com // Change thread if multi-threaded 60011147Smitch.hayenga@arm.com swapActiveThread(); 60111147Smitch.hayenga@arm.com 60211147Smitch.hayenga@arm.com SimpleExecContext &t_info = *threadInfo[curThread]; 60311147Smitch.hayenga@arm.com SimpleThread* thread = t_info.thread; 60411147Smitch.hayenga@arm.com 6055221Ssaidi@eecs.umich.edu DPRINTF(SimpleCPU, "Fetch\n"); 6065221Ssaidi@eecs.umich.edu 60710596Sgabeblack@google.com if (!curStaticInst || !curStaticInst->isDelayedCommit()) { 6083387Sgblack@eecs.umich.edu checkForInterrupts(); 60910596Sgabeblack@google.com checkPcEventQueue(); 61010596Sgabeblack@google.com } 6115348Ssaidi@eecs.umich.edu 6128143SAli.Saidi@ARM.com // We must have just got suspended by a PC event 6138143SAli.Saidi@ARM.com if (_status == Idle) 6148143SAli.Saidi@ARM.com return; 6158143SAli.Saidi@ARM.com 6167720Sgblack@eecs.umich.edu TheISA::PCState pcState = thread->pcState(); 61711147Smitch.hayenga@arm.com bool needToFetch = !isRomMicroPC(pcState.microPC()) && 61811147Smitch.hayenga@arm.com !curMacroStaticInst; 6192623SN/A 6207720Sgblack@eecs.umich.edu if (needToFetch) { 6219342SAndreas.Sandberg@arm.com _status = BaseSimpleCPU::Running; 6225669Sgblack@eecs.umich.edu Request *ifetch_req = new Request(); 62310024Sdam.sunwoo@arm.com ifetch_req->taskId(taskId()); 62411435Smitch.hayenga@arm.com ifetch_req->setContext(thread->contextId()); 6255894Sgblack@eecs.umich.edu setupFetchRequest(ifetch_req); 6268277SAli.Saidi@ARM.com DPRINTF(SimpleCPU, "Translating address %#x\n", ifetch_req->getVaddr()); 62711147Smitch.hayenga@arm.com thread->itb->translateTiming(ifetch_req, thread->getTC(), 62811147Smitch.hayenga@arm.com &fetchTranslation, BaseTLB::Execute); 6292623SN/A } else { 6305669Sgblack@eecs.umich.edu _status = IcacheWaitResponse; 6315669Sgblack@eecs.umich.edu completeIfetch(NULL); 6325894Sgblack@eecs.umich.edu 63310464SAndreas.Sandberg@ARM.com updateCycleCounts(); 6345894Sgblack@eecs.umich.edu } 6355894Sgblack@eecs.umich.edu} 6365894Sgblack@eecs.umich.edu 6375894Sgblack@eecs.umich.edu 6385894Sgblack@eecs.umich.eduvoid 63910379Sandreas.hansson@arm.comTimingSimpleCPU::sendFetch(const Fault &fault, RequestPtr req, 64010379Sandreas.hansson@arm.com ThreadContext *tc) 6415894Sgblack@eecs.umich.edu{ 6425894Sgblack@eecs.umich.edu if (fault == NoFault) { 6438277SAli.Saidi@ARM.com DPRINTF(SimpleCPU, "Sending fetch for addr %#x(pa: %#x)\n", 6448277SAli.Saidi@ARM.com req->getVaddr(), req->getPaddr()); 6458949Sandreas.hansson@arm.com ifetch_pkt = new Packet(req, MemCmd::ReadReq); 6465894Sgblack@eecs.umich.edu ifetch_pkt->dataStatic(&inst); 6478277SAli.Saidi@ARM.com DPRINTF(SimpleCPU, " -- pkt addr: %#x\n", ifetch_pkt->getAddr()); 6485894Sgblack@eecs.umich.edu 6498975Sandreas.hansson@arm.com if (!icachePort.sendTimingReq(ifetch_pkt)) { 6505894Sgblack@eecs.umich.edu // Need to wait for retry 6515894Sgblack@eecs.umich.edu _status = IcacheRetry; 6525894Sgblack@eecs.umich.edu } else { 6535894Sgblack@eecs.umich.edu // Need to wait for cache to respond 6545894Sgblack@eecs.umich.edu _status = IcacheWaitResponse; 6555894Sgblack@eecs.umich.edu // ownership of packet transferred to memory system 6565894Sgblack@eecs.umich.edu ifetch_pkt = NULL; 6575894Sgblack@eecs.umich.edu } 6585894Sgblack@eecs.umich.edu } else { 6598277SAli.Saidi@ARM.com DPRINTF(SimpleCPU, "Translation of addr %#x faulted\n", req->getVaddr()); 6605894Sgblack@eecs.umich.edu delete req; 6615894Sgblack@eecs.umich.edu // fetch fault: advance directly to next instruction (fault handler) 6629342SAndreas.Sandberg@arm.com _status = BaseSimpleCPU::Running; 6635894Sgblack@eecs.umich.edu advanceInst(fault); 6642623SN/A } 6653222Sktlim@umich.edu 66610464SAndreas.Sandberg@ARM.com updateCycleCounts(); 6672623SN/A} 6682623SN/A 6692623SN/A 6702623SN/Avoid 67110379Sandreas.hansson@arm.comTimingSimpleCPU::advanceInst(const Fault &fault) 6722623SN/A{ 67311147Smitch.hayenga@arm.com SimpleExecContext &t_info = *threadInfo[curThread]; 67411147Smitch.hayenga@arm.com 6758276SAli.Saidi@ARM.com if (_status == Faulting) 6768276SAli.Saidi@ARM.com return; 6778276SAli.Saidi@ARM.com 6788276SAli.Saidi@ARM.com if (fault != NoFault) { 67911877Sbrandon.potter@amd.com DPRINTF(SimpleCPU, "Fault occured, scheduling fetch event\n"); 68011877Sbrandon.potter@amd.com 6818276SAli.Saidi@ARM.com advancePC(fault); 68211877Sbrandon.potter@amd.com 68311877Sbrandon.potter@amd.com Tick stall = dynamic_pointer_cast<SyscallRetryFault>(fault) ? 68411877Sbrandon.potter@amd.com clockEdge(syscallRetryLatency) : clockEdge(); 68511877Sbrandon.potter@amd.com 68611877Sbrandon.potter@amd.com reschedule(fetchEvent, stall, true); 68711877Sbrandon.potter@amd.com 6888276SAli.Saidi@ARM.com _status = Faulting; 6898276SAli.Saidi@ARM.com return; 6908276SAli.Saidi@ARM.com } 6918276SAli.Saidi@ARM.com 6928276SAli.Saidi@ARM.com 69311147Smitch.hayenga@arm.com if (!t_info.stayAtPC) 6945726Sgblack@eecs.umich.edu advancePC(fault); 6952623SN/A 6969442SAndreas.Sandberg@ARM.com if (tryCompleteDrain()) 6979442SAndreas.Sandberg@ARM.com return; 6989442SAndreas.Sandberg@ARM.com 6999342SAndreas.Sandberg@arm.com if (_status == BaseSimpleCPU::Running) { 7002631SN/A // kick off fetch of next instruction... callback from icache 7012631SN/A // response will cause that instruction to be executed, 7022631SN/A // keeping the CPU running. 7032631SN/A fetch(); 7042631SN/A } 7052623SN/A} 7062623SN/A 7072623SN/A 7082623SN/Avoid 7093349Sbinkertn@umich.eduTimingSimpleCPU::completeIfetch(PacketPtr pkt) 7102623SN/A{ 71111147Smitch.hayenga@arm.com SimpleExecContext& t_info = *threadInfo[curThread]; 71211147Smitch.hayenga@arm.com 7138277SAli.Saidi@ARM.com DPRINTF(SimpleCPU, "Complete ICache Fetch for addr %#x\n", pkt ? 7148277SAli.Saidi@ARM.com pkt->getAddr() : 0); 7158277SAli.Saidi@ARM.com 7162623SN/A // received a response from the icache: execute the received 7172623SN/A // instruction 7185669Sgblack@eecs.umich.edu assert(!pkt || !pkt->isError()); 7192623SN/A assert(_status == IcacheWaitResponse); 7202798Sktlim@umich.edu 7219342SAndreas.Sandberg@arm.com _status = BaseSimpleCPU::Running; 7222644Sstever@eecs.umich.edu 72310464SAndreas.Sandberg@ARM.com updateCycleCounts(); 7243222Sktlim@umich.edu 72510020Smatt.horsnell@ARM.com if (pkt) 72610020Smatt.horsnell@ARM.com pkt->req->setAccessLatency(); 72710020Smatt.horsnell@ARM.com 72810020Smatt.horsnell@ARM.com 7292623SN/A preExecute(); 7307725SAli.Saidi@ARM.com if (curStaticInst && curStaticInst->isMemRef()) { 7312623SN/A // load or store: just send to dcache 73211147Smitch.hayenga@arm.com Fault fault = curStaticInst->initiateAcc(&t_info, traceData); 7337945SAli.Saidi@ARM.com 7347945SAli.Saidi@ARM.com // If we're not running now the instruction will complete in a dcache 7357945SAli.Saidi@ARM.com // response callback or the instruction faulted and has started an 7367945SAli.Saidi@ARM.com // ifetch 7379342SAndreas.Sandberg@arm.com if (_status == BaseSimpleCPU::Running) { 7385894Sgblack@eecs.umich.edu if (fault != NoFault && traceData) { 7395001Sgblack@eecs.umich.edu // If there was a fault, we shouldn't trace this instruction. 7405001Sgblack@eecs.umich.edu delete traceData; 7415001Sgblack@eecs.umich.edu traceData = NULL; 7423170Sstever@eecs.umich.edu } 7434998Sgblack@eecs.umich.edu 7442644Sstever@eecs.umich.edu postExecute(); 7455103Ssaidi@eecs.umich.edu // @todo remove me after debugging with legion done 7465103Ssaidi@eecs.umich.edu if (curStaticInst && (!curStaticInst->isMicroop() || 7475103Ssaidi@eecs.umich.edu curStaticInst->isFirstMicroop())) 7485103Ssaidi@eecs.umich.edu instCnt++; 7492644Sstever@eecs.umich.edu advanceInst(fault); 7502644Sstever@eecs.umich.edu } 7515726Sgblack@eecs.umich.edu } else if (curStaticInst) { 7522623SN/A // non-memory instruction: execute completely now 75311147Smitch.hayenga@arm.com Fault fault = curStaticInst->execute(&t_info, traceData); 7544998Sgblack@eecs.umich.edu 7554998Sgblack@eecs.umich.edu // keep an instruction count 7564998Sgblack@eecs.umich.edu if (fault == NoFault) 7574998Sgblack@eecs.umich.edu countInst(); 7587655Sali.saidi@arm.com else if (traceData && !DTRACE(ExecFaulting)) { 7595001Sgblack@eecs.umich.edu delete traceData; 7605001Sgblack@eecs.umich.edu traceData = NULL; 7615001Sgblack@eecs.umich.edu } 7624998Sgblack@eecs.umich.edu 7632644Sstever@eecs.umich.edu postExecute(); 7645103Ssaidi@eecs.umich.edu // @todo remove me after debugging with legion done 7655103Ssaidi@eecs.umich.edu if (curStaticInst && (!curStaticInst->isMicroop() || 76611147Smitch.hayenga@arm.com curStaticInst->isFirstMicroop())) 7675103Ssaidi@eecs.umich.edu instCnt++; 7682644Sstever@eecs.umich.edu advanceInst(fault); 7695726Sgblack@eecs.umich.edu } else { 7705726Sgblack@eecs.umich.edu advanceInst(NoFault); 7712623SN/A } 7723658Sktlim@umich.edu 7735669Sgblack@eecs.umich.edu if (pkt) { 7745669Sgblack@eecs.umich.edu delete pkt->req; 7755669Sgblack@eecs.umich.edu delete pkt; 7765669Sgblack@eecs.umich.edu } 7772623SN/A} 7782623SN/A 7792948Ssaidi@eecs.umich.eduvoid 7802948Ssaidi@eecs.umich.eduTimingSimpleCPU::IcachePort::ITickEvent::process() 7812948Ssaidi@eecs.umich.edu{ 7822948Ssaidi@eecs.umich.edu cpu->completeIfetch(pkt); 7832948Ssaidi@eecs.umich.edu} 7842623SN/A 7852623SN/Abool 7868975Sandreas.hansson@arm.comTimingSimpleCPU::IcachePort::recvTimingResp(PacketPtr pkt) 7872623SN/A{ 78810669Sandreas.hansson@arm.com DPRINTF(SimpleCPU, "Received fetch response %#x\n", pkt->getAddr()); 78910669Sandreas.hansson@arm.com // we should only ever see one response per cycle since we only 79010669Sandreas.hansson@arm.com // issue a new request once this response is sunk 79110669Sandreas.hansson@arm.com assert(!tickEvent.scheduled()); 7929165Sandreas.hansson@arm.com // delay processing of returned data until next CPU clock edge 79310669Sandreas.hansson@arm.com tickEvent.schedule(pkt, cpu->clockEdge()); 7948948Sandreas.hansson@arm.com 7954433Ssaidi@eecs.umich.edu return true; 7962623SN/A} 7972623SN/A 7982657Ssaidi@eecs.umich.eduvoid 79910713Sandreas.hansson@arm.comTimingSimpleCPU::IcachePort::recvReqRetry() 8002623SN/A{ 8012623SN/A // we shouldn't get a retry unless we have a packet that we're 8022623SN/A // waiting to transmit 8032623SN/A assert(cpu->ifetch_pkt != NULL); 8042623SN/A assert(cpu->_status == IcacheRetry); 8053349Sbinkertn@umich.edu PacketPtr tmp = cpu->ifetch_pkt; 8068975Sandreas.hansson@arm.com if (sendTimingReq(tmp)) { 8072657Ssaidi@eecs.umich.edu cpu->_status = IcacheWaitResponse; 8082657Ssaidi@eecs.umich.edu cpu->ifetch_pkt = NULL; 8092657Ssaidi@eecs.umich.edu } 8102623SN/A} 8112623SN/A 8122623SN/Avoid 8133349Sbinkertn@umich.eduTimingSimpleCPU::completeDataAccess(PacketPtr pkt) 8142623SN/A{ 8152623SN/A // received a response from the dcache: complete the load or store 8162623SN/A // instruction 8174870Sstever@eecs.umich.edu assert(!pkt->isError()); 8187516Shestness@cs.utexas.edu assert(_status == DcacheWaitResponse || _status == DTBWaitResponse || 8197516Shestness@cs.utexas.edu pkt->req->getFlags().isSet(Request::NO_ACCESS)); 8202623SN/A 82110020Smatt.horsnell@ARM.com pkt->req->setAccessLatency(); 82210464SAndreas.Sandberg@ARM.com 82310464SAndreas.Sandberg@ARM.com updateCycleCounts(); 8243184Srdreslin@umich.edu 8255728Sgblack@eecs.umich.edu if (pkt->senderState) { 8265728Sgblack@eecs.umich.edu SplitFragmentSenderState * send_state = 8275728Sgblack@eecs.umich.edu dynamic_cast<SplitFragmentSenderState *>(pkt->senderState); 8285728Sgblack@eecs.umich.edu assert(send_state); 8295728Sgblack@eecs.umich.edu delete pkt->req; 8305728Sgblack@eecs.umich.edu delete pkt; 8315728Sgblack@eecs.umich.edu PacketPtr big_pkt = send_state->bigPkt; 8325728Sgblack@eecs.umich.edu delete send_state; 83311320Ssteve.reinhardt@amd.com 8345728Sgblack@eecs.umich.edu SplitMainSenderState * main_send_state = 8355728Sgblack@eecs.umich.edu dynamic_cast<SplitMainSenderState *>(big_pkt->senderState); 8365728Sgblack@eecs.umich.edu assert(main_send_state); 8375728Sgblack@eecs.umich.edu // Record the fact that this packet is no longer outstanding. 8385728Sgblack@eecs.umich.edu assert(main_send_state->outstanding != 0); 8395728Sgblack@eecs.umich.edu main_send_state->outstanding--; 8405728Sgblack@eecs.umich.edu 8415728Sgblack@eecs.umich.edu if (main_send_state->outstanding) { 8425728Sgblack@eecs.umich.edu return; 8435728Sgblack@eecs.umich.edu } else { 8445728Sgblack@eecs.umich.edu delete main_send_state; 8455728Sgblack@eecs.umich.edu big_pkt->senderState = NULL; 8465728Sgblack@eecs.umich.edu pkt = big_pkt; 8475728Sgblack@eecs.umich.edu } 8485728Sgblack@eecs.umich.edu } 8495728Sgblack@eecs.umich.edu 8509342SAndreas.Sandberg@arm.com _status = BaseSimpleCPU::Running; 8515728Sgblack@eecs.umich.edu 85211147Smitch.hayenga@arm.com Fault fault = curStaticInst->completeAcc(pkt, threadInfo[curThread], 85311147Smitch.hayenga@arm.com traceData); 8542623SN/A 8554998Sgblack@eecs.umich.edu // keep an instruction count 8564998Sgblack@eecs.umich.edu if (fault == NoFault) 8574998Sgblack@eecs.umich.edu countInst(); 8585001Sgblack@eecs.umich.edu else if (traceData) { 8595001Sgblack@eecs.umich.edu // If there was a fault, we shouldn't trace this instruction. 8605001Sgblack@eecs.umich.edu delete traceData; 8615001Sgblack@eecs.umich.edu traceData = NULL; 8625001Sgblack@eecs.umich.edu } 8634998Sgblack@eecs.umich.edu 8642644Sstever@eecs.umich.edu delete pkt->req; 8652644Sstever@eecs.umich.edu delete pkt; 8662644Sstever@eecs.umich.edu 8673184Srdreslin@umich.edu postExecute(); 8683227Sktlim@umich.edu 8692644Sstever@eecs.umich.edu advanceInst(fault); 8702623SN/A} 8712623SN/A 87210030SAli.Saidi@ARM.comvoid 87310464SAndreas.Sandberg@ARM.comTimingSimpleCPU::updateCycleCounts() 87410464SAndreas.Sandberg@ARM.com{ 87510464SAndreas.Sandberg@ARM.com const Cycles delta(curCycle() - previousCycle); 87610464SAndreas.Sandberg@ARM.com 87710464SAndreas.Sandberg@ARM.com numCycles += delta; 87810464SAndreas.Sandberg@ARM.com ppCycles->notify(delta); 87910464SAndreas.Sandberg@ARM.com 88010464SAndreas.Sandberg@ARM.com previousCycle = curCycle(); 88110464SAndreas.Sandberg@ARM.com} 88210464SAndreas.Sandberg@ARM.com 88310464SAndreas.Sandberg@ARM.comvoid 88410030SAli.Saidi@ARM.comTimingSimpleCPU::DcachePort::recvTimingSnoopReq(PacketPtr pkt) 88510030SAli.Saidi@ARM.com{ 88611148Smitch.hayenga@arm.com for (ThreadID tid = 0; tid < cpu->numThreads; tid++) { 88711148Smitch.hayenga@arm.com if (cpu->getCpuAddrMonitor(tid)->doMonitor(pkt)) { 88811151Smitch.hayenga@arm.com cpu->wakeup(tid); 88911148Smitch.hayenga@arm.com } 89010529Smorr@cs.wisc.edu } 89111147Smitch.hayenga@arm.com 89211356Skrinat01@arm.com // Making it uniform across all CPUs: 89311356Skrinat01@arm.com // The CPUs need to be woken up only on an invalidation packet (when using caches) 89411356Skrinat01@arm.com // or on an incoming write packet (when not using caches) 89511356Skrinat01@arm.com // It is not necessary to wake up the processor on all incoming packets 89611356Skrinat01@arm.com if (pkt->isInvalidate() || pkt->isWrite()) { 89711356Skrinat01@arm.com for (auto &t_info : cpu->threadInfo) { 89811356Skrinat01@arm.com TheISA::handleLockedSnoop(t_info->thread, pkt, cacheBlockMask); 89911356Skrinat01@arm.com } 90011147Smitch.hayenga@arm.com } 90110030SAli.Saidi@ARM.com} 90210030SAli.Saidi@ARM.com 90310529Smorr@cs.wisc.eduvoid 90410529Smorr@cs.wisc.eduTimingSimpleCPU::DcachePort::recvFunctionalSnoop(PacketPtr pkt) 90510529Smorr@cs.wisc.edu{ 90611148Smitch.hayenga@arm.com for (ThreadID tid = 0; tid < cpu->numThreads; tid++) { 90711321Ssteve.reinhardt@amd.com if (cpu->getCpuAddrMonitor(tid)->doMonitor(pkt)) { 90811151Smitch.hayenga@arm.com cpu->wakeup(tid); 90911148Smitch.hayenga@arm.com } 91010529Smorr@cs.wisc.edu } 91110529Smorr@cs.wisc.edu} 91210030SAli.Saidi@ARM.com 9132623SN/Abool 9148975Sandreas.hansson@arm.comTimingSimpleCPU::DcachePort::recvTimingResp(PacketPtr pkt) 9152623SN/A{ 91610669Sandreas.hansson@arm.com DPRINTF(SimpleCPU, "Received load/store response %#x\n", pkt->getAddr()); 9172948Ssaidi@eecs.umich.edu 91810669Sandreas.hansson@arm.com // The timing CPU is not really ticked, instead it relies on the 91910669Sandreas.hansson@arm.com // memory system (fetch and load/store) to set the pace. 92010669Sandreas.hansson@arm.com if (!tickEvent.scheduled()) { 92110669Sandreas.hansson@arm.com // Delay processing of returned data until next CPU clock edge 92210669Sandreas.hansson@arm.com tickEvent.schedule(pkt, cpu->clockEdge()); 92310669Sandreas.hansson@arm.com return true; 9249165Sandreas.hansson@arm.com } else { 92510669Sandreas.hansson@arm.com // In the case of a split transaction and a cache that is 92610669Sandreas.hansson@arm.com // faster than a CPU we could get two responses in the 92710669Sandreas.hansson@arm.com // same tick, delay the second one 92810713Sandreas.hansson@arm.com if (!retryRespEvent.scheduled()) 92910713Sandreas.hansson@arm.com cpu->schedule(retryRespEvent, cpu->clockEdge(Cycles(1))); 93010669Sandreas.hansson@arm.com return false; 9313310Srdreslin@umich.edu } 9322948Ssaidi@eecs.umich.edu} 9332948Ssaidi@eecs.umich.edu 9342948Ssaidi@eecs.umich.eduvoid 9352948Ssaidi@eecs.umich.eduTimingSimpleCPU::DcachePort::DTickEvent::process() 9362948Ssaidi@eecs.umich.edu{ 9372630SN/A cpu->completeDataAccess(pkt); 9382623SN/A} 9392623SN/A 9402657Ssaidi@eecs.umich.eduvoid 94110713Sandreas.hansson@arm.comTimingSimpleCPU::DcachePort::recvReqRetry() 9422623SN/A{ 9432623SN/A // we shouldn't get a retry unless we have a packet that we're 9442623SN/A // waiting to transmit 9452623SN/A assert(cpu->dcache_pkt != NULL); 9462623SN/A assert(cpu->_status == DcacheRetry); 9473349Sbinkertn@umich.edu PacketPtr tmp = cpu->dcache_pkt; 9485728Sgblack@eecs.umich.edu if (tmp->senderState) { 9495728Sgblack@eecs.umich.edu // This is a packet from a split access. 9505728Sgblack@eecs.umich.edu SplitFragmentSenderState * send_state = 9515728Sgblack@eecs.umich.edu dynamic_cast<SplitFragmentSenderState *>(tmp->senderState); 9525728Sgblack@eecs.umich.edu assert(send_state); 9535728Sgblack@eecs.umich.edu PacketPtr big_pkt = send_state->bigPkt; 95411320Ssteve.reinhardt@amd.com 9555728Sgblack@eecs.umich.edu SplitMainSenderState * main_send_state = 9565728Sgblack@eecs.umich.edu dynamic_cast<SplitMainSenderState *>(big_pkt->senderState); 9575728Sgblack@eecs.umich.edu assert(main_send_state); 9585728Sgblack@eecs.umich.edu 9598975Sandreas.hansson@arm.com if (sendTimingReq(tmp)) { 9605728Sgblack@eecs.umich.edu // If we were able to send without retrying, record that fact 9615728Sgblack@eecs.umich.edu // and try sending the other fragment. 9625728Sgblack@eecs.umich.edu send_state->clearFromParent(); 9635728Sgblack@eecs.umich.edu int other_index = main_send_state->getPendingFragment(); 9645728Sgblack@eecs.umich.edu if (other_index > 0) { 9655728Sgblack@eecs.umich.edu tmp = main_send_state->fragments[other_index]; 9665728Sgblack@eecs.umich.edu cpu->dcache_pkt = tmp; 9675728Sgblack@eecs.umich.edu if ((big_pkt->isRead() && cpu->handleReadPacket(tmp)) || 9685728Sgblack@eecs.umich.edu (big_pkt->isWrite() && cpu->handleWritePacket())) { 9695728Sgblack@eecs.umich.edu main_send_state->fragments[other_index] = NULL; 9705728Sgblack@eecs.umich.edu } 9715728Sgblack@eecs.umich.edu } else { 9725728Sgblack@eecs.umich.edu cpu->_status = DcacheWaitResponse; 9735728Sgblack@eecs.umich.edu // memory system takes ownership of packet 9745728Sgblack@eecs.umich.edu cpu->dcache_pkt = NULL; 9755728Sgblack@eecs.umich.edu } 9765728Sgblack@eecs.umich.edu } 9778975Sandreas.hansson@arm.com } else if (sendTimingReq(tmp)) { 9782657Ssaidi@eecs.umich.edu cpu->_status = DcacheWaitResponse; 9793170Sstever@eecs.umich.edu // memory system takes ownership of packet 9802657Ssaidi@eecs.umich.edu cpu->dcache_pkt = NULL; 9812657Ssaidi@eecs.umich.edu } 9822623SN/A} 9832623SN/A 9845606Snate@binkert.orgTimingSimpleCPU::IprEvent::IprEvent(Packet *_pkt, TimingSimpleCPU *_cpu, 9855606Snate@binkert.org Tick t) 9865606Snate@binkert.org : pkt(_pkt), cpu(_cpu) 9875103Ssaidi@eecs.umich.edu{ 9885606Snate@binkert.org cpu->schedule(this, t); 9895103Ssaidi@eecs.umich.edu} 9905103Ssaidi@eecs.umich.edu 9915103Ssaidi@eecs.umich.eduvoid 9925103Ssaidi@eecs.umich.eduTimingSimpleCPU::IprEvent::process() 9935103Ssaidi@eecs.umich.edu{ 9945103Ssaidi@eecs.umich.edu cpu->completeDataAccess(pkt); 9955103Ssaidi@eecs.umich.edu} 9965103Ssaidi@eecs.umich.edu 9975103Ssaidi@eecs.umich.educonst char * 9985336Shines@cs.fsu.eduTimingSimpleCPU::IprEvent::description() const 9995103Ssaidi@eecs.umich.edu{ 10005103Ssaidi@eecs.umich.edu return "Timing Simple CPU Delay IPR event"; 10015103Ssaidi@eecs.umich.edu} 10025103Ssaidi@eecs.umich.edu 10032623SN/A 10045315Sstever@gmail.comvoid 10055315Sstever@gmail.comTimingSimpleCPU::printAddr(Addr a) 10065315Sstever@gmail.com{ 10075315Sstever@gmail.com dcachePort.printAddr(a); 10085315Sstever@gmail.com} 10095315Sstever@gmail.com 10105315Sstever@gmail.com 10112623SN/A//////////////////////////////////////////////////////////////////////// 10122623SN/A// 10132623SN/A// TimingSimpleCPU Simulation Object 10142623SN/A// 10154762Snate@binkert.orgTimingSimpleCPU * 10164762Snate@binkert.orgTimingSimpleCPUParams::create() 10172623SN/A{ 10185529Snate@binkert.org return new TimingSimpleCPU(this); 10192623SN/A} 1020