timing.cc revision 11148
12623SN/A/* 210596Sgabeblack@google.com * Copyright 2014 Google, Inc. 311147Smitch.hayenga@arm.com * Copyright (c) 2010-2013,2015 ARM Limited 47725SAli.Saidi@ARM.com * All rights reserved 57725SAli.Saidi@ARM.com * 67725SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall 77725SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 87725SAli.Saidi@ARM.com * property including but not limited to intellectual property relating 97725SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software 107725SAli.Saidi@ARM.com * licensed hereunder. You may use the software subject to the license 117725SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated 127725SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software, 137725SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form. 147725SAli.Saidi@ARM.com * 152623SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 162623SN/A * All rights reserved. 172623SN/A * 182623SN/A * Redistribution and use in source and binary forms, with or without 192623SN/A * modification, are permitted provided that the following conditions are 202623SN/A * met: redistributions of source code must retain the above copyright 212623SN/A * notice, this list of conditions and the following disclaimer; 222623SN/A * redistributions in binary form must reproduce the above copyright 232623SN/A * notice, this list of conditions and the following disclaimer in the 242623SN/A * documentation and/or other materials provided with the distribution; 252623SN/A * neither the name of the copyright holders nor the names of its 262623SN/A * contributors may be used to endorse or promote products derived from 272623SN/A * this software without specific prior written permission. 282623SN/A * 292623SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 302623SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 312623SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 322623SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 332623SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 342623SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 352623SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 362623SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 372623SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 382623SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 392623SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402665Ssaidi@eecs.umich.edu * 412665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 422623SN/A */ 432623SN/A 443170Sstever@eecs.umich.edu#include "arch/locked_mem.hh" 458105Sgblack@eecs.umich.edu#include "arch/mmapped_ipr.hh" 462623SN/A#include "arch/utility.hh" 474040Ssaidi@eecs.umich.edu#include "base/bigint.hh" 486658Snate@binkert.org#include "config/the_isa.hh" 498229Snate@binkert.org#include "cpu/simple/timing.hh" 502623SN/A#include "cpu/exetrace.hh" 518232Snate@binkert.org#include "debug/Config.hh" 529152Satgutier@umich.edu#include "debug/Drain.hh" 538232Snate@binkert.org#include "debug/ExecFaulting.hh" 548232Snate@binkert.org#include "debug/SimpleCPU.hh" 553348Sbinkertn@umich.edu#include "mem/packet.hh" 563348Sbinkertn@umich.edu#include "mem/packet_access.hh" 574762Snate@binkert.org#include "params/TimingSimpleCPU.hh" 587678Sgblack@eecs.umich.edu#include "sim/faults.hh" 598779Sgblack@eecs.umich.edu#include "sim/full_system.hh" 602901Ssaidi@eecs.umich.edu#include "sim/system.hh" 612623SN/A 6210529Smorr@cs.wisc.edu#include "debug/Mwait.hh" 6310529Smorr@cs.wisc.edu 642623SN/Ausing namespace std; 652623SN/Ausing namespace TheISA; 662623SN/A 672623SN/Avoid 682623SN/ATimingSimpleCPU::init() 692623SN/A{ 7011147Smitch.hayenga@arm.com BaseSimpleCPU::init(); 712623SN/A} 722623SN/A 732623SN/Avoid 748707Sandreas.hansson@arm.comTimingSimpleCPU::TimingCPUPort::TickEvent::schedule(PacketPtr _pkt, Tick t) 752948Ssaidi@eecs.umich.edu{ 762948Ssaidi@eecs.umich.edu pkt = _pkt; 775606Snate@binkert.org cpu->schedule(this, t); 782948Ssaidi@eecs.umich.edu} 792948Ssaidi@eecs.umich.edu 805529Snate@binkert.orgTimingSimpleCPU::TimingSimpleCPU(TimingSimpleCPUParams *p) 818707Sandreas.hansson@arm.com : BaseSimpleCPU(p), fetchTranslation(this), icachePort(this), 829179Sandreas.hansson@arm.com dcachePort(this), ifetch_pkt(NULL), dcache_pkt(NULL), previousCycle(0), 8310913Sandreas.sandberg@arm.com fetchEvent(this) 842623SN/A{ 852623SN/A _status = Idle; 862623SN/A} 872623SN/A 882623SN/A 8910030SAli.Saidi@ARM.com 902623SN/ATimingSimpleCPU::~TimingSimpleCPU() 912623SN/A{ 922623SN/A} 932623SN/A 9410913Sandreas.sandberg@arm.comDrainState 9510913Sandreas.sandberg@arm.comTimingSimpleCPU::drain() 962798Sktlim@umich.edu{ 979448SAndreas.Sandberg@ARM.com if (switchedOut()) 9810913Sandreas.sandberg@arm.com return DrainState::Drained; 999448SAndreas.Sandberg@ARM.com 1009342SAndreas.Sandberg@arm.com if (_status == Idle || 1019448SAndreas.Sandberg@ARM.com (_status == BaseSimpleCPU::Running && isDrained())) { 1029442SAndreas.Sandberg@ARM.com DPRINTF(Drain, "No need to drain.\n"); 10311147Smitch.hayenga@arm.com activeThreads.clear(); 10410913Sandreas.sandberg@arm.com return DrainState::Drained; 1052798Sktlim@umich.edu } else { 10611147Smitch.hayenga@arm.com DPRINTF(Drain, "Requesting drain.\n"); 1079442SAndreas.Sandberg@ARM.com 1089442SAndreas.Sandberg@ARM.com // The fetch event can become descheduled if a drain didn't 1099442SAndreas.Sandberg@ARM.com // succeed on the first attempt. We need to reschedule it if 1109442SAndreas.Sandberg@ARM.com // the CPU is waiting for a microcode routine to complete. 1119448SAndreas.Sandberg@ARM.com if (_status == BaseSimpleCPU::Running && !fetchEvent.scheduled()) 1129648Sdam.sunwoo@arm.com schedule(fetchEvent, clockEdge()); 1139442SAndreas.Sandberg@ARM.com 11410913Sandreas.sandberg@arm.com return DrainState::Draining; 1152798Sktlim@umich.edu } 1162623SN/A} 1172623SN/A 1182623SN/Avoid 1199342SAndreas.Sandberg@arm.comTimingSimpleCPU::drainResume() 1202623SN/A{ 1219442SAndreas.Sandberg@ARM.com assert(!fetchEvent.scheduled()); 1229448SAndreas.Sandberg@ARM.com if (switchedOut()) 1239448SAndreas.Sandberg@ARM.com return; 1249442SAndreas.Sandberg@ARM.com 1255221Ssaidi@eecs.umich.edu DPRINTF(SimpleCPU, "Resume\n"); 1269523SAndreas.Sandberg@ARM.com verifyMemoryMode(); 1273201Shsul@eecs.umich.edu 1289448SAndreas.Sandberg@ARM.com assert(!threadContexts.empty()); 1299448SAndreas.Sandberg@ARM.com 13011147Smitch.hayenga@arm.com _status = BaseSimpleCPU::Idle; 13111147Smitch.hayenga@arm.com 13211147Smitch.hayenga@arm.com for (ThreadID tid = 0; tid < numThreads; tid++) { 13311147Smitch.hayenga@arm.com if (threadInfo[tid]->thread->status() == ThreadContext::Active) { 13411147Smitch.hayenga@arm.com threadInfo[tid]->notIdleFraction = 1; 13511147Smitch.hayenga@arm.com 13611147Smitch.hayenga@arm.com activeThreads.push_back(tid); 13711147Smitch.hayenga@arm.com 13811147Smitch.hayenga@arm.com _status = BaseSimpleCPU::Running; 13911147Smitch.hayenga@arm.com 14011147Smitch.hayenga@arm.com // Fetch if any threads active 14111147Smitch.hayenga@arm.com if (!fetchEvent.scheduled()) { 14211147Smitch.hayenga@arm.com schedule(fetchEvent, nextCycle()); 14311147Smitch.hayenga@arm.com } 14411147Smitch.hayenga@arm.com } else { 14511147Smitch.hayenga@arm.com threadInfo[tid]->notIdleFraction = 0; 14611147Smitch.hayenga@arm.com } 1472623SN/A } 14811147Smitch.hayenga@arm.com 14911147Smitch.hayenga@arm.com system->totalNumInsts = 0; 1509442SAndreas.Sandberg@ARM.com} 1512798Sktlim@umich.edu 1529442SAndreas.Sandberg@ARM.combool 1539442SAndreas.Sandberg@ARM.comTimingSimpleCPU::tryCompleteDrain() 1549442SAndreas.Sandberg@ARM.com{ 15510913Sandreas.sandberg@arm.com if (drainState() != DrainState::Draining) 1569442SAndreas.Sandberg@ARM.com return false; 1579442SAndreas.Sandberg@ARM.com 15811147Smitch.hayenga@arm.com DPRINTF(Drain, "tryCompleteDrain.\n"); 1599442SAndreas.Sandberg@ARM.com if (!isDrained()) 1609442SAndreas.Sandberg@ARM.com return false; 1619442SAndreas.Sandberg@ARM.com 1629442SAndreas.Sandberg@ARM.com DPRINTF(Drain, "CPU done draining, processing drain event\n"); 16310913Sandreas.sandberg@arm.com signalDrainDone(); 1649442SAndreas.Sandberg@ARM.com 1659442SAndreas.Sandberg@ARM.com return true; 1662798Sktlim@umich.edu} 1672798Sktlim@umich.edu 1682798Sktlim@umich.eduvoid 1692798Sktlim@umich.eduTimingSimpleCPU::switchOut() 1702798Sktlim@umich.edu{ 17111147Smitch.hayenga@arm.com SimpleExecContext& t_info = *threadInfo[curThread]; 17211147Smitch.hayenga@arm.com M5_VAR_USED SimpleThread* thread = t_info.thread; 17311147Smitch.hayenga@arm.com 1749429SAndreas.Sandberg@ARM.com BaseSimpleCPU::switchOut(); 1759429SAndreas.Sandberg@ARM.com 1769442SAndreas.Sandberg@ARM.com assert(!fetchEvent.scheduled()); 1779342SAndreas.Sandberg@arm.com assert(_status == BaseSimpleCPU::Running || _status == Idle); 17811147Smitch.hayenga@arm.com assert(!t_info.stayAtPC); 17911147Smitch.hayenga@arm.com assert(thread->microPC() == 0); 1809442SAndreas.Sandberg@ARM.com 18110464SAndreas.Sandberg@ARM.com updateCycleCounts(); 1822623SN/A} 1832623SN/A 1842623SN/A 1852623SN/Avoid 1862623SN/ATimingSimpleCPU::takeOverFrom(BaseCPU *oldCPU) 1872623SN/A{ 1889429SAndreas.Sandberg@ARM.com BaseSimpleCPU::takeOverFrom(oldCPU); 1892623SN/A 1909179Sandreas.hansson@arm.com previousCycle = curCycle(); 1912623SN/A} 1922623SN/A 1939523SAndreas.Sandberg@ARM.comvoid 1949523SAndreas.Sandberg@ARM.comTimingSimpleCPU::verifyMemoryMode() const 1959523SAndreas.Sandberg@ARM.com{ 1969524SAndreas.Sandberg@ARM.com if (!system->isTimingMode()) { 1979523SAndreas.Sandberg@ARM.com fatal("The timing CPU requires the memory system to be in " 1989523SAndreas.Sandberg@ARM.com "'timing' mode.\n"); 1999523SAndreas.Sandberg@ARM.com } 2009523SAndreas.Sandberg@ARM.com} 2012623SN/A 2022623SN/Avoid 20310407Smitch.hayenga@arm.comTimingSimpleCPU::activateContext(ThreadID thread_num) 2042623SN/A{ 20510407Smitch.hayenga@arm.com DPRINTF(SimpleCPU, "ActivateContext %d\n", thread_num); 2065221Ssaidi@eecs.umich.edu 20711147Smitch.hayenga@arm.com assert(thread_num < numThreads); 2082623SN/A 20911147Smitch.hayenga@arm.com threadInfo[thread_num]->notIdleFraction = 1; 21011147Smitch.hayenga@arm.com if (_status == BaseSimpleCPU::Idle) 21111147Smitch.hayenga@arm.com _status = BaseSimpleCPU::Running; 2123686Sktlim@umich.edu 2132623SN/A // kick things off by initiating the fetch of the next instruction 21411147Smitch.hayenga@arm.com if (!fetchEvent.scheduled()) 21511147Smitch.hayenga@arm.com schedule(fetchEvent, clockEdge(Cycles(0))); 21611147Smitch.hayenga@arm.com 21711147Smitch.hayenga@arm.com if (std::find(activeThreads.begin(), activeThreads.end(), thread_num) 21811147Smitch.hayenga@arm.com == activeThreads.end()) { 21911147Smitch.hayenga@arm.com activeThreads.push_back(thread_num); 22011147Smitch.hayenga@arm.com } 2212623SN/A} 2222623SN/A 2232623SN/A 2242623SN/Avoid 2258737Skoansin.tan@gmail.comTimingSimpleCPU::suspendContext(ThreadID thread_num) 2262623SN/A{ 2275221Ssaidi@eecs.umich.edu DPRINTF(SimpleCPU, "SuspendContext %d\n", thread_num); 2285221Ssaidi@eecs.umich.edu 22911147Smitch.hayenga@arm.com assert(thread_num < numThreads); 23011147Smitch.hayenga@arm.com activeThreads.remove(thread_num); 2312623SN/A 2326043Sgblack@eecs.umich.edu if (_status == Idle) 2336043Sgblack@eecs.umich.edu return; 2346043Sgblack@eecs.umich.edu 2359342SAndreas.Sandberg@arm.com assert(_status == BaseSimpleCPU::Running); 2362623SN/A 23711147Smitch.hayenga@arm.com threadInfo[thread_num]->notIdleFraction = 0; 2382623SN/A 23911147Smitch.hayenga@arm.com if (activeThreads.empty()) { 24011147Smitch.hayenga@arm.com _status = Idle; 24111147Smitch.hayenga@arm.com 24211147Smitch.hayenga@arm.com if (fetchEvent.scheduled()) { 24311147Smitch.hayenga@arm.com deschedule(fetchEvent); 24411147Smitch.hayenga@arm.com } 24511147Smitch.hayenga@arm.com } 2462623SN/A} 2472623SN/A 2485728Sgblack@eecs.umich.edubool 2495728Sgblack@eecs.umich.eduTimingSimpleCPU::handleReadPacket(PacketPtr pkt) 2505728Sgblack@eecs.umich.edu{ 25111147Smitch.hayenga@arm.com SimpleExecContext &t_info = *threadInfo[curThread]; 25211147Smitch.hayenga@arm.com SimpleThread* thread = t_info.thread; 25311147Smitch.hayenga@arm.com 2545728Sgblack@eecs.umich.edu RequestPtr req = pkt->req; 25510533Sali.saidi@arm.com 25610533Sali.saidi@arm.com // We're about the issues a locked load, so tell the monitor 25710533Sali.saidi@arm.com // to start caring about this address 25810533Sali.saidi@arm.com if (pkt->isRead() && pkt->req->isLLSC()) { 25910533Sali.saidi@arm.com TheISA::handleLockedRead(thread, pkt->req); 26010533Sali.saidi@arm.com } 2618105Sgblack@eecs.umich.edu if (req->isMmappedIpr()) { 2629180Sandreas.hansson@arm.com Cycles delay = TheISA::handleIprRead(thread->getTC(), pkt); 2639179Sandreas.hansson@arm.com new IprEvent(pkt, this, clockEdge(delay)); 2645728Sgblack@eecs.umich.edu _status = DcacheWaitResponse; 2655728Sgblack@eecs.umich.edu dcache_pkt = NULL; 2668975Sandreas.hansson@arm.com } else if (!dcachePort.sendTimingReq(pkt)) { 2675728Sgblack@eecs.umich.edu _status = DcacheRetry; 2685728Sgblack@eecs.umich.edu dcache_pkt = pkt; 2695728Sgblack@eecs.umich.edu } else { 2705728Sgblack@eecs.umich.edu _status = DcacheWaitResponse; 2715728Sgblack@eecs.umich.edu // memory system takes ownership of packet 2725728Sgblack@eecs.umich.edu dcache_pkt = NULL; 2735728Sgblack@eecs.umich.edu } 2745728Sgblack@eecs.umich.edu return dcache_pkt == NULL; 2755728Sgblack@eecs.umich.edu} 2762623SN/A 2775894Sgblack@eecs.umich.eduvoid 2786973Stjones1@inf.ed.ac.ukTimingSimpleCPU::sendData(RequestPtr req, uint8_t *data, uint64_t *res, 2796973Stjones1@inf.ed.ac.uk bool read) 2805744Sgblack@eecs.umich.edu{ 28111147Smitch.hayenga@arm.com SimpleExecContext &t_info = *threadInfo[curThread]; 28211147Smitch.hayenga@arm.com SimpleThread* thread = t_info.thread; 28311147Smitch.hayenga@arm.com 28410653Sandreas.hansson@arm.com PacketPtr pkt = buildPacket(req, read); 28510566Sandreas.hansson@arm.com pkt->dataDynamic<uint8_t>(data); 2865894Sgblack@eecs.umich.edu if (req->getFlags().isSet(Request::NO_ACCESS)) { 2875894Sgblack@eecs.umich.edu assert(!dcache_pkt); 2885894Sgblack@eecs.umich.edu pkt->makeResponse(); 2895894Sgblack@eecs.umich.edu completeDataAccess(pkt); 2905894Sgblack@eecs.umich.edu } else if (read) { 2915894Sgblack@eecs.umich.edu handleReadPacket(pkt); 2925894Sgblack@eecs.umich.edu } else { 2935894Sgblack@eecs.umich.edu bool do_access = true; // flag to suppress cache access 2945894Sgblack@eecs.umich.edu 2956102Sgblack@eecs.umich.edu if (req->isLLSC()) { 29610030SAli.Saidi@ARM.com do_access = TheISA::handleLockedWrite(thread, req, dcachePort.cacheBlockMask); 2975894Sgblack@eecs.umich.edu } else if (req->isCondSwap()) { 2985894Sgblack@eecs.umich.edu assert(res); 2995894Sgblack@eecs.umich.edu req->setExtraData(*res); 3005894Sgblack@eecs.umich.edu } 3015894Sgblack@eecs.umich.edu 3025894Sgblack@eecs.umich.edu if (do_access) { 3035894Sgblack@eecs.umich.edu dcache_pkt = pkt; 3045894Sgblack@eecs.umich.edu handleWritePacket(); 30511148Smitch.hayenga@arm.com threadSnoop(pkt, curThread); 3065894Sgblack@eecs.umich.edu } else { 3075894Sgblack@eecs.umich.edu _status = DcacheWaitResponse; 3085894Sgblack@eecs.umich.edu completeDataAccess(pkt); 3095894Sgblack@eecs.umich.edu } 3105894Sgblack@eecs.umich.edu } 3115894Sgblack@eecs.umich.edu} 3125894Sgblack@eecs.umich.edu 3135894Sgblack@eecs.umich.eduvoid 3146973Stjones1@inf.ed.ac.ukTimingSimpleCPU::sendSplitData(RequestPtr req1, RequestPtr req2, 3156973Stjones1@inf.ed.ac.uk RequestPtr req, uint8_t *data, bool read) 3165894Sgblack@eecs.umich.edu{ 3175894Sgblack@eecs.umich.edu PacketPtr pkt1, pkt2; 3185894Sgblack@eecs.umich.edu buildSplitPacket(pkt1, pkt2, req1, req2, req, data, read); 3195894Sgblack@eecs.umich.edu if (req->getFlags().isSet(Request::NO_ACCESS)) { 3205894Sgblack@eecs.umich.edu assert(!dcache_pkt); 3215894Sgblack@eecs.umich.edu pkt1->makeResponse(); 3225894Sgblack@eecs.umich.edu completeDataAccess(pkt1); 3235894Sgblack@eecs.umich.edu } else if (read) { 3247911Shestness@cs.utexas.edu SplitFragmentSenderState * send_state = 3257911Shestness@cs.utexas.edu dynamic_cast<SplitFragmentSenderState *>(pkt1->senderState); 3265894Sgblack@eecs.umich.edu if (handleReadPacket(pkt1)) { 3275894Sgblack@eecs.umich.edu send_state->clearFromParent(); 3287911Shestness@cs.utexas.edu send_state = dynamic_cast<SplitFragmentSenderState *>( 3297911Shestness@cs.utexas.edu pkt2->senderState); 3305894Sgblack@eecs.umich.edu if (handleReadPacket(pkt2)) { 3315894Sgblack@eecs.umich.edu send_state->clearFromParent(); 3325894Sgblack@eecs.umich.edu } 3335894Sgblack@eecs.umich.edu } 3345894Sgblack@eecs.umich.edu } else { 3355894Sgblack@eecs.umich.edu dcache_pkt = pkt1; 3367911Shestness@cs.utexas.edu SplitFragmentSenderState * send_state = 3377911Shestness@cs.utexas.edu dynamic_cast<SplitFragmentSenderState *>(pkt1->senderState); 3385894Sgblack@eecs.umich.edu if (handleWritePacket()) { 3395894Sgblack@eecs.umich.edu send_state->clearFromParent(); 3405894Sgblack@eecs.umich.edu dcache_pkt = pkt2; 3417911Shestness@cs.utexas.edu send_state = dynamic_cast<SplitFragmentSenderState *>( 3427911Shestness@cs.utexas.edu pkt2->senderState); 3435894Sgblack@eecs.umich.edu if (handleWritePacket()) { 3445894Sgblack@eecs.umich.edu send_state->clearFromParent(); 3455894Sgblack@eecs.umich.edu } 3465894Sgblack@eecs.umich.edu } 3475894Sgblack@eecs.umich.edu } 3485894Sgblack@eecs.umich.edu} 3495894Sgblack@eecs.umich.edu 3505894Sgblack@eecs.umich.eduvoid 35110379Sandreas.hansson@arm.comTimingSimpleCPU::translationFault(const Fault &fault) 3525894Sgblack@eecs.umich.edu{ 3536739Sgblack@eecs.umich.edu // fault may be NoFault in cases where a fault is suppressed, 3546739Sgblack@eecs.umich.edu // for instance prefetches. 35510464SAndreas.Sandberg@ARM.com updateCycleCounts(); 3565894Sgblack@eecs.umich.edu 3575894Sgblack@eecs.umich.edu if (traceData) { 3585894Sgblack@eecs.umich.edu // Since there was a fault, we shouldn't trace this instruction. 3595894Sgblack@eecs.umich.edu delete traceData; 3605894Sgblack@eecs.umich.edu traceData = NULL; 3615744Sgblack@eecs.umich.edu } 3625744Sgblack@eecs.umich.edu 3635894Sgblack@eecs.umich.edu postExecute(); 3645894Sgblack@eecs.umich.edu 3659442SAndreas.Sandberg@ARM.com advanceInst(fault); 3665894Sgblack@eecs.umich.edu} 3675894Sgblack@eecs.umich.edu 36810653Sandreas.hansson@arm.comPacketPtr 36910653Sandreas.hansson@arm.comTimingSimpleCPU::buildPacket(RequestPtr req, bool read) 3705894Sgblack@eecs.umich.edu{ 37110653Sandreas.hansson@arm.com return read ? Packet::createRead(req) : Packet::createWrite(req); 3725894Sgblack@eecs.umich.edu} 3735894Sgblack@eecs.umich.edu 3745894Sgblack@eecs.umich.eduvoid 3755894Sgblack@eecs.umich.eduTimingSimpleCPU::buildSplitPacket(PacketPtr &pkt1, PacketPtr &pkt2, 3765894Sgblack@eecs.umich.edu RequestPtr req1, RequestPtr req2, RequestPtr req, 3775894Sgblack@eecs.umich.edu uint8_t *data, bool read) 3785894Sgblack@eecs.umich.edu{ 3795894Sgblack@eecs.umich.edu pkt1 = pkt2 = NULL; 3805894Sgblack@eecs.umich.edu 3818105Sgblack@eecs.umich.edu assert(!req1->isMmappedIpr() && !req2->isMmappedIpr()); 3825744Sgblack@eecs.umich.edu 3835894Sgblack@eecs.umich.edu if (req->getFlags().isSet(Request::NO_ACCESS)) { 38410653Sandreas.hansson@arm.com pkt1 = buildPacket(req, read); 3855894Sgblack@eecs.umich.edu return; 3865894Sgblack@eecs.umich.edu } 3875894Sgblack@eecs.umich.edu 38810653Sandreas.hansson@arm.com pkt1 = buildPacket(req1, read); 38910653Sandreas.hansson@arm.com pkt2 = buildPacket(req2, read); 3905894Sgblack@eecs.umich.edu 3918949Sandreas.hansson@arm.com PacketPtr pkt = new Packet(req, pkt1->cmd.responseCommand()); 3925744Sgblack@eecs.umich.edu 39310566Sandreas.hansson@arm.com pkt->dataDynamic<uint8_t>(data); 3945744Sgblack@eecs.umich.edu pkt1->dataStatic<uint8_t>(data); 3955744Sgblack@eecs.umich.edu pkt2->dataStatic<uint8_t>(data + req1->getSize()); 3965744Sgblack@eecs.umich.edu 3975744Sgblack@eecs.umich.edu SplitMainSenderState * main_send_state = new SplitMainSenderState; 3985744Sgblack@eecs.umich.edu pkt->senderState = main_send_state; 3995744Sgblack@eecs.umich.edu main_send_state->fragments[0] = pkt1; 4005744Sgblack@eecs.umich.edu main_send_state->fragments[1] = pkt2; 4015744Sgblack@eecs.umich.edu main_send_state->outstanding = 2; 4025744Sgblack@eecs.umich.edu pkt1->senderState = new SplitFragmentSenderState(pkt, 0); 4035744Sgblack@eecs.umich.edu pkt2->senderState = new SplitFragmentSenderState(pkt, 1); 4045744Sgblack@eecs.umich.edu} 4055744Sgblack@eecs.umich.edu 4062623SN/AFault 4078444Sgblack@eecs.umich.eduTimingSimpleCPU::readMem(Addr addr, uint8_t *data, 4088444Sgblack@eecs.umich.edu unsigned size, unsigned flags) 4092623SN/A{ 41011147Smitch.hayenga@arm.com SimpleExecContext &t_info = *threadInfo[curThread]; 41111147Smitch.hayenga@arm.com SimpleThread* thread = t_info.thread; 41211147Smitch.hayenga@arm.com 4135728Sgblack@eecs.umich.edu Fault fault; 4145728Sgblack@eecs.umich.edu const int asid = 0; 41511147Smitch.hayenga@arm.com const ThreadID tid = curThread; 4167720Sgblack@eecs.umich.edu const Addr pc = thread->instAddr(); 4179814Sandreas.hansson@arm.com unsigned block_size = cacheLineSize(); 4186973Stjones1@inf.ed.ac.uk BaseTLB::Mode mode = BaseTLB::Read; 4192623SN/A 42010665SAli.Saidi@ARM.com if (traceData) 42110665SAli.Saidi@ARM.com traceData->setMem(addr, size, flags); 4227045Ssteve.reinhardt@amd.com 4237520Sgblack@eecs.umich.edu RequestPtr req = new Request(asid, addr, size, 42411147Smitch.hayenga@arm.com flags, dataMasterId(), pc, 42511147Smitch.hayenga@arm.com thread->contextId(), tid); 4265728Sgblack@eecs.umich.edu 42710024Sdam.sunwoo@arm.com req->taskId(taskId()); 42810024Sdam.sunwoo@arm.com 4297520Sgblack@eecs.umich.edu Addr split_addr = roundDown(addr + size - 1, block_size); 4305744Sgblack@eecs.umich.edu assert(split_addr <= addr || split_addr - addr < block_size); 4315728Sgblack@eecs.umich.edu 4325894Sgblack@eecs.umich.edu _status = DTBWaitResponse; 4335744Sgblack@eecs.umich.edu if (split_addr > addr) { 4345894Sgblack@eecs.umich.edu RequestPtr req1, req2; 4356102Sgblack@eecs.umich.edu assert(!req->isLLSC() && !req->isSwap()); 4365894Sgblack@eecs.umich.edu req->splitOnVaddr(split_addr, req1, req2); 4375894Sgblack@eecs.umich.edu 4386973Stjones1@inf.ed.ac.uk WholeTranslationState *state = 4397520Sgblack@eecs.umich.edu new WholeTranslationState(req, req1, req2, new uint8_t[size], 4406973Stjones1@inf.ed.ac.uk NULL, mode); 4418486Sgblack@eecs.umich.edu DataTranslation<TimingSimpleCPU *> *trans1 = 4428486Sgblack@eecs.umich.edu new DataTranslation<TimingSimpleCPU *>(this, state, 0); 4438486Sgblack@eecs.umich.edu DataTranslation<TimingSimpleCPU *> *trans2 = 4448486Sgblack@eecs.umich.edu new DataTranslation<TimingSimpleCPU *>(this, state, 1); 4456973Stjones1@inf.ed.ac.uk 44611147Smitch.hayenga@arm.com thread->dtb->translateTiming(req1, thread->getTC(), trans1, mode); 44711147Smitch.hayenga@arm.com thread->dtb->translateTiming(req2, thread->getTC(), trans2, mode); 4485744Sgblack@eecs.umich.edu } else { 4496973Stjones1@inf.ed.ac.uk WholeTranslationState *state = 4507520Sgblack@eecs.umich.edu new WholeTranslationState(req, new uint8_t[size], NULL, mode); 4518486Sgblack@eecs.umich.edu DataTranslation<TimingSimpleCPU *> *translation 4528486Sgblack@eecs.umich.edu = new DataTranslation<TimingSimpleCPU *>(this, state); 45311147Smitch.hayenga@arm.com thread->dtb->translateTiming(req, thread->getTC(), translation, mode); 4542623SN/A } 4552623SN/A 4565728Sgblack@eecs.umich.edu return NoFault; 4572623SN/A} 4582623SN/A 4595728Sgblack@eecs.umich.edubool 4605728Sgblack@eecs.umich.eduTimingSimpleCPU::handleWritePacket() 4615728Sgblack@eecs.umich.edu{ 46211147Smitch.hayenga@arm.com SimpleExecContext &t_info = *threadInfo[curThread]; 46311147Smitch.hayenga@arm.com SimpleThread* thread = t_info.thread; 46411147Smitch.hayenga@arm.com 4655728Sgblack@eecs.umich.edu RequestPtr req = dcache_pkt->req; 4668105Sgblack@eecs.umich.edu if (req->isMmappedIpr()) { 4679180Sandreas.hansson@arm.com Cycles delay = TheISA::handleIprWrite(thread->getTC(), dcache_pkt); 4689179Sandreas.hansson@arm.com new IprEvent(dcache_pkt, this, clockEdge(delay)); 4695728Sgblack@eecs.umich.edu _status = DcacheWaitResponse; 4705728Sgblack@eecs.umich.edu dcache_pkt = NULL; 4718975Sandreas.hansson@arm.com } else if (!dcachePort.sendTimingReq(dcache_pkt)) { 4725728Sgblack@eecs.umich.edu _status = DcacheRetry; 4735728Sgblack@eecs.umich.edu } else { 4745728Sgblack@eecs.umich.edu _status = DcacheWaitResponse; 4755728Sgblack@eecs.umich.edu // memory system takes ownership of packet 4765728Sgblack@eecs.umich.edu dcache_pkt = NULL; 4775728Sgblack@eecs.umich.edu } 4785728Sgblack@eecs.umich.edu return dcache_pkt == NULL; 4795728Sgblack@eecs.umich.edu} 4802623SN/A 4812623SN/AFault 4828444Sgblack@eecs.umich.eduTimingSimpleCPU::writeMem(uint8_t *data, unsigned size, 4838444Sgblack@eecs.umich.edu Addr addr, unsigned flags, uint64_t *res) 4842623SN/A{ 48511147Smitch.hayenga@arm.com SimpleExecContext &t_info = *threadInfo[curThread]; 48611147Smitch.hayenga@arm.com SimpleThread* thread = t_info.thread; 48711147Smitch.hayenga@arm.com 4888443Sgblack@eecs.umich.edu uint8_t *newData = new uint8_t[size]; 4895728Sgblack@eecs.umich.edu const int asid = 0; 49011147Smitch.hayenga@arm.com const ThreadID tid = curThread; 4917720Sgblack@eecs.umich.edu const Addr pc = thread->instAddr(); 4929814Sandreas.hansson@arm.com unsigned block_size = cacheLineSize(); 4936973Stjones1@inf.ed.ac.uk BaseTLB::Mode mode = BaseTLB::Write; 4943169Sstever@eecs.umich.edu 49510031SAli.Saidi@ARM.com if (data == NULL) { 49610031SAli.Saidi@ARM.com assert(flags & Request::CACHE_BLOCK_ZERO); 49710031SAli.Saidi@ARM.com // This must be a cache block cleaning request 49810031SAli.Saidi@ARM.com memset(newData, 0, size); 49910031SAli.Saidi@ARM.com } else { 50010031SAli.Saidi@ARM.com memcpy(newData, data, size); 50110031SAli.Saidi@ARM.com } 50210031SAli.Saidi@ARM.com 50310665SAli.Saidi@ARM.com if (traceData) 50410665SAli.Saidi@ARM.com traceData->setMem(addr, size, flags); 5057045Ssteve.reinhardt@amd.com 5067520Sgblack@eecs.umich.edu RequestPtr req = new Request(asid, addr, size, 50711147Smitch.hayenga@arm.com flags, dataMasterId(), pc, 50811147Smitch.hayenga@arm.com thread->contextId(), tid); 5095728Sgblack@eecs.umich.edu 51010024Sdam.sunwoo@arm.com req->taskId(taskId()); 51110024Sdam.sunwoo@arm.com 5127520Sgblack@eecs.umich.edu Addr split_addr = roundDown(addr + size - 1, block_size); 5135744Sgblack@eecs.umich.edu assert(split_addr <= addr || split_addr - addr < block_size); 5145728Sgblack@eecs.umich.edu 5155894Sgblack@eecs.umich.edu _status = DTBWaitResponse; 5165744Sgblack@eecs.umich.edu if (split_addr > addr) { 5175894Sgblack@eecs.umich.edu RequestPtr req1, req2; 5186102Sgblack@eecs.umich.edu assert(!req->isLLSC() && !req->isSwap()); 5195894Sgblack@eecs.umich.edu req->splitOnVaddr(split_addr, req1, req2); 5205894Sgblack@eecs.umich.edu 5216973Stjones1@inf.ed.ac.uk WholeTranslationState *state = 5228443Sgblack@eecs.umich.edu new WholeTranslationState(req, req1, req2, newData, res, mode); 5238486Sgblack@eecs.umich.edu DataTranslation<TimingSimpleCPU *> *trans1 = 5248486Sgblack@eecs.umich.edu new DataTranslation<TimingSimpleCPU *>(this, state, 0); 5258486Sgblack@eecs.umich.edu DataTranslation<TimingSimpleCPU *> *trans2 = 5268486Sgblack@eecs.umich.edu new DataTranslation<TimingSimpleCPU *>(this, state, 1); 5276973Stjones1@inf.ed.ac.uk 52811147Smitch.hayenga@arm.com thread->dtb->translateTiming(req1, thread->getTC(), trans1, mode); 52911147Smitch.hayenga@arm.com thread->dtb->translateTiming(req2, thread->getTC(), trans2, mode); 5305744Sgblack@eecs.umich.edu } else { 5316973Stjones1@inf.ed.ac.uk WholeTranslationState *state = 5328443Sgblack@eecs.umich.edu new WholeTranslationState(req, newData, res, mode); 5338486Sgblack@eecs.umich.edu DataTranslation<TimingSimpleCPU *> *translation = 5348486Sgblack@eecs.umich.edu new DataTranslation<TimingSimpleCPU *>(this, state); 53511147Smitch.hayenga@arm.com thread->dtb->translateTiming(req, thread->getTC(), translation, mode); 5362623SN/A } 5372623SN/A 5387045Ssteve.reinhardt@amd.com // Translation faults will be returned via finishTranslation() 5395728Sgblack@eecs.umich.edu return NoFault; 5402623SN/A} 5412623SN/A 54211148Smitch.hayenga@arm.comvoid 54311148Smitch.hayenga@arm.comTimingSimpleCPU::threadSnoop(PacketPtr pkt, ThreadID sender) 54411148Smitch.hayenga@arm.com{ 54511148Smitch.hayenga@arm.com for (ThreadID tid = 0; tid < numThreads; tid++) { 54611148Smitch.hayenga@arm.com if (tid != sender) { 54711148Smitch.hayenga@arm.com if(getCpuAddrMonitor(tid)->doMonitor(pkt)) { 54811148Smitch.hayenga@arm.com wakeup(); 54911148Smitch.hayenga@arm.com } 55011148Smitch.hayenga@arm.com TheISA::handleLockedSnoop(threadInfo[tid]->thread, pkt, 55111148Smitch.hayenga@arm.com dcachePort.cacheBlockMask); 55211148Smitch.hayenga@arm.com } 55311148Smitch.hayenga@arm.com } 55411148Smitch.hayenga@arm.com} 5552623SN/A 5562623SN/Avoid 5576973Stjones1@inf.ed.ac.ukTimingSimpleCPU::finishTranslation(WholeTranslationState *state) 5586973Stjones1@inf.ed.ac.uk{ 5599342SAndreas.Sandberg@arm.com _status = BaseSimpleCPU::Running; 5606973Stjones1@inf.ed.ac.uk 5616973Stjones1@inf.ed.ac.uk if (state->getFault() != NoFault) { 5626973Stjones1@inf.ed.ac.uk if (state->isPrefetch()) { 5636973Stjones1@inf.ed.ac.uk state->setNoFault(); 5646973Stjones1@inf.ed.ac.uk } 5657691SAli.Saidi@ARM.com delete [] state->data; 5666973Stjones1@inf.ed.ac.uk state->deleteReqs(); 5676973Stjones1@inf.ed.ac.uk translationFault(state->getFault()); 5686973Stjones1@inf.ed.ac.uk } else { 5696973Stjones1@inf.ed.ac.uk if (!state->isSplit) { 5706973Stjones1@inf.ed.ac.uk sendData(state->mainReq, state->data, state->res, 5716973Stjones1@inf.ed.ac.uk state->mode == BaseTLB::Read); 5726973Stjones1@inf.ed.ac.uk } else { 5736973Stjones1@inf.ed.ac.uk sendSplitData(state->sreqLow, state->sreqHigh, state->mainReq, 5746973Stjones1@inf.ed.ac.uk state->data, state->mode == BaseTLB::Read); 5756973Stjones1@inf.ed.ac.uk } 5766973Stjones1@inf.ed.ac.uk } 5776973Stjones1@inf.ed.ac.uk 5786973Stjones1@inf.ed.ac.uk delete state; 5796973Stjones1@inf.ed.ac.uk} 5806973Stjones1@inf.ed.ac.uk 5816973Stjones1@inf.ed.ac.uk 5826973Stjones1@inf.ed.ac.ukvoid 5832623SN/ATimingSimpleCPU::fetch() 5842623SN/A{ 58511147Smitch.hayenga@arm.com // Change thread if multi-threaded 58611147Smitch.hayenga@arm.com swapActiveThread(); 58711147Smitch.hayenga@arm.com 58811147Smitch.hayenga@arm.com SimpleExecContext &t_info = *threadInfo[curThread]; 58911147Smitch.hayenga@arm.com SimpleThread* thread = t_info.thread; 59011147Smitch.hayenga@arm.com 5915221Ssaidi@eecs.umich.edu DPRINTF(SimpleCPU, "Fetch\n"); 5925221Ssaidi@eecs.umich.edu 59310596Sgabeblack@google.com if (!curStaticInst || !curStaticInst->isDelayedCommit()) { 5943387Sgblack@eecs.umich.edu checkForInterrupts(); 59510596Sgabeblack@google.com checkPcEventQueue(); 59610596Sgabeblack@google.com } 5975348Ssaidi@eecs.umich.edu 5988143SAli.Saidi@ARM.com // We must have just got suspended by a PC event 5998143SAli.Saidi@ARM.com if (_status == Idle) 6008143SAli.Saidi@ARM.com return; 6018143SAli.Saidi@ARM.com 6027720Sgblack@eecs.umich.edu TheISA::PCState pcState = thread->pcState(); 60311147Smitch.hayenga@arm.com bool needToFetch = !isRomMicroPC(pcState.microPC()) && 60411147Smitch.hayenga@arm.com !curMacroStaticInst; 6052623SN/A 6067720Sgblack@eecs.umich.edu if (needToFetch) { 6079342SAndreas.Sandberg@arm.com _status = BaseSimpleCPU::Running; 6085669Sgblack@eecs.umich.edu Request *ifetch_req = new Request(); 60910024Sdam.sunwoo@arm.com ifetch_req->taskId(taskId()); 61011147Smitch.hayenga@arm.com ifetch_req->setThreadContext(thread->contextId(), curThread); 6115894Sgblack@eecs.umich.edu setupFetchRequest(ifetch_req); 6128277SAli.Saidi@ARM.com DPRINTF(SimpleCPU, "Translating address %#x\n", ifetch_req->getVaddr()); 61311147Smitch.hayenga@arm.com thread->itb->translateTiming(ifetch_req, thread->getTC(), 61411147Smitch.hayenga@arm.com &fetchTranslation, BaseTLB::Execute); 6152623SN/A } else { 6165669Sgblack@eecs.umich.edu _status = IcacheWaitResponse; 6175669Sgblack@eecs.umich.edu completeIfetch(NULL); 6185894Sgblack@eecs.umich.edu 61910464SAndreas.Sandberg@ARM.com updateCycleCounts(); 6205894Sgblack@eecs.umich.edu } 6215894Sgblack@eecs.umich.edu} 6225894Sgblack@eecs.umich.edu 6235894Sgblack@eecs.umich.edu 6245894Sgblack@eecs.umich.eduvoid 62510379Sandreas.hansson@arm.comTimingSimpleCPU::sendFetch(const Fault &fault, RequestPtr req, 62610379Sandreas.hansson@arm.com ThreadContext *tc) 6275894Sgblack@eecs.umich.edu{ 6285894Sgblack@eecs.umich.edu if (fault == NoFault) { 6298277SAli.Saidi@ARM.com DPRINTF(SimpleCPU, "Sending fetch for addr %#x(pa: %#x)\n", 6308277SAli.Saidi@ARM.com req->getVaddr(), req->getPaddr()); 6318949Sandreas.hansson@arm.com ifetch_pkt = new Packet(req, MemCmd::ReadReq); 6325894Sgblack@eecs.umich.edu ifetch_pkt->dataStatic(&inst); 6338277SAli.Saidi@ARM.com DPRINTF(SimpleCPU, " -- pkt addr: %#x\n", ifetch_pkt->getAddr()); 6345894Sgblack@eecs.umich.edu 6358975Sandreas.hansson@arm.com if (!icachePort.sendTimingReq(ifetch_pkt)) { 6365894Sgblack@eecs.umich.edu // Need to wait for retry 6375894Sgblack@eecs.umich.edu _status = IcacheRetry; 6385894Sgblack@eecs.umich.edu } else { 6395894Sgblack@eecs.umich.edu // Need to wait for cache to respond 6405894Sgblack@eecs.umich.edu _status = IcacheWaitResponse; 6415894Sgblack@eecs.umich.edu // ownership of packet transferred to memory system 6425894Sgblack@eecs.umich.edu ifetch_pkt = NULL; 6435894Sgblack@eecs.umich.edu } 6445894Sgblack@eecs.umich.edu } else { 6458277SAli.Saidi@ARM.com DPRINTF(SimpleCPU, "Translation of addr %#x faulted\n", req->getVaddr()); 6465894Sgblack@eecs.umich.edu delete req; 6475894Sgblack@eecs.umich.edu // fetch fault: advance directly to next instruction (fault handler) 6489342SAndreas.Sandberg@arm.com _status = BaseSimpleCPU::Running; 6495894Sgblack@eecs.umich.edu advanceInst(fault); 6502623SN/A } 6513222Sktlim@umich.edu 65210464SAndreas.Sandberg@ARM.com updateCycleCounts(); 6532623SN/A} 6542623SN/A 6552623SN/A 6562623SN/Avoid 65710379Sandreas.hansson@arm.comTimingSimpleCPU::advanceInst(const Fault &fault) 6582623SN/A{ 65911147Smitch.hayenga@arm.com SimpleExecContext &t_info = *threadInfo[curThread]; 66011147Smitch.hayenga@arm.com 6618276SAli.Saidi@ARM.com if (_status == Faulting) 6628276SAli.Saidi@ARM.com return; 6638276SAli.Saidi@ARM.com 6648276SAli.Saidi@ARM.com if (fault != NoFault) { 6658276SAli.Saidi@ARM.com advancePC(fault); 6668276SAli.Saidi@ARM.com DPRINTF(SimpleCPU, "Fault occured, scheduling fetch event\n"); 6679648Sdam.sunwoo@arm.com reschedule(fetchEvent, clockEdge(), true); 6688276SAli.Saidi@ARM.com _status = Faulting; 6698276SAli.Saidi@ARM.com return; 6708276SAli.Saidi@ARM.com } 6718276SAli.Saidi@ARM.com 6728276SAli.Saidi@ARM.com 67311147Smitch.hayenga@arm.com if (!t_info.stayAtPC) 6745726Sgblack@eecs.umich.edu advancePC(fault); 6752623SN/A 6769442SAndreas.Sandberg@ARM.com if (tryCompleteDrain()) 6779442SAndreas.Sandberg@ARM.com return; 6789442SAndreas.Sandberg@ARM.com 6799342SAndreas.Sandberg@arm.com if (_status == BaseSimpleCPU::Running) { 6802631SN/A // kick off fetch of next instruction... callback from icache 6812631SN/A // response will cause that instruction to be executed, 6822631SN/A // keeping the CPU running. 6832631SN/A fetch(); 6842631SN/A } 6852623SN/A} 6862623SN/A 6872623SN/A 6882623SN/Avoid 6893349Sbinkertn@umich.eduTimingSimpleCPU::completeIfetch(PacketPtr pkt) 6902623SN/A{ 69111147Smitch.hayenga@arm.com SimpleExecContext& t_info = *threadInfo[curThread]; 69211147Smitch.hayenga@arm.com 6938277SAli.Saidi@ARM.com DPRINTF(SimpleCPU, "Complete ICache Fetch for addr %#x\n", pkt ? 6948277SAli.Saidi@ARM.com pkt->getAddr() : 0); 6958277SAli.Saidi@ARM.com 6962623SN/A // received a response from the icache: execute the received 6972623SN/A // instruction 6985669Sgblack@eecs.umich.edu assert(!pkt || !pkt->isError()); 6992623SN/A assert(_status == IcacheWaitResponse); 7002798Sktlim@umich.edu 7019342SAndreas.Sandberg@arm.com _status = BaseSimpleCPU::Running; 7022644Sstever@eecs.umich.edu 70310464SAndreas.Sandberg@ARM.com updateCycleCounts(); 7043222Sktlim@umich.edu 70510020Smatt.horsnell@ARM.com if (pkt) 70610020Smatt.horsnell@ARM.com pkt->req->setAccessLatency(); 70710020Smatt.horsnell@ARM.com 70810020Smatt.horsnell@ARM.com 7092623SN/A preExecute(); 7107725SAli.Saidi@ARM.com if (curStaticInst && curStaticInst->isMemRef()) { 7112623SN/A // load or store: just send to dcache 71211147Smitch.hayenga@arm.com Fault fault = curStaticInst->initiateAcc(&t_info, traceData); 7137945SAli.Saidi@ARM.com 7147945SAli.Saidi@ARM.com // If we're not running now the instruction will complete in a dcache 7157945SAli.Saidi@ARM.com // response callback or the instruction faulted and has started an 7167945SAli.Saidi@ARM.com // ifetch 7179342SAndreas.Sandberg@arm.com if (_status == BaseSimpleCPU::Running) { 7185894Sgblack@eecs.umich.edu if (fault != NoFault && traceData) { 7195001Sgblack@eecs.umich.edu // If there was a fault, we shouldn't trace this instruction. 7205001Sgblack@eecs.umich.edu delete traceData; 7215001Sgblack@eecs.umich.edu traceData = NULL; 7223170Sstever@eecs.umich.edu } 7234998Sgblack@eecs.umich.edu 7242644Sstever@eecs.umich.edu postExecute(); 7255103Ssaidi@eecs.umich.edu // @todo remove me after debugging with legion done 7265103Ssaidi@eecs.umich.edu if (curStaticInst && (!curStaticInst->isMicroop() || 7275103Ssaidi@eecs.umich.edu curStaticInst->isFirstMicroop())) 7285103Ssaidi@eecs.umich.edu instCnt++; 7292644Sstever@eecs.umich.edu advanceInst(fault); 7302644Sstever@eecs.umich.edu } 7315726Sgblack@eecs.umich.edu } else if (curStaticInst) { 7322623SN/A // non-memory instruction: execute completely now 73311147Smitch.hayenga@arm.com Fault fault = curStaticInst->execute(&t_info, traceData); 7344998Sgblack@eecs.umich.edu 7354998Sgblack@eecs.umich.edu // keep an instruction count 7364998Sgblack@eecs.umich.edu if (fault == NoFault) 7374998Sgblack@eecs.umich.edu countInst(); 7387655Sali.saidi@arm.com else if (traceData && !DTRACE(ExecFaulting)) { 7395001Sgblack@eecs.umich.edu delete traceData; 7405001Sgblack@eecs.umich.edu traceData = NULL; 7415001Sgblack@eecs.umich.edu } 7424998Sgblack@eecs.umich.edu 7432644Sstever@eecs.umich.edu postExecute(); 7445103Ssaidi@eecs.umich.edu // @todo remove me after debugging with legion done 7455103Ssaidi@eecs.umich.edu if (curStaticInst && (!curStaticInst->isMicroop() || 74611147Smitch.hayenga@arm.com curStaticInst->isFirstMicroop())) 7475103Ssaidi@eecs.umich.edu instCnt++; 7482644Sstever@eecs.umich.edu advanceInst(fault); 7495726Sgblack@eecs.umich.edu } else { 7505726Sgblack@eecs.umich.edu advanceInst(NoFault); 7512623SN/A } 7523658Sktlim@umich.edu 7535669Sgblack@eecs.umich.edu if (pkt) { 7545669Sgblack@eecs.umich.edu delete pkt->req; 7555669Sgblack@eecs.umich.edu delete pkt; 7565669Sgblack@eecs.umich.edu } 7572623SN/A} 7582623SN/A 7592948Ssaidi@eecs.umich.eduvoid 7602948Ssaidi@eecs.umich.eduTimingSimpleCPU::IcachePort::ITickEvent::process() 7612948Ssaidi@eecs.umich.edu{ 7622948Ssaidi@eecs.umich.edu cpu->completeIfetch(pkt); 7632948Ssaidi@eecs.umich.edu} 7642623SN/A 7652623SN/Abool 7668975Sandreas.hansson@arm.comTimingSimpleCPU::IcachePort::recvTimingResp(PacketPtr pkt) 7672623SN/A{ 76810669Sandreas.hansson@arm.com DPRINTF(SimpleCPU, "Received fetch response %#x\n", pkt->getAddr()); 76910669Sandreas.hansson@arm.com // we should only ever see one response per cycle since we only 77010669Sandreas.hansson@arm.com // issue a new request once this response is sunk 77110669Sandreas.hansson@arm.com assert(!tickEvent.scheduled()); 7729165Sandreas.hansson@arm.com // delay processing of returned data until next CPU clock edge 77310669Sandreas.hansson@arm.com tickEvent.schedule(pkt, cpu->clockEdge()); 7748948Sandreas.hansson@arm.com 7754433Ssaidi@eecs.umich.edu return true; 7762623SN/A} 7772623SN/A 7782657Ssaidi@eecs.umich.eduvoid 77910713Sandreas.hansson@arm.comTimingSimpleCPU::IcachePort::recvReqRetry() 7802623SN/A{ 7812623SN/A // we shouldn't get a retry unless we have a packet that we're 7822623SN/A // waiting to transmit 7832623SN/A assert(cpu->ifetch_pkt != NULL); 7842623SN/A assert(cpu->_status == IcacheRetry); 7853349Sbinkertn@umich.edu PacketPtr tmp = cpu->ifetch_pkt; 7868975Sandreas.hansson@arm.com if (sendTimingReq(tmp)) { 7872657Ssaidi@eecs.umich.edu cpu->_status = IcacheWaitResponse; 7882657Ssaidi@eecs.umich.edu cpu->ifetch_pkt = NULL; 7892657Ssaidi@eecs.umich.edu } 7902623SN/A} 7912623SN/A 7922623SN/Avoid 7933349Sbinkertn@umich.eduTimingSimpleCPU::completeDataAccess(PacketPtr pkt) 7942623SN/A{ 7952623SN/A // received a response from the dcache: complete the load or store 7962623SN/A // instruction 7974870Sstever@eecs.umich.edu assert(!pkt->isError()); 7987516Shestness@cs.utexas.edu assert(_status == DcacheWaitResponse || _status == DTBWaitResponse || 7997516Shestness@cs.utexas.edu pkt->req->getFlags().isSet(Request::NO_ACCESS)); 8002623SN/A 80110020Smatt.horsnell@ARM.com pkt->req->setAccessLatency(); 80210464SAndreas.Sandberg@ARM.com 80310464SAndreas.Sandberg@ARM.com updateCycleCounts(); 8043184Srdreslin@umich.edu 8055728Sgblack@eecs.umich.edu if (pkt->senderState) { 8065728Sgblack@eecs.umich.edu SplitFragmentSenderState * send_state = 8075728Sgblack@eecs.umich.edu dynamic_cast<SplitFragmentSenderState *>(pkt->senderState); 8085728Sgblack@eecs.umich.edu assert(send_state); 8095728Sgblack@eecs.umich.edu delete pkt->req; 8105728Sgblack@eecs.umich.edu delete pkt; 8115728Sgblack@eecs.umich.edu PacketPtr big_pkt = send_state->bigPkt; 8125728Sgblack@eecs.umich.edu delete send_state; 8135728Sgblack@eecs.umich.edu 8145728Sgblack@eecs.umich.edu SplitMainSenderState * main_send_state = 8155728Sgblack@eecs.umich.edu dynamic_cast<SplitMainSenderState *>(big_pkt->senderState); 8165728Sgblack@eecs.umich.edu assert(main_send_state); 8175728Sgblack@eecs.umich.edu // Record the fact that this packet is no longer outstanding. 8185728Sgblack@eecs.umich.edu assert(main_send_state->outstanding != 0); 8195728Sgblack@eecs.umich.edu main_send_state->outstanding--; 8205728Sgblack@eecs.umich.edu 8215728Sgblack@eecs.umich.edu if (main_send_state->outstanding) { 8225728Sgblack@eecs.umich.edu return; 8235728Sgblack@eecs.umich.edu } else { 8245728Sgblack@eecs.umich.edu delete main_send_state; 8255728Sgblack@eecs.umich.edu big_pkt->senderState = NULL; 8265728Sgblack@eecs.umich.edu pkt = big_pkt; 8275728Sgblack@eecs.umich.edu } 8285728Sgblack@eecs.umich.edu } 8295728Sgblack@eecs.umich.edu 8309342SAndreas.Sandberg@arm.com _status = BaseSimpleCPU::Running; 8315728Sgblack@eecs.umich.edu 83211147Smitch.hayenga@arm.com Fault fault = curStaticInst->completeAcc(pkt, threadInfo[curThread], 83311147Smitch.hayenga@arm.com traceData); 8342623SN/A 8354998Sgblack@eecs.umich.edu // keep an instruction count 8364998Sgblack@eecs.umich.edu if (fault == NoFault) 8374998Sgblack@eecs.umich.edu countInst(); 8385001Sgblack@eecs.umich.edu else if (traceData) { 8395001Sgblack@eecs.umich.edu // If there was a fault, we shouldn't trace this instruction. 8405001Sgblack@eecs.umich.edu delete traceData; 8415001Sgblack@eecs.umich.edu traceData = NULL; 8425001Sgblack@eecs.umich.edu } 8434998Sgblack@eecs.umich.edu 8442644Sstever@eecs.umich.edu delete pkt->req; 8452644Sstever@eecs.umich.edu delete pkt; 8462644Sstever@eecs.umich.edu 8473184Srdreslin@umich.edu postExecute(); 8483227Sktlim@umich.edu 8492644Sstever@eecs.umich.edu advanceInst(fault); 8502623SN/A} 8512623SN/A 85210030SAli.Saidi@ARM.comvoid 85310464SAndreas.Sandberg@ARM.comTimingSimpleCPU::updateCycleCounts() 85410464SAndreas.Sandberg@ARM.com{ 85510464SAndreas.Sandberg@ARM.com const Cycles delta(curCycle() - previousCycle); 85610464SAndreas.Sandberg@ARM.com 85710464SAndreas.Sandberg@ARM.com numCycles += delta; 85810464SAndreas.Sandberg@ARM.com ppCycles->notify(delta); 85910464SAndreas.Sandberg@ARM.com 86010464SAndreas.Sandberg@ARM.com previousCycle = curCycle(); 86110464SAndreas.Sandberg@ARM.com} 86210464SAndreas.Sandberg@ARM.com 86310464SAndreas.Sandberg@ARM.comvoid 86410030SAli.Saidi@ARM.comTimingSimpleCPU::DcachePort::recvTimingSnoopReq(PacketPtr pkt) 86510030SAli.Saidi@ARM.com{ 86611148Smitch.hayenga@arm.com for (ThreadID tid = 0; tid < cpu->numThreads; tid++) { 86711148Smitch.hayenga@arm.com if (cpu->getCpuAddrMonitor(tid)->doMonitor(pkt)) { 86811148Smitch.hayenga@arm.com cpu->wakeup(); 86911148Smitch.hayenga@arm.com } 87010529Smorr@cs.wisc.edu } 87111147Smitch.hayenga@arm.com 87211147Smitch.hayenga@arm.com for (auto &t_info : cpu->threadInfo) { 87311147Smitch.hayenga@arm.com TheISA::handleLockedSnoop(t_info->thread, pkt, cacheBlockMask); 87411147Smitch.hayenga@arm.com } 87510030SAli.Saidi@ARM.com} 87610030SAli.Saidi@ARM.com 87710529Smorr@cs.wisc.eduvoid 87810529Smorr@cs.wisc.eduTimingSimpleCPU::DcachePort::recvFunctionalSnoop(PacketPtr pkt) 87910529Smorr@cs.wisc.edu{ 88011148Smitch.hayenga@arm.com for (ThreadID tid = 0; tid < cpu->numThreads; tid++) { 88111148Smitch.hayenga@arm.com if(cpu->getCpuAddrMonitor(tid)->doMonitor(pkt)) { 88211148Smitch.hayenga@arm.com cpu->wakeup(); 88311148Smitch.hayenga@arm.com } 88410529Smorr@cs.wisc.edu } 88510529Smorr@cs.wisc.edu} 88610030SAli.Saidi@ARM.com 8872623SN/Abool 8888975Sandreas.hansson@arm.comTimingSimpleCPU::DcachePort::recvTimingResp(PacketPtr pkt) 8892623SN/A{ 89010669Sandreas.hansson@arm.com DPRINTF(SimpleCPU, "Received load/store response %#x\n", pkt->getAddr()); 8912948Ssaidi@eecs.umich.edu 89210669Sandreas.hansson@arm.com // The timing CPU is not really ticked, instead it relies on the 89310669Sandreas.hansson@arm.com // memory system (fetch and load/store) to set the pace. 89410669Sandreas.hansson@arm.com if (!tickEvent.scheduled()) { 89510669Sandreas.hansson@arm.com // Delay processing of returned data until next CPU clock edge 89610669Sandreas.hansson@arm.com tickEvent.schedule(pkt, cpu->clockEdge()); 89710669Sandreas.hansson@arm.com return true; 8989165Sandreas.hansson@arm.com } else { 89910669Sandreas.hansson@arm.com // In the case of a split transaction and a cache that is 90010669Sandreas.hansson@arm.com // faster than a CPU we could get two responses in the 90110669Sandreas.hansson@arm.com // same tick, delay the second one 90210713Sandreas.hansson@arm.com if (!retryRespEvent.scheduled()) 90310713Sandreas.hansson@arm.com cpu->schedule(retryRespEvent, cpu->clockEdge(Cycles(1))); 90410669Sandreas.hansson@arm.com return false; 9053310Srdreslin@umich.edu } 9062948Ssaidi@eecs.umich.edu} 9072948Ssaidi@eecs.umich.edu 9082948Ssaidi@eecs.umich.eduvoid 9092948Ssaidi@eecs.umich.eduTimingSimpleCPU::DcachePort::DTickEvent::process() 9102948Ssaidi@eecs.umich.edu{ 9112630SN/A cpu->completeDataAccess(pkt); 9122623SN/A} 9132623SN/A 9142657Ssaidi@eecs.umich.eduvoid 91510713Sandreas.hansson@arm.comTimingSimpleCPU::DcachePort::recvReqRetry() 9162623SN/A{ 9172623SN/A // we shouldn't get a retry unless we have a packet that we're 9182623SN/A // waiting to transmit 9192623SN/A assert(cpu->dcache_pkt != NULL); 9202623SN/A assert(cpu->_status == DcacheRetry); 9213349Sbinkertn@umich.edu PacketPtr tmp = cpu->dcache_pkt; 9225728Sgblack@eecs.umich.edu if (tmp->senderState) { 9235728Sgblack@eecs.umich.edu // This is a packet from a split access. 9245728Sgblack@eecs.umich.edu SplitFragmentSenderState * send_state = 9255728Sgblack@eecs.umich.edu dynamic_cast<SplitFragmentSenderState *>(tmp->senderState); 9265728Sgblack@eecs.umich.edu assert(send_state); 9275728Sgblack@eecs.umich.edu PacketPtr big_pkt = send_state->bigPkt; 9285728Sgblack@eecs.umich.edu 9295728Sgblack@eecs.umich.edu SplitMainSenderState * main_send_state = 9305728Sgblack@eecs.umich.edu dynamic_cast<SplitMainSenderState *>(big_pkt->senderState); 9315728Sgblack@eecs.umich.edu assert(main_send_state); 9325728Sgblack@eecs.umich.edu 9338975Sandreas.hansson@arm.com if (sendTimingReq(tmp)) { 9345728Sgblack@eecs.umich.edu // If we were able to send without retrying, record that fact 9355728Sgblack@eecs.umich.edu // and try sending the other fragment. 9365728Sgblack@eecs.umich.edu send_state->clearFromParent(); 9375728Sgblack@eecs.umich.edu int other_index = main_send_state->getPendingFragment(); 9385728Sgblack@eecs.umich.edu if (other_index > 0) { 9395728Sgblack@eecs.umich.edu tmp = main_send_state->fragments[other_index]; 9405728Sgblack@eecs.umich.edu cpu->dcache_pkt = tmp; 9415728Sgblack@eecs.umich.edu if ((big_pkt->isRead() && cpu->handleReadPacket(tmp)) || 9425728Sgblack@eecs.umich.edu (big_pkt->isWrite() && cpu->handleWritePacket())) { 9435728Sgblack@eecs.umich.edu main_send_state->fragments[other_index] = NULL; 9445728Sgblack@eecs.umich.edu } 9455728Sgblack@eecs.umich.edu } else { 9465728Sgblack@eecs.umich.edu cpu->_status = DcacheWaitResponse; 9475728Sgblack@eecs.umich.edu // memory system takes ownership of packet 9485728Sgblack@eecs.umich.edu cpu->dcache_pkt = NULL; 9495728Sgblack@eecs.umich.edu } 9505728Sgblack@eecs.umich.edu } 9518975Sandreas.hansson@arm.com } else if (sendTimingReq(tmp)) { 9522657Ssaidi@eecs.umich.edu cpu->_status = DcacheWaitResponse; 9533170Sstever@eecs.umich.edu // memory system takes ownership of packet 9542657Ssaidi@eecs.umich.edu cpu->dcache_pkt = NULL; 9552657Ssaidi@eecs.umich.edu } 9562623SN/A} 9572623SN/A 9585606Snate@binkert.orgTimingSimpleCPU::IprEvent::IprEvent(Packet *_pkt, TimingSimpleCPU *_cpu, 9595606Snate@binkert.org Tick t) 9605606Snate@binkert.org : pkt(_pkt), cpu(_cpu) 9615103Ssaidi@eecs.umich.edu{ 9625606Snate@binkert.org cpu->schedule(this, t); 9635103Ssaidi@eecs.umich.edu} 9645103Ssaidi@eecs.umich.edu 9655103Ssaidi@eecs.umich.eduvoid 9665103Ssaidi@eecs.umich.eduTimingSimpleCPU::IprEvent::process() 9675103Ssaidi@eecs.umich.edu{ 9685103Ssaidi@eecs.umich.edu cpu->completeDataAccess(pkt); 9695103Ssaidi@eecs.umich.edu} 9705103Ssaidi@eecs.umich.edu 9715103Ssaidi@eecs.umich.educonst char * 9725336Shines@cs.fsu.eduTimingSimpleCPU::IprEvent::description() const 9735103Ssaidi@eecs.umich.edu{ 9745103Ssaidi@eecs.umich.edu return "Timing Simple CPU Delay IPR event"; 9755103Ssaidi@eecs.umich.edu} 9765103Ssaidi@eecs.umich.edu 9772623SN/A 9785315Sstever@gmail.comvoid 9795315Sstever@gmail.comTimingSimpleCPU::printAddr(Addr a) 9805315Sstever@gmail.com{ 9815315Sstever@gmail.com dcachePort.printAddr(a); 9825315Sstever@gmail.com} 9835315Sstever@gmail.com 9845315Sstever@gmail.com 9852623SN/A//////////////////////////////////////////////////////////////////////// 9862623SN/A// 9872623SN/A// TimingSimpleCPU Simulation Object 9882623SN/A// 9894762Snate@binkert.orgTimingSimpleCPU * 9904762Snate@binkert.orgTimingSimpleCPUParams::create() 9912623SN/A{ 9925529Snate@binkert.org return new TimingSimpleCPU(this); 9932623SN/A} 994