timing.cc revision 11147
12623SN/A/* 210596Sgabeblack@google.com * Copyright 2014 Google, Inc. 311147Smitch.hayenga@arm.com * Copyright (c) 2010-2013,2015 ARM Limited 47725SAli.Saidi@ARM.com * All rights reserved 57725SAli.Saidi@ARM.com * 67725SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall 77725SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 87725SAli.Saidi@ARM.com * property including but not limited to intellectual property relating 97725SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software 107725SAli.Saidi@ARM.com * licensed hereunder. You may use the software subject to the license 117725SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated 127725SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software, 137725SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form. 147725SAli.Saidi@ARM.com * 152623SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 162623SN/A * All rights reserved. 172623SN/A * 182623SN/A * Redistribution and use in source and binary forms, with or without 192623SN/A * modification, are permitted provided that the following conditions are 202623SN/A * met: redistributions of source code must retain the above copyright 212623SN/A * notice, this list of conditions and the following disclaimer; 222623SN/A * redistributions in binary form must reproduce the above copyright 232623SN/A * notice, this list of conditions and the following disclaimer in the 242623SN/A * documentation and/or other materials provided with the distribution; 252623SN/A * neither the name of the copyright holders nor the names of its 262623SN/A * contributors may be used to endorse or promote products derived from 272623SN/A * this software without specific prior written permission. 282623SN/A * 292623SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 302623SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 312623SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 322623SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 332623SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 342623SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 352623SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 362623SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 372623SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 382623SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 392623SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402665Ssaidi@eecs.umich.edu * 412665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 422623SN/A */ 432623SN/A 443170Sstever@eecs.umich.edu#include "arch/locked_mem.hh" 458105Sgblack@eecs.umich.edu#include "arch/mmapped_ipr.hh" 462623SN/A#include "arch/utility.hh" 474040Ssaidi@eecs.umich.edu#include "base/bigint.hh" 486658Snate@binkert.org#include "config/the_isa.hh" 498229Snate@binkert.org#include "cpu/simple/timing.hh" 502623SN/A#include "cpu/exetrace.hh" 518232Snate@binkert.org#include "debug/Config.hh" 529152Satgutier@umich.edu#include "debug/Drain.hh" 538232Snate@binkert.org#include "debug/ExecFaulting.hh" 548232Snate@binkert.org#include "debug/SimpleCPU.hh" 553348Sbinkertn@umich.edu#include "mem/packet.hh" 563348Sbinkertn@umich.edu#include "mem/packet_access.hh" 574762Snate@binkert.org#include "params/TimingSimpleCPU.hh" 587678Sgblack@eecs.umich.edu#include "sim/faults.hh" 598779Sgblack@eecs.umich.edu#include "sim/full_system.hh" 602901Ssaidi@eecs.umich.edu#include "sim/system.hh" 612623SN/A 6210529Smorr@cs.wisc.edu#include "debug/Mwait.hh" 6310529Smorr@cs.wisc.edu 642623SN/Ausing namespace std; 652623SN/Ausing namespace TheISA; 662623SN/A 672623SN/Avoid 682623SN/ATimingSimpleCPU::init() 692623SN/A{ 7011147Smitch.hayenga@arm.com BaseSimpleCPU::init(); 712623SN/A} 722623SN/A 732623SN/Avoid 748707Sandreas.hansson@arm.comTimingSimpleCPU::TimingCPUPort::TickEvent::schedule(PacketPtr _pkt, Tick t) 752948Ssaidi@eecs.umich.edu{ 762948Ssaidi@eecs.umich.edu pkt = _pkt; 775606Snate@binkert.org cpu->schedule(this, t); 782948Ssaidi@eecs.umich.edu} 792948Ssaidi@eecs.umich.edu 805529Snate@binkert.orgTimingSimpleCPU::TimingSimpleCPU(TimingSimpleCPUParams *p) 818707Sandreas.hansson@arm.com : BaseSimpleCPU(p), fetchTranslation(this), icachePort(this), 829179Sandreas.hansson@arm.com dcachePort(this), ifetch_pkt(NULL), dcache_pkt(NULL), previousCycle(0), 8310913Sandreas.sandberg@arm.com fetchEvent(this) 842623SN/A{ 852623SN/A _status = Idle; 862623SN/A} 872623SN/A 882623SN/A 8910030SAli.Saidi@ARM.com 902623SN/ATimingSimpleCPU::~TimingSimpleCPU() 912623SN/A{ 922623SN/A} 932623SN/A 9410913Sandreas.sandberg@arm.comDrainState 9510913Sandreas.sandberg@arm.comTimingSimpleCPU::drain() 962798Sktlim@umich.edu{ 979448SAndreas.Sandberg@ARM.com if (switchedOut()) 9810913Sandreas.sandberg@arm.com return DrainState::Drained; 999448SAndreas.Sandberg@ARM.com 1009342SAndreas.Sandberg@arm.com if (_status == Idle || 1019448SAndreas.Sandberg@ARM.com (_status == BaseSimpleCPU::Running && isDrained())) { 1029442SAndreas.Sandberg@ARM.com DPRINTF(Drain, "No need to drain.\n"); 10311147Smitch.hayenga@arm.com activeThreads.clear(); 10410913Sandreas.sandberg@arm.com return DrainState::Drained; 1052798Sktlim@umich.edu } else { 10611147Smitch.hayenga@arm.com DPRINTF(Drain, "Requesting drain.\n"); 1079442SAndreas.Sandberg@ARM.com 1089442SAndreas.Sandberg@ARM.com // The fetch event can become descheduled if a drain didn't 1099442SAndreas.Sandberg@ARM.com // succeed on the first attempt. We need to reschedule it if 1109442SAndreas.Sandberg@ARM.com // the CPU is waiting for a microcode routine to complete. 1119448SAndreas.Sandberg@ARM.com if (_status == BaseSimpleCPU::Running && !fetchEvent.scheduled()) 1129648Sdam.sunwoo@arm.com schedule(fetchEvent, clockEdge()); 1139442SAndreas.Sandberg@ARM.com 11410913Sandreas.sandberg@arm.com return DrainState::Draining; 1152798Sktlim@umich.edu } 1162623SN/A} 1172623SN/A 1182623SN/Avoid 1199342SAndreas.Sandberg@arm.comTimingSimpleCPU::drainResume() 1202623SN/A{ 1219442SAndreas.Sandberg@ARM.com assert(!fetchEvent.scheduled()); 1229448SAndreas.Sandberg@ARM.com if (switchedOut()) 1239448SAndreas.Sandberg@ARM.com return; 1249442SAndreas.Sandberg@ARM.com 1255221Ssaidi@eecs.umich.edu DPRINTF(SimpleCPU, "Resume\n"); 1269523SAndreas.Sandberg@ARM.com verifyMemoryMode(); 1273201Shsul@eecs.umich.edu 1289448SAndreas.Sandberg@ARM.com assert(!threadContexts.empty()); 1299448SAndreas.Sandberg@ARM.com 13011147Smitch.hayenga@arm.com _status = BaseSimpleCPU::Idle; 13111147Smitch.hayenga@arm.com 13211147Smitch.hayenga@arm.com for (ThreadID tid = 0; tid < numThreads; tid++) { 13311147Smitch.hayenga@arm.com if (threadInfo[tid]->thread->status() == ThreadContext::Active) { 13411147Smitch.hayenga@arm.com threadInfo[tid]->notIdleFraction = 1; 13511147Smitch.hayenga@arm.com 13611147Smitch.hayenga@arm.com activeThreads.push_back(tid); 13711147Smitch.hayenga@arm.com 13811147Smitch.hayenga@arm.com _status = BaseSimpleCPU::Running; 13911147Smitch.hayenga@arm.com 14011147Smitch.hayenga@arm.com // Fetch if any threads active 14111147Smitch.hayenga@arm.com if (!fetchEvent.scheduled()) { 14211147Smitch.hayenga@arm.com schedule(fetchEvent, nextCycle()); 14311147Smitch.hayenga@arm.com } 14411147Smitch.hayenga@arm.com } else { 14511147Smitch.hayenga@arm.com threadInfo[tid]->notIdleFraction = 0; 14611147Smitch.hayenga@arm.com } 1472623SN/A } 14811147Smitch.hayenga@arm.com 14911147Smitch.hayenga@arm.com system->totalNumInsts = 0; 1509442SAndreas.Sandberg@ARM.com} 1512798Sktlim@umich.edu 1529442SAndreas.Sandberg@ARM.combool 1539442SAndreas.Sandberg@ARM.comTimingSimpleCPU::tryCompleteDrain() 1549442SAndreas.Sandberg@ARM.com{ 15510913Sandreas.sandberg@arm.com if (drainState() != DrainState::Draining) 1569442SAndreas.Sandberg@ARM.com return false; 1579442SAndreas.Sandberg@ARM.com 15811147Smitch.hayenga@arm.com DPRINTF(Drain, "tryCompleteDrain.\n"); 1599442SAndreas.Sandberg@ARM.com if (!isDrained()) 1609442SAndreas.Sandberg@ARM.com return false; 1619442SAndreas.Sandberg@ARM.com 1629442SAndreas.Sandberg@ARM.com DPRINTF(Drain, "CPU done draining, processing drain event\n"); 16310913Sandreas.sandberg@arm.com signalDrainDone(); 1649442SAndreas.Sandberg@ARM.com 1659442SAndreas.Sandberg@ARM.com return true; 1662798Sktlim@umich.edu} 1672798Sktlim@umich.edu 1682798Sktlim@umich.eduvoid 1692798Sktlim@umich.eduTimingSimpleCPU::switchOut() 1702798Sktlim@umich.edu{ 17111147Smitch.hayenga@arm.com SimpleExecContext& t_info = *threadInfo[curThread]; 17211147Smitch.hayenga@arm.com M5_VAR_USED SimpleThread* thread = t_info.thread; 17311147Smitch.hayenga@arm.com 1749429SAndreas.Sandberg@ARM.com BaseSimpleCPU::switchOut(); 1759429SAndreas.Sandberg@ARM.com 1769442SAndreas.Sandberg@ARM.com assert(!fetchEvent.scheduled()); 1779342SAndreas.Sandberg@arm.com assert(_status == BaseSimpleCPU::Running || _status == Idle); 17811147Smitch.hayenga@arm.com assert(!t_info.stayAtPC); 17911147Smitch.hayenga@arm.com assert(thread->microPC() == 0); 1809442SAndreas.Sandberg@ARM.com 18110464SAndreas.Sandberg@ARM.com updateCycleCounts(); 1822623SN/A} 1832623SN/A 1842623SN/A 1852623SN/Avoid 1862623SN/ATimingSimpleCPU::takeOverFrom(BaseCPU *oldCPU) 1872623SN/A{ 1889429SAndreas.Sandberg@ARM.com BaseSimpleCPU::takeOverFrom(oldCPU); 1892623SN/A 1909179Sandreas.hansson@arm.com previousCycle = curCycle(); 1912623SN/A} 1922623SN/A 1939523SAndreas.Sandberg@ARM.comvoid 1949523SAndreas.Sandberg@ARM.comTimingSimpleCPU::verifyMemoryMode() const 1959523SAndreas.Sandberg@ARM.com{ 1969524SAndreas.Sandberg@ARM.com if (!system->isTimingMode()) { 1979523SAndreas.Sandberg@ARM.com fatal("The timing CPU requires the memory system to be in " 1989523SAndreas.Sandberg@ARM.com "'timing' mode.\n"); 1999523SAndreas.Sandberg@ARM.com } 2009523SAndreas.Sandberg@ARM.com} 2012623SN/A 2022623SN/Avoid 20310407Smitch.hayenga@arm.comTimingSimpleCPU::activateContext(ThreadID thread_num) 2042623SN/A{ 20510407Smitch.hayenga@arm.com DPRINTF(SimpleCPU, "ActivateContext %d\n", thread_num); 2065221Ssaidi@eecs.umich.edu 20711147Smitch.hayenga@arm.com assert(thread_num < numThreads); 2082623SN/A 20911147Smitch.hayenga@arm.com threadInfo[thread_num]->notIdleFraction = 1; 21011147Smitch.hayenga@arm.com if (_status == BaseSimpleCPU::Idle) 21111147Smitch.hayenga@arm.com _status = BaseSimpleCPU::Running; 2123686Sktlim@umich.edu 2132623SN/A // kick things off by initiating the fetch of the next instruction 21411147Smitch.hayenga@arm.com if (!fetchEvent.scheduled()) 21511147Smitch.hayenga@arm.com schedule(fetchEvent, clockEdge(Cycles(0))); 21611147Smitch.hayenga@arm.com 21711147Smitch.hayenga@arm.com if (std::find(activeThreads.begin(), activeThreads.end(), thread_num) 21811147Smitch.hayenga@arm.com == activeThreads.end()) { 21911147Smitch.hayenga@arm.com activeThreads.push_back(thread_num); 22011147Smitch.hayenga@arm.com } 2212623SN/A} 2222623SN/A 2232623SN/A 2242623SN/Avoid 2258737Skoansin.tan@gmail.comTimingSimpleCPU::suspendContext(ThreadID thread_num) 2262623SN/A{ 2275221Ssaidi@eecs.umich.edu DPRINTF(SimpleCPU, "SuspendContext %d\n", thread_num); 2285221Ssaidi@eecs.umich.edu 22911147Smitch.hayenga@arm.com assert(thread_num < numThreads); 23011147Smitch.hayenga@arm.com activeThreads.remove(thread_num); 2312623SN/A 2326043Sgblack@eecs.umich.edu if (_status == Idle) 2336043Sgblack@eecs.umich.edu return; 2346043Sgblack@eecs.umich.edu 2359342SAndreas.Sandberg@arm.com assert(_status == BaseSimpleCPU::Running); 2362623SN/A 23711147Smitch.hayenga@arm.com threadInfo[thread_num]->notIdleFraction = 0; 2382623SN/A 23911147Smitch.hayenga@arm.com if (activeThreads.empty()) { 24011147Smitch.hayenga@arm.com _status = Idle; 24111147Smitch.hayenga@arm.com 24211147Smitch.hayenga@arm.com if (fetchEvent.scheduled()) { 24311147Smitch.hayenga@arm.com deschedule(fetchEvent); 24411147Smitch.hayenga@arm.com } 24511147Smitch.hayenga@arm.com } 2462623SN/A} 2472623SN/A 2485728Sgblack@eecs.umich.edubool 2495728Sgblack@eecs.umich.eduTimingSimpleCPU::handleReadPacket(PacketPtr pkt) 2505728Sgblack@eecs.umich.edu{ 25111147Smitch.hayenga@arm.com SimpleExecContext &t_info = *threadInfo[curThread]; 25211147Smitch.hayenga@arm.com SimpleThread* thread = t_info.thread; 25311147Smitch.hayenga@arm.com 2545728Sgblack@eecs.umich.edu RequestPtr req = pkt->req; 25510533Sali.saidi@arm.com 25610533Sali.saidi@arm.com // We're about the issues a locked load, so tell the monitor 25710533Sali.saidi@arm.com // to start caring about this address 25810533Sali.saidi@arm.com if (pkt->isRead() && pkt->req->isLLSC()) { 25910533Sali.saidi@arm.com TheISA::handleLockedRead(thread, pkt->req); 26010533Sali.saidi@arm.com } 2618105Sgblack@eecs.umich.edu if (req->isMmappedIpr()) { 2629180Sandreas.hansson@arm.com Cycles delay = TheISA::handleIprRead(thread->getTC(), pkt); 2639179Sandreas.hansson@arm.com new IprEvent(pkt, this, clockEdge(delay)); 2645728Sgblack@eecs.umich.edu _status = DcacheWaitResponse; 2655728Sgblack@eecs.umich.edu dcache_pkt = NULL; 2668975Sandreas.hansson@arm.com } else if (!dcachePort.sendTimingReq(pkt)) { 2675728Sgblack@eecs.umich.edu _status = DcacheRetry; 2685728Sgblack@eecs.umich.edu dcache_pkt = pkt; 2695728Sgblack@eecs.umich.edu } else { 2705728Sgblack@eecs.umich.edu _status = DcacheWaitResponse; 2715728Sgblack@eecs.umich.edu // memory system takes ownership of packet 2725728Sgblack@eecs.umich.edu dcache_pkt = NULL; 2735728Sgblack@eecs.umich.edu } 2745728Sgblack@eecs.umich.edu return dcache_pkt == NULL; 2755728Sgblack@eecs.umich.edu} 2762623SN/A 2775894Sgblack@eecs.umich.eduvoid 2786973Stjones1@inf.ed.ac.ukTimingSimpleCPU::sendData(RequestPtr req, uint8_t *data, uint64_t *res, 2796973Stjones1@inf.ed.ac.uk bool read) 2805744Sgblack@eecs.umich.edu{ 28111147Smitch.hayenga@arm.com SimpleExecContext &t_info = *threadInfo[curThread]; 28211147Smitch.hayenga@arm.com SimpleThread* thread = t_info.thread; 28311147Smitch.hayenga@arm.com 28410653Sandreas.hansson@arm.com PacketPtr pkt = buildPacket(req, read); 28510566Sandreas.hansson@arm.com pkt->dataDynamic<uint8_t>(data); 2865894Sgblack@eecs.umich.edu if (req->getFlags().isSet(Request::NO_ACCESS)) { 2875894Sgblack@eecs.umich.edu assert(!dcache_pkt); 2885894Sgblack@eecs.umich.edu pkt->makeResponse(); 2895894Sgblack@eecs.umich.edu completeDataAccess(pkt); 2905894Sgblack@eecs.umich.edu } else if (read) { 2915894Sgblack@eecs.umich.edu handleReadPacket(pkt); 2925894Sgblack@eecs.umich.edu } else { 2935894Sgblack@eecs.umich.edu bool do_access = true; // flag to suppress cache access 2945894Sgblack@eecs.umich.edu 2956102Sgblack@eecs.umich.edu if (req->isLLSC()) { 29610030SAli.Saidi@ARM.com do_access = TheISA::handleLockedWrite(thread, req, dcachePort.cacheBlockMask); 2975894Sgblack@eecs.umich.edu } else if (req->isCondSwap()) { 2985894Sgblack@eecs.umich.edu assert(res); 2995894Sgblack@eecs.umich.edu req->setExtraData(*res); 3005894Sgblack@eecs.umich.edu } 3015894Sgblack@eecs.umich.edu 3025894Sgblack@eecs.umich.edu if (do_access) { 3035894Sgblack@eecs.umich.edu dcache_pkt = pkt; 3045894Sgblack@eecs.umich.edu handleWritePacket(); 3055894Sgblack@eecs.umich.edu } else { 3065894Sgblack@eecs.umich.edu _status = DcacheWaitResponse; 3075894Sgblack@eecs.umich.edu completeDataAccess(pkt); 3085894Sgblack@eecs.umich.edu } 3095894Sgblack@eecs.umich.edu } 3105894Sgblack@eecs.umich.edu} 3115894Sgblack@eecs.umich.edu 3125894Sgblack@eecs.umich.eduvoid 3136973Stjones1@inf.ed.ac.ukTimingSimpleCPU::sendSplitData(RequestPtr req1, RequestPtr req2, 3146973Stjones1@inf.ed.ac.uk RequestPtr req, uint8_t *data, bool read) 3155894Sgblack@eecs.umich.edu{ 3165894Sgblack@eecs.umich.edu PacketPtr pkt1, pkt2; 3175894Sgblack@eecs.umich.edu buildSplitPacket(pkt1, pkt2, req1, req2, req, data, read); 3185894Sgblack@eecs.umich.edu if (req->getFlags().isSet(Request::NO_ACCESS)) { 3195894Sgblack@eecs.umich.edu assert(!dcache_pkt); 3205894Sgblack@eecs.umich.edu pkt1->makeResponse(); 3215894Sgblack@eecs.umich.edu completeDataAccess(pkt1); 3225894Sgblack@eecs.umich.edu } else if (read) { 3237911Shestness@cs.utexas.edu SplitFragmentSenderState * send_state = 3247911Shestness@cs.utexas.edu dynamic_cast<SplitFragmentSenderState *>(pkt1->senderState); 3255894Sgblack@eecs.umich.edu if (handleReadPacket(pkt1)) { 3265894Sgblack@eecs.umich.edu send_state->clearFromParent(); 3277911Shestness@cs.utexas.edu send_state = dynamic_cast<SplitFragmentSenderState *>( 3287911Shestness@cs.utexas.edu pkt2->senderState); 3295894Sgblack@eecs.umich.edu if (handleReadPacket(pkt2)) { 3305894Sgblack@eecs.umich.edu send_state->clearFromParent(); 3315894Sgblack@eecs.umich.edu } 3325894Sgblack@eecs.umich.edu } 3335894Sgblack@eecs.umich.edu } else { 3345894Sgblack@eecs.umich.edu dcache_pkt = pkt1; 3357911Shestness@cs.utexas.edu SplitFragmentSenderState * send_state = 3367911Shestness@cs.utexas.edu dynamic_cast<SplitFragmentSenderState *>(pkt1->senderState); 3375894Sgblack@eecs.umich.edu if (handleWritePacket()) { 3385894Sgblack@eecs.umich.edu send_state->clearFromParent(); 3395894Sgblack@eecs.umich.edu dcache_pkt = pkt2; 3407911Shestness@cs.utexas.edu send_state = dynamic_cast<SplitFragmentSenderState *>( 3417911Shestness@cs.utexas.edu pkt2->senderState); 3425894Sgblack@eecs.umich.edu if (handleWritePacket()) { 3435894Sgblack@eecs.umich.edu send_state->clearFromParent(); 3445894Sgblack@eecs.umich.edu } 3455894Sgblack@eecs.umich.edu } 3465894Sgblack@eecs.umich.edu } 3475894Sgblack@eecs.umich.edu} 3485894Sgblack@eecs.umich.edu 3495894Sgblack@eecs.umich.eduvoid 35010379Sandreas.hansson@arm.comTimingSimpleCPU::translationFault(const Fault &fault) 3515894Sgblack@eecs.umich.edu{ 3526739Sgblack@eecs.umich.edu // fault may be NoFault in cases where a fault is suppressed, 3536739Sgblack@eecs.umich.edu // for instance prefetches. 35410464SAndreas.Sandberg@ARM.com updateCycleCounts(); 3555894Sgblack@eecs.umich.edu 3565894Sgblack@eecs.umich.edu if (traceData) { 3575894Sgblack@eecs.umich.edu // Since there was a fault, we shouldn't trace this instruction. 3585894Sgblack@eecs.umich.edu delete traceData; 3595894Sgblack@eecs.umich.edu traceData = NULL; 3605744Sgblack@eecs.umich.edu } 3615744Sgblack@eecs.umich.edu 3625894Sgblack@eecs.umich.edu postExecute(); 3635894Sgblack@eecs.umich.edu 3649442SAndreas.Sandberg@ARM.com advanceInst(fault); 3655894Sgblack@eecs.umich.edu} 3665894Sgblack@eecs.umich.edu 36710653Sandreas.hansson@arm.comPacketPtr 36810653Sandreas.hansson@arm.comTimingSimpleCPU::buildPacket(RequestPtr req, bool read) 3695894Sgblack@eecs.umich.edu{ 37010653Sandreas.hansson@arm.com return read ? Packet::createRead(req) : Packet::createWrite(req); 3715894Sgblack@eecs.umich.edu} 3725894Sgblack@eecs.umich.edu 3735894Sgblack@eecs.umich.eduvoid 3745894Sgblack@eecs.umich.eduTimingSimpleCPU::buildSplitPacket(PacketPtr &pkt1, PacketPtr &pkt2, 3755894Sgblack@eecs.umich.edu RequestPtr req1, RequestPtr req2, RequestPtr req, 3765894Sgblack@eecs.umich.edu uint8_t *data, bool read) 3775894Sgblack@eecs.umich.edu{ 3785894Sgblack@eecs.umich.edu pkt1 = pkt2 = NULL; 3795894Sgblack@eecs.umich.edu 3808105Sgblack@eecs.umich.edu assert(!req1->isMmappedIpr() && !req2->isMmappedIpr()); 3815744Sgblack@eecs.umich.edu 3825894Sgblack@eecs.umich.edu if (req->getFlags().isSet(Request::NO_ACCESS)) { 38310653Sandreas.hansson@arm.com pkt1 = buildPacket(req, read); 3845894Sgblack@eecs.umich.edu return; 3855894Sgblack@eecs.umich.edu } 3865894Sgblack@eecs.umich.edu 38710653Sandreas.hansson@arm.com pkt1 = buildPacket(req1, read); 38810653Sandreas.hansson@arm.com pkt2 = buildPacket(req2, read); 3895894Sgblack@eecs.umich.edu 3908949Sandreas.hansson@arm.com PacketPtr pkt = new Packet(req, pkt1->cmd.responseCommand()); 3915744Sgblack@eecs.umich.edu 39210566Sandreas.hansson@arm.com pkt->dataDynamic<uint8_t>(data); 3935744Sgblack@eecs.umich.edu pkt1->dataStatic<uint8_t>(data); 3945744Sgblack@eecs.umich.edu pkt2->dataStatic<uint8_t>(data + req1->getSize()); 3955744Sgblack@eecs.umich.edu 3965744Sgblack@eecs.umich.edu SplitMainSenderState * main_send_state = new SplitMainSenderState; 3975744Sgblack@eecs.umich.edu pkt->senderState = main_send_state; 3985744Sgblack@eecs.umich.edu main_send_state->fragments[0] = pkt1; 3995744Sgblack@eecs.umich.edu main_send_state->fragments[1] = pkt2; 4005744Sgblack@eecs.umich.edu main_send_state->outstanding = 2; 4015744Sgblack@eecs.umich.edu pkt1->senderState = new SplitFragmentSenderState(pkt, 0); 4025744Sgblack@eecs.umich.edu pkt2->senderState = new SplitFragmentSenderState(pkt, 1); 4035744Sgblack@eecs.umich.edu} 4045744Sgblack@eecs.umich.edu 4052623SN/AFault 4068444Sgblack@eecs.umich.eduTimingSimpleCPU::readMem(Addr addr, uint8_t *data, 4078444Sgblack@eecs.umich.edu unsigned size, unsigned flags) 4082623SN/A{ 40911147Smitch.hayenga@arm.com SimpleExecContext &t_info = *threadInfo[curThread]; 41011147Smitch.hayenga@arm.com SimpleThread* thread = t_info.thread; 41111147Smitch.hayenga@arm.com 4125728Sgblack@eecs.umich.edu Fault fault; 4135728Sgblack@eecs.umich.edu const int asid = 0; 41411147Smitch.hayenga@arm.com const ThreadID tid = curThread; 4157720Sgblack@eecs.umich.edu const Addr pc = thread->instAddr(); 4169814Sandreas.hansson@arm.com unsigned block_size = cacheLineSize(); 4176973Stjones1@inf.ed.ac.uk BaseTLB::Mode mode = BaseTLB::Read; 4182623SN/A 41910665SAli.Saidi@ARM.com if (traceData) 42010665SAli.Saidi@ARM.com traceData->setMem(addr, size, flags); 4217045Ssteve.reinhardt@amd.com 4227520Sgblack@eecs.umich.edu RequestPtr req = new Request(asid, addr, size, 42311147Smitch.hayenga@arm.com flags, dataMasterId(), pc, 42411147Smitch.hayenga@arm.com thread->contextId(), tid); 4255728Sgblack@eecs.umich.edu 42610024Sdam.sunwoo@arm.com req->taskId(taskId()); 42710024Sdam.sunwoo@arm.com 4287520Sgblack@eecs.umich.edu Addr split_addr = roundDown(addr + size - 1, block_size); 4295744Sgblack@eecs.umich.edu assert(split_addr <= addr || split_addr - addr < block_size); 4305728Sgblack@eecs.umich.edu 4315894Sgblack@eecs.umich.edu _status = DTBWaitResponse; 4325744Sgblack@eecs.umich.edu if (split_addr > addr) { 4335894Sgblack@eecs.umich.edu RequestPtr req1, req2; 4346102Sgblack@eecs.umich.edu assert(!req->isLLSC() && !req->isSwap()); 4355894Sgblack@eecs.umich.edu req->splitOnVaddr(split_addr, req1, req2); 4365894Sgblack@eecs.umich.edu 4376973Stjones1@inf.ed.ac.uk WholeTranslationState *state = 4387520Sgblack@eecs.umich.edu new WholeTranslationState(req, req1, req2, new uint8_t[size], 4396973Stjones1@inf.ed.ac.uk NULL, mode); 4408486Sgblack@eecs.umich.edu DataTranslation<TimingSimpleCPU *> *trans1 = 4418486Sgblack@eecs.umich.edu new DataTranslation<TimingSimpleCPU *>(this, state, 0); 4428486Sgblack@eecs.umich.edu DataTranslation<TimingSimpleCPU *> *trans2 = 4438486Sgblack@eecs.umich.edu new DataTranslation<TimingSimpleCPU *>(this, state, 1); 4446973Stjones1@inf.ed.ac.uk 44511147Smitch.hayenga@arm.com thread->dtb->translateTiming(req1, thread->getTC(), trans1, mode); 44611147Smitch.hayenga@arm.com thread->dtb->translateTiming(req2, thread->getTC(), trans2, mode); 4475744Sgblack@eecs.umich.edu } else { 4486973Stjones1@inf.ed.ac.uk WholeTranslationState *state = 4497520Sgblack@eecs.umich.edu new WholeTranslationState(req, new uint8_t[size], NULL, mode); 4508486Sgblack@eecs.umich.edu DataTranslation<TimingSimpleCPU *> *translation 4518486Sgblack@eecs.umich.edu = new DataTranslation<TimingSimpleCPU *>(this, state); 45211147Smitch.hayenga@arm.com thread->dtb->translateTiming(req, thread->getTC(), translation, mode); 4532623SN/A } 4542623SN/A 4555728Sgblack@eecs.umich.edu return NoFault; 4562623SN/A} 4572623SN/A 4585728Sgblack@eecs.umich.edubool 4595728Sgblack@eecs.umich.eduTimingSimpleCPU::handleWritePacket() 4605728Sgblack@eecs.umich.edu{ 46111147Smitch.hayenga@arm.com SimpleExecContext &t_info = *threadInfo[curThread]; 46211147Smitch.hayenga@arm.com SimpleThread* thread = t_info.thread; 46311147Smitch.hayenga@arm.com 4645728Sgblack@eecs.umich.edu RequestPtr req = dcache_pkt->req; 4658105Sgblack@eecs.umich.edu if (req->isMmappedIpr()) { 4669180Sandreas.hansson@arm.com Cycles delay = TheISA::handleIprWrite(thread->getTC(), dcache_pkt); 4679179Sandreas.hansson@arm.com new IprEvent(dcache_pkt, this, clockEdge(delay)); 4685728Sgblack@eecs.umich.edu _status = DcacheWaitResponse; 4695728Sgblack@eecs.umich.edu dcache_pkt = NULL; 4708975Sandreas.hansson@arm.com } else if (!dcachePort.sendTimingReq(dcache_pkt)) { 4715728Sgblack@eecs.umich.edu _status = DcacheRetry; 4725728Sgblack@eecs.umich.edu } else { 4735728Sgblack@eecs.umich.edu _status = DcacheWaitResponse; 4745728Sgblack@eecs.umich.edu // memory system takes ownership of packet 4755728Sgblack@eecs.umich.edu dcache_pkt = NULL; 4765728Sgblack@eecs.umich.edu } 4775728Sgblack@eecs.umich.edu return dcache_pkt == NULL; 4785728Sgblack@eecs.umich.edu} 4792623SN/A 4802623SN/AFault 4818444Sgblack@eecs.umich.eduTimingSimpleCPU::writeMem(uint8_t *data, unsigned size, 4828444Sgblack@eecs.umich.edu Addr addr, unsigned flags, uint64_t *res) 4832623SN/A{ 48411147Smitch.hayenga@arm.com SimpleExecContext &t_info = *threadInfo[curThread]; 48511147Smitch.hayenga@arm.com SimpleThread* thread = t_info.thread; 48611147Smitch.hayenga@arm.com 4878443Sgblack@eecs.umich.edu uint8_t *newData = new uint8_t[size]; 4885728Sgblack@eecs.umich.edu const int asid = 0; 48911147Smitch.hayenga@arm.com const ThreadID tid = curThread; 4907720Sgblack@eecs.umich.edu const Addr pc = thread->instAddr(); 4919814Sandreas.hansson@arm.com unsigned block_size = cacheLineSize(); 4926973Stjones1@inf.ed.ac.uk BaseTLB::Mode mode = BaseTLB::Write; 4933169Sstever@eecs.umich.edu 49410031SAli.Saidi@ARM.com if (data == NULL) { 49510031SAli.Saidi@ARM.com assert(flags & Request::CACHE_BLOCK_ZERO); 49610031SAli.Saidi@ARM.com // This must be a cache block cleaning request 49710031SAli.Saidi@ARM.com memset(newData, 0, size); 49810031SAli.Saidi@ARM.com } else { 49910031SAli.Saidi@ARM.com memcpy(newData, data, size); 50010031SAli.Saidi@ARM.com } 50110031SAli.Saidi@ARM.com 50210665SAli.Saidi@ARM.com if (traceData) 50310665SAli.Saidi@ARM.com traceData->setMem(addr, size, flags); 5047045Ssteve.reinhardt@amd.com 5057520Sgblack@eecs.umich.edu RequestPtr req = new Request(asid, addr, size, 50611147Smitch.hayenga@arm.com flags, dataMasterId(), pc, 50711147Smitch.hayenga@arm.com thread->contextId(), tid); 5085728Sgblack@eecs.umich.edu 50910024Sdam.sunwoo@arm.com req->taskId(taskId()); 51010024Sdam.sunwoo@arm.com 5117520Sgblack@eecs.umich.edu Addr split_addr = roundDown(addr + size - 1, block_size); 5125744Sgblack@eecs.umich.edu assert(split_addr <= addr || split_addr - addr < block_size); 5135728Sgblack@eecs.umich.edu 5145894Sgblack@eecs.umich.edu _status = DTBWaitResponse; 5155744Sgblack@eecs.umich.edu if (split_addr > addr) { 5165894Sgblack@eecs.umich.edu RequestPtr req1, req2; 5176102Sgblack@eecs.umich.edu assert(!req->isLLSC() && !req->isSwap()); 5185894Sgblack@eecs.umich.edu req->splitOnVaddr(split_addr, req1, req2); 5195894Sgblack@eecs.umich.edu 5206973Stjones1@inf.ed.ac.uk WholeTranslationState *state = 5218443Sgblack@eecs.umich.edu new WholeTranslationState(req, req1, req2, newData, res, mode); 5228486Sgblack@eecs.umich.edu DataTranslation<TimingSimpleCPU *> *trans1 = 5238486Sgblack@eecs.umich.edu new DataTranslation<TimingSimpleCPU *>(this, state, 0); 5248486Sgblack@eecs.umich.edu DataTranslation<TimingSimpleCPU *> *trans2 = 5258486Sgblack@eecs.umich.edu new DataTranslation<TimingSimpleCPU *>(this, state, 1); 5266973Stjones1@inf.ed.ac.uk 52711147Smitch.hayenga@arm.com thread->dtb->translateTiming(req1, thread->getTC(), trans1, mode); 52811147Smitch.hayenga@arm.com thread->dtb->translateTiming(req2, thread->getTC(), trans2, mode); 5295744Sgblack@eecs.umich.edu } else { 5306973Stjones1@inf.ed.ac.uk WholeTranslationState *state = 5318443Sgblack@eecs.umich.edu new WholeTranslationState(req, newData, res, mode); 5328486Sgblack@eecs.umich.edu DataTranslation<TimingSimpleCPU *> *translation = 5338486Sgblack@eecs.umich.edu new DataTranslation<TimingSimpleCPU *>(this, state); 53411147Smitch.hayenga@arm.com thread->dtb->translateTiming(req, thread->getTC(), translation, mode); 5352623SN/A } 5362623SN/A 5377045Ssteve.reinhardt@amd.com // Translation faults will be returned via finishTranslation() 5385728Sgblack@eecs.umich.edu return NoFault; 5392623SN/A} 5402623SN/A 5412623SN/A 5422623SN/Avoid 5436973Stjones1@inf.ed.ac.ukTimingSimpleCPU::finishTranslation(WholeTranslationState *state) 5446973Stjones1@inf.ed.ac.uk{ 5459342SAndreas.Sandberg@arm.com _status = BaseSimpleCPU::Running; 5466973Stjones1@inf.ed.ac.uk 5476973Stjones1@inf.ed.ac.uk if (state->getFault() != NoFault) { 5486973Stjones1@inf.ed.ac.uk if (state->isPrefetch()) { 5496973Stjones1@inf.ed.ac.uk state->setNoFault(); 5506973Stjones1@inf.ed.ac.uk } 5517691SAli.Saidi@ARM.com delete [] state->data; 5526973Stjones1@inf.ed.ac.uk state->deleteReqs(); 5536973Stjones1@inf.ed.ac.uk translationFault(state->getFault()); 5546973Stjones1@inf.ed.ac.uk } else { 5556973Stjones1@inf.ed.ac.uk if (!state->isSplit) { 5566973Stjones1@inf.ed.ac.uk sendData(state->mainReq, state->data, state->res, 5576973Stjones1@inf.ed.ac.uk state->mode == BaseTLB::Read); 5586973Stjones1@inf.ed.ac.uk } else { 5596973Stjones1@inf.ed.ac.uk sendSplitData(state->sreqLow, state->sreqHigh, state->mainReq, 5606973Stjones1@inf.ed.ac.uk state->data, state->mode == BaseTLB::Read); 5616973Stjones1@inf.ed.ac.uk } 5626973Stjones1@inf.ed.ac.uk } 5636973Stjones1@inf.ed.ac.uk 5646973Stjones1@inf.ed.ac.uk delete state; 5656973Stjones1@inf.ed.ac.uk} 5666973Stjones1@inf.ed.ac.uk 5676973Stjones1@inf.ed.ac.uk 5686973Stjones1@inf.ed.ac.ukvoid 5692623SN/ATimingSimpleCPU::fetch() 5702623SN/A{ 57111147Smitch.hayenga@arm.com // Change thread if multi-threaded 57211147Smitch.hayenga@arm.com swapActiveThread(); 57311147Smitch.hayenga@arm.com 57411147Smitch.hayenga@arm.com SimpleExecContext &t_info = *threadInfo[curThread]; 57511147Smitch.hayenga@arm.com SimpleThread* thread = t_info.thread; 57611147Smitch.hayenga@arm.com 5775221Ssaidi@eecs.umich.edu DPRINTF(SimpleCPU, "Fetch\n"); 5785221Ssaidi@eecs.umich.edu 57910596Sgabeblack@google.com if (!curStaticInst || !curStaticInst->isDelayedCommit()) { 5803387Sgblack@eecs.umich.edu checkForInterrupts(); 58110596Sgabeblack@google.com checkPcEventQueue(); 58210596Sgabeblack@google.com } 5835348Ssaidi@eecs.umich.edu 5848143SAli.Saidi@ARM.com // We must have just got suspended by a PC event 5858143SAli.Saidi@ARM.com if (_status == Idle) 5868143SAli.Saidi@ARM.com return; 5878143SAli.Saidi@ARM.com 5887720Sgblack@eecs.umich.edu TheISA::PCState pcState = thread->pcState(); 58911147Smitch.hayenga@arm.com bool needToFetch = !isRomMicroPC(pcState.microPC()) && 59011147Smitch.hayenga@arm.com !curMacroStaticInst; 5912623SN/A 5927720Sgblack@eecs.umich.edu if (needToFetch) { 5939342SAndreas.Sandberg@arm.com _status = BaseSimpleCPU::Running; 5945669Sgblack@eecs.umich.edu Request *ifetch_req = new Request(); 59510024Sdam.sunwoo@arm.com ifetch_req->taskId(taskId()); 59611147Smitch.hayenga@arm.com ifetch_req->setThreadContext(thread->contextId(), curThread); 5975894Sgblack@eecs.umich.edu setupFetchRequest(ifetch_req); 5988277SAli.Saidi@ARM.com DPRINTF(SimpleCPU, "Translating address %#x\n", ifetch_req->getVaddr()); 59911147Smitch.hayenga@arm.com thread->itb->translateTiming(ifetch_req, thread->getTC(), 60011147Smitch.hayenga@arm.com &fetchTranslation, BaseTLB::Execute); 6012623SN/A } else { 6025669Sgblack@eecs.umich.edu _status = IcacheWaitResponse; 6035669Sgblack@eecs.umich.edu completeIfetch(NULL); 6045894Sgblack@eecs.umich.edu 60510464SAndreas.Sandberg@ARM.com updateCycleCounts(); 6065894Sgblack@eecs.umich.edu } 6075894Sgblack@eecs.umich.edu} 6085894Sgblack@eecs.umich.edu 6095894Sgblack@eecs.umich.edu 6105894Sgblack@eecs.umich.eduvoid 61110379Sandreas.hansson@arm.comTimingSimpleCPU::sendFetch(const Fault &fault, RequestPtr req, 61210379Sandreas.hansson@arm.com ThreadContext *tc) 6135894Sgblack@eecs.umich.edu{ 6145894Sgblack@eecs.umich.edu if (fault == NoFault) { 6158277SAli.Saidi@ARM.com DPRINTF(SimpleCPU, "Sending fetch for addr %#x(pa: %#x)\n", 6168277SAli.Saidi@ARM.com req->getVaddr(), req->getPaddr()); 6178949Sandreas.hansson@arm.com ifetch_pkt = new Packet(req, MemCmd::ReadReq); 6185894Sgblack@eecs.umich.edu ifetch_pkt->dataStatic(&inst); 6198277SAli.Saidi@ARM.com DPRINTF(SimpleCPU, " -- pkt addr: %#x\n", ifetch_pkt->getAddr()); 6205894Sgblack@eecs.umich.edu 6218975Sandreas.hansson@arm.com if (!icachePort.sendTimingReq(ifetch_pkt)) { 6225894Sgblack@eecs.umich.edu // Need to wait for retry 6235894Sgblack@eecs.umich.edu _status = IcacheRetry; 6245894Sgblack@eecs.umich.edu } else { 6255894Sgblack@eecs.umich.edu // Need to wait for cache to respond 6265894Sgblack@eecs.umich.edu _status = IcacheWaitResponse; 6275894Sgblack@eecs.umich.edu // ownership of packet transferred to memory system 6285894Sgblack@eecs.umich.edu ifetch_pkt = NULL; 6295894Sgblack@eecs.umich.edu } 6305894Sgblack@eecs.umich.edu } else { 6318277SAli.Saidi@ARM.com DPRINTF(SimpleCPU, "Translation of addr %#x faulted\n", req->getVaddr()); 6325894Sgblack@eecs.umich.edu delete req; 6335894Sgblack@eecs.umich.edu // fetch fault: advance directly to next instruction (fault handler) 6349342SAndreas.Sandberg@arm.com _status = BaseSimpleCPU::Running; 6355894Sgblack@eecs.umich.edu advanceInst(fault); 6362623SN/A } 6373222Sktlim@umich.edu 63810464SAndreas.Sandberg@ARM.com updateCycleCounts(); 6392623SN/A} 6402623SN/A 6412623SN/A 6422623SN/Avoid 64310379Sandreas.hansson@arm.comTimingSimpleCPU::advanceInst(const Fault &fault) 6442623SN/A{ 64511147Smitch.hayenga@arm.com SimpleExecContext &t_info = *threadInfo[curThread]; 64611147Smitch.hayenga@arm.com 6478276SAli.Saidi@ARM.com if (_status == Faulting) 6488276SAli.Saidi@ARM.com return; 6498276SAli.Saidi@ARM.com 6508276SAli.Saidi@ARM.com if (fault != NoFault) { 6518276SAli.Saidi@ARM.com advancePC(fault); 6528276SAli.Saidi@ARM.com DPRINTF(SimpleCPU, "Fault occured, scheduling fetch event\n"); 6539648Sdam.sunwoo@arm.com reschedule(fetchEvent, clockEdge(), true); 6548276SAli.Saidi@ARM.com _status = Faulting; 6558276SAli.Saidi@ARM.com return; 6568276SAli.Saidi@ARM.com } 6578276SAli.Saidi@ARM.com 6588276SAli.Saidi@ARM.com 65911147Smitch.hayenga@arm.com if (!t_info.stayAtPC) 6605726Sgblack@eecs.umich.edu advancePC(fault); 6612623SN/A 6629442SAndreas.Sandberg@ARM.com if (tryCompleteDrain()) 6639442SAndreas.Sandberg@ARM.com return; 6649442SAndreas.Sandberg@ARM.com 6659342SAndreas.Sandberg@arm.com if (_status == BaseSimpleCPU::Running) { 6662631SN/A // kick off fetch of next instruction... callback from icache 6672631SN/A // response will cause that instruction to be executed, 6682631SN/A // keeping the CPU running. 6692631SN/A fetch(); 6702631SN/A } 6712623SN/A} 6722623SN/A 6732623SN/A 6742623SN/Avoid 6753349Sbinkertn@umich.eduTimingSimpleCPU::completeIfetch(PacketPtr pkt) 6762623SN/A{ 67711147Smitch.hayenga@arm.com SimpleExecContext& t_info = *threadInfo[curThread]; 67811147Smitch.hayenga@arm.com 6798277SAli.Saidi@ARM.com DPRINTF(SimpleCPU, "Complete ICache Fetch for addr %#x\n", pkt ? 6808277SAli.Saidi@ARM.com pkt->getAddr() : 0); 6818277SAli.Saidi@ARM.com 6822623SN/A // received a response from the icache: execute the received 6832623SN/A // instruction 6845669Sgblack@eecs.umich.edu assert(!pkt || !pkt->isError()); 6852623SN/A assert(_status == IcacheWaitResponse); 6862798Sktlim@umich.edu 6879342SAndreas.Sandberg@arm.com _status = BaseSimpleCPU::Running; 6882644Sstever@eecs.umich.edu 68910464SAndreas.Sandberg@ARM.com updateCycleCounts(); 6903222Sktlim@umich.edu 69110020Smatt.horsnell@ARM.com if (pkt) 69210020Smatt.horsnell@ARM.com pkt->req->setAccessLatency(); 69310020Smatt.horsnell@ARM.com 69410020Smatt.horsnell@ARM.com 6952623SN/A preExecute(); 6967725SAli.Saidi@ARM.com if (curStaticInst && curStaticInst->isMemRef()) { 6972623SN/A // load or store: just send to dcache 69811147Smitch.hayenga@arm.com Fault fault = curStaticInst->initiateAcc(&t_info, traceData); 6997945SAli.Saidi@ARM.com 7007945SAli.Saidi@ARM.com // If we're not running now the instruction will complete in a dcache 7017945SAli.Saidi@ARM.com // response callback or the instruction faulted and has started an 7027945SAli.Saidi@ARM.com // ifetch 7039342SAndreas.Sandberg@arm.com if (_status == BaseSimpleCPU::Running) { 7045894Sgblack@eecs.umich.edu if (fault != NoFault && traceData) { 7055001Sgblack@eecs.umich.edu // If there was a fault, we shouldn't trace this instruction. 7065001Sgblack@eecs.umich.edu delete traceData; 7075001Sgblack@eecs.umich.edu traceData = NULL; 7083170Sstever@eecs.umich.edu } 7094998Sgblack@eecs.umich.edu 7102644Sstever@eecs.umich.edu postExecute(); 7115103Ssaidi@eecs.umich.edu // @todo remove me after debugging with legion done 7125103Ssaidi@eecs.umich.edu if (curStaticInst && (!curStaticInst->isMicroop() || 7135103Ssaidi@eecs.umich.edu curStaticInst->isFirstMicroop())) 7145103Ssaidi@eecs.umich.edu instCnt++; 7152644Sstever@eecs.umich.edu advanceInst(fault); 7162644Sstever@eecs.umich.edu } 7175726Sgblack@eecs.umich.edu } else if (curStaticInst) { 7182623SN/A // non-memory instruction: execute completely now 71911147Smitch.hayenga@arm.com Fault fault = curStaticInst->execute(&t_info, traceData); 7204998Sgblack@eecs.umich.edu 7214998Sgblack@eecs.umich.edu // keep an instruction count 7224998Sgblack@eecs.umich.edu if (fault == NoFault) 7234998Sgblack@eecs.umich.edu countInst(); 7247655Sali.saidi@arm.com else if (traceData && !DTRACE(ExecFaulting)) { 7255001Sgblack@eecs.umich.edu delete traceData; 7265001Sgblack@eecs.umich.edu traceData = NULL; 7275001Sgblack@eecs.umich.edu } 7284998Sgblack@eecs.umich.edu 7292644Sstever@eecs.umich.edu postExecute(); 7305103Ssaidi@eecs.umich.edu // @todo remove me after debugging with legion done 7315103Ssaidi@eecs.umich.edu if (curStaticInst && (!curStaticInst->isMicroop() || 73211147Smitch.hayenga@arm.com curStaticInst->isFirstMicroop())) 7335103Ssaidi@eecs.umich.edu instCnt++; 7342644Sstever@eecs.umich.edu advanceInst(fault); 7355726Sgblack@eecs.umich.edu } else { 7365726Sgblack@eecs.umich.edu advanceInst(NoFault); 7372623SN/A } 7383658Sktlim@umich.edu 7395669Sgblack@eecs.umich.edu if (pkt) { 7405669Sgblack@eecs.umich.edu delete pkt->req; 7415669Sgblack@eecs.umich.edu delete pkt; 7425669Sgblack@eecs.umich.edu } 7432623SN/A} 7442623SN/A 7452948Ssaidi@eecs.umich.eduvoid 7462948Ssaidi@eecs.umich.eduTimingSimpleCPU::IcachePort::ITickEvent::process() 7472948Ssaidi@eecs.umich.edu{ 7482948Ssaidi@eecs.umich.edu cpu->completeIfetch(pkt); 7492948Ssaidi@eecs.umich.edu} 7502623SN/A 7512623SN/Abool 7528975Sandreas.hansson@arm.comTimingSimpleCPU::IcachePort::recvTimingResp(PacketPtr pkt) 7532623SN/A{ 75410669Sandreas.hansson@arm.com DPRINTF(SimpleCPU, "Received fetch response %#x\n", pkt->getAddr()); 75510669Sandreas.hansson@arm.com // we should only ever see one response per cycle since we only 75610669Sandreas.hansson@arm.com // issue a new request once this response is sunk 75710669Sandreas.hansson@arm.com assert(!tickEvent.scheduled()); 7589165Sandreas.hansson@arm.com // delay processing of returned data until next CPU clock edge 75910669Sandreas.hansson@arm.com tickEvent.schedule(pkt, cpu->clockEdge()); 7608948Sandreas.hansson@arm.com 7614433Ssaidi@eecs.umich.edu return true; 7622623SN/A} 7632623SN/A 7642657Ssaidi@eecs.umich.eduvoid 76510713Sandreas.hansson@arm.comTimingSimpleCPU::IcachePort::recvReqRetry() 7662623SN/A{ 7672623SN/A // we shouldn't get a retry unless we have a packet that we're 7682623SN/A // waiting to transmit 7692623SN/A assert(cpu->ifetch_pkt != NULL); 7702623SN/A assert(cpu->_status == IcacheRetry); 7713349Sbinkertn@umich.edu PacketPtr tmp = cpu->ifetch_pkt; 7728975Sandreas.hansson@arm.com if (sendTimingReq(tmp)) { 7732657Ssaidi@eecs.umich.edu cpu->_status = IcacheWaitResponse; 7742657Ssaidi@eecs.umich.edu cpu->ifetch_pkt = NULL; 7752657Ssaidi@eecs.umich.edu } 7762623SN/A} 7772623SN/A 7782623SN/Avoid 7793349Sbinkertn@umich.eduTimingSimpleCPU::completeDataAccess(PacketPtr pkt) 7802623SN/A{ 7812623SN/A // received a response from the dcache: complete the load or store 7822623SN/A // instruction 7834870Sstever@eecs.umich.edu assert(!pkt->isError()); 7847516Shestness@cs.utexas.edu assert(_status == DcacheWaitResponse || _status == DTBWaitResponse || 7857516Shestness@cs.utexas.edu pkt->req->getFlags().isSet(Request::NO_ACCESS)); 7862623SN/A 78710020Smatt.horsnell@ARM.com pkt->req->setAccessLatency(); 78810464SAndreas.Sandberg@ARM.com 78910464SAndreas.Sandberg@ARM.com updateCycleCounts(); 7903184Srdreslin@umich.edu 7915728Sgblack@eecs.umich.edu if (pkt->senderState) { 7925728Sgblack@eecs.umich.edu SplitFragmentSenderState * send_state = 7935728Sgblack@eecs.umich.edu dynamic_cast<SplitFragmentSenderState *>(pkt->senderState); 7945728Sgblack@eecs.umich.edu assert(send_state); 7955728Sgblack@eecs.umich.edu delete pkt->req; 7965728Sgblack@eecs.umich.edu delete pkt; 7975728Sgblack@eecs.umich.edu PacketPtr big_pkt = send_state->bigPkt; 7985728Sgblack@eecs.umich.edu delete send_state; 7995728Sgblack@eecs.umich.edu 8005728Sgblack@eecs.umich.edu SplitMainSenderState * main_send_state = 8015728Sgblack@eecs.umich.edu dynamic_cast<SplitMainSenderState *>(big_pkt->senderState); 8025728Sgblack@eecs.umich.edu assert(main_send_state); 8035728Sgblack@eecs.umich.edu // Record the fact that this packet is no longer outstanding. 8045728Sgblack@eecs.umich.edu assert(main_send_state->outstanding != 0); 8055728Sgblack@eecs.umich.edu main_send_state->outstanding--; 8065728Sgblack@eecs.umich.edu 8075728Sgblack@eecs.umich.edu if (main_send_state->outstanding) { 8085728Sgblack@eecs.umich.edu return; 8095728Sgblack@eecs.umich.edu } else { 8105728Sgblack@eecs.umich.edu delete main_send_state; 8115728Sgblack@eecs.umich.edu big_pkt->senderState = NULL; 8125728Sgblack@eecs.umich.edu pkt = big_pkt; 8135728Sgblack@eecs.umich.edu } 8145728Sgblack@eecs.umich.edu } 8155728Sgblack@eecs.umich.edu 8169342SAndreas.Sandberg@arm.com _status = BaseSimpleCPU::Running; 8175728Sgblack@eecs.umich.edu 81811147Smitch.hayenga@arm.com Fault fault = curStaticInst->completeAcc(pkt, threadInfo[curThread], 81911147Smitch.hayenga@arm.com traceData); 8202623SN/A 8214998Sgblack@eecs.umich.edu // keep an instruction count 8224998Sgblack@eecs.umich.edu if (fault == NoFault) 8234998Sgblack@eecs.umich.edu countInst(); 8245001Sgblack@eecs.umich.edu else if (traceData) { 8255001Sgblack@eecs.umich.edu // If there was a fault, we shouldn't trace this instruction. 8265001Sgblack@eecs.umich.edu delete traceData; 8275001Sgblack@eecs.umich.edu traceData = NULL; 8285001Sgblack@eecs.umich.edu } 8294998Sgblack@eecs.umich.edu 8302644Sstever@eecs.umich.edu delete pkt->req; 8312644Sstever@eecs.umich.edu delete pkt; 8322644Sstever@eecs.umich.edu 8333184Srdreslin@umich.edu postExecute(); 8343227Sktlim@umich.edu 8352644Sstever@eecs.umich.edu advanceInst(fault); 8362623SN/A} 8372623SN/A 83810030SAli.Saidi@ARM.comvoid 83910464SAndreas.Sandberg@ARM.comTimingSimpleCPU::updateCycleCounts() 84010464SAndreas.Sandberg@ARM.com{ 84110464SAndreas.Sandberg@ARM.com const Cycles delta(curCycle() - previousCycle); 84210464SAndreas.Sandberg@ARM.com 84310464SAndreas.Sandberg@ARM.com numCycles += delta; 84410464SAndreas.Sandberg@ARM.com ppCycles->notify(delta); 84510464SAndreas.Sandberg@ARM.com 84610464SAndreas.Sandberg@ARM.com previousCycle = curCycle(); 84710464SAndreas.Sandberg@ARM.com} 84810464SAndreas.Sandberg@ARM.com 84910464SAndreas.Sandberg@ARM.comvoid 85010030SAli.Saidi@ARM.comTimingSimpleCPU::DcachePort::recvTimingSnoopReq(PacketPtr pkt) 85110030SAli.Saidi@ARM.com{ 85210529Smorr@cs.wisc.edu // X86 ISA: Snooping an invalidation for monitor/mwait 85311147Smitch.hayenga@arm.com if(cpu->getCpuAddrMonitor()->doMonitor(pkt)) { 85410529Smorr@cs.wisc.edu cpu->wakeup(); 85510529Smorr@cs.wisc.edu } 85611147Smitch.hayenga@arm.com 85711147Smitch.hayenga@arm.com for (auto &t_info : cpu->threadInfo) { 85811147Smitch.hayenga@arm.com TheISA::handleLockedSnoop(t_info->thread, pkt, cacheBlockMask); 85911147Smitch.hayenga@arm.com } 86010030SAli.Saidi@ARM.com} 86110030SAli.Saidi@ARM.com 86210529Smorr@cs.wisc.eduvoid 86310529Smorr@cs.wisc.eduTimingSimpleCPU::DcachePort::recvFunctionalSnoop(PacketPtr pkt) 86410529Smorr@cs.wisc.edu{ 86510529Smorr@cs.wisc.edu // X86 ISA: Snooping an invalidation for monitor/mwait 86611147Smitch.hayenga@arm.com if(cpu->getCpuAddrMonitor()->doMonitor(pkt)) { 86710529Smorr@cs.wisc.edu cpu->wakeup(); 86810529Smorr@cs.wisc.edu } 86910529Smorr@cs.wisc.edu} 87010030SAli.Saidi@ARM.com 8712623SN/Abool 8728975Sandreas.hansson@arm.comTimingSimpleCPU::DcachePort::recvTimingResp(PacketPtr pkt) 8732623SN/A{ 87410669Sandreas.hansson@arm.com DPRINTF(SimpleCPU, "Received load/store response %#x\n", pkt->getAddr()); 8752948Ssaidi@eecs.umich.edu 87610669Sandreas.hansson@arm.com // The timing CPU is not really ticked, instead it relies on the 87710669Sandreas.hansson@arm.com // memory system (fetch and load/store) to set the pace. 87810669Sandreas.hansson@arm.com if (!tickEvent.scheduled()) { 87910669Sandreas.hansson@arm.com // Delay processing of returned data until next CPU clock edge 88010669Sandreas.hansson@arm.com tickEvent.schedule(pkt, cpu->clockEdge()); 88110669Sandreas.hansson@arm.com return true; 8829165Sandreas.hansson@arm.com } else { 88310669Sandreas.hansson@arm.com // In the case of a split transaction and a cache that is 88410669Sandreas.hansson@arm.com // faster than a CPU we could get two responses in the 88510669Sandreas.hansson@arm.com // same tick, delay the second one 88610713Sandreas.hansson@arm.com if (!retryRespEvent.scheduled()) 88710713Sandreas.hansson@arm.com cpu->schedule(retryRespEvent, cpu->clockEdge(Cycles(1))); 88810669Sandreas.hansson@arm.com return false; 8893310Srdreslin@umich.edu } 8902948Ssaidi@eecs.umich.edu} 8912948Ssaidi@eecs.umich.edu 8922948Ssaidi@eecs.umich.eduvoid 8932948Ssaidi@eecs.umich.eduTimingSimpleCPU::DcachePort::DTickEvent::process() 8942948Ssaidi@eecs.umich.edu{ 8952630SN/A cpu->completeDataAccess(pkt); 8962623SN/A} 8972623SN/A 8982657Ssaidi@eecs.umich.eduvoid 89910713Sandreas.hansson@arm.comTimingSimpleCPU::DcachePort::recvReqRetry() 9002623SN/A{ 9012623SN/A // we shouldn't get a retry unless we have a packet that we're 9022623SN/A // waiting to transmit 9032623SN/A assert(cpu->dcache_pkt != NULL); 9042623SN/A assert(cpu->_status == DcacheRetry); 9053349Sbinkertn@umich.edu PacketPtr tmp = cpu->dcache_pkt; 9065728Sgblack@eecs.umich.edu if (tmp->senderState) { 9075728Sgblack@eecs.umich.edu // This is a packet from a split access. 9085728Sgblack@eecs.umich.edu SplitFragmentSenderState * send_state = 9095728Sgblack@eecs.umich.edu dynamic_cast<SplitFragmentSenderState *>(tmp->senderState); 9105728Sgblack@eecs.umich.edu assert(send_state); 9115728Sgblack@eecs.umich.edu PacketPtr big_pkt = send_state->bigPkt; 9125728Sgblack@eecs.umich.edu 9135728Sgblack@eecs.umich.edu SplitMainSenderState * main_send_state = 9145728Sgblack@eecs.umich.edu dynamic_cast<SplitMainSenderState *>(big_pkt->senderState); 9155728Sgblack@eecs.umich.edu assert(main_send_state); 9165728Sgblack@eecs.umich.edu 9178975Sandreas.hansson@arm.com if (sendTimingReq(tmp)) { 9185728Sgblack@eecs.umich.edu // If we were able to send without retrying, record that fact 9195728Sgblack@eecs.umich.edu // and try sending the other fragment. 9205728Sgblack@eecs.umich.edu send_state->clearFromParent(); 9215728Sgblack@eecs.umich.edu int other_index = main_send_state->getPendingFragment(); 9225728Sgblack@eecs.umich.edu if (other_index > 0) { 9235728Sgblack@eecs.umich.edu tmp = main_send_state->fragments[other_index]; 9245728Sgblack@eecs.umich.edu cpu->dcache_pkt = tmp; 9255728Sgblack@eecs.umich.edu if ((big_pkt->isRead() && cpu->handleReadPacket(tmp)) || 9265728Sgblack@eecs.umich.edu (big_pkt->isWrite() && cpu->handleWritePacket())) { 9275728Sgblack@eecs.umich.edu main_send_state->fragments[other_index] = NULL; 9285728Sgblack@eecs.umich.edu } 9295728Sgblack@eecs.umich.edu } else { 9305728Sgblack@eecs.umich.edu cpu->_status = DcacheWaitResponse; 9315728Sgblack@eecs.umich.edu // memory system takes ownership of packet 9325728Sgblack@eecs.umich.edu cpu->dcache_pkt = NULL; 9335728Sgblack@eecs.umich.edu } 9345728Sgblack@eecs.umich.edu } 9358975Sandreas.hansson@arm.com } else if (sendTimingReq(tmp)) { 9362657Ssaidi@eecs.umich.edu cpu->_status = DcacheWaitResponse; 9373170Sstever@eecs.umich.edu // memory system takes ownership of packet 9382657Ssaidi@eecs.umich.edu cpu->dcache_pkt = NULL; 9392657Ssaidi@eecs.umich.edu } 9402623SN/A} 9412623SN/A 9425606Snate@binkert.orgTimingSimpleCPU::IprEvent::IprEvent(Packet *_pkt, TimingSimpleCPU *_cpu, 9435606Snate@binkert.org Tick t) 9445606Snate@binkert.org : pkt(_pkt), cpu(_cpu) 9455103Ssaidi@eecs.umich.edu{ 9465606Snate@binkert.org cpu->schedule(this, t); 9475103Ssaidi@eecs.umich.edu} 9485103Ssaidi@eecs.umich.edu 9495103Ssaidi@eecs.umich.eduvoid 9505103Ssaidi@eecs.umich.eduTimingSimpleCPU::IprEvent::process() 9515103Ssaidi@eecs.umich.edu{ 9525103Ssaidi@eecs.umich.edu cpu->completeDataAccess(pkt); 9535103Ssaidi@eecs.umich.edu} 9545103Ssaidi@eecs.umich.edu 9555103Ssaidi@eecs.umich.educonst char * 9565336Shines@cs.fsu.eduTimingSimpleCPU::IprEvent::description() const 9575103Ssaidi@eecs.umich.edu{ 9585103Ssaidi@eecs.umich.edu return "Timing Simple CPU Delay IPR event"; 9595103Ssaidi@eecs.umich.edu} 9605103Ssaidi@eecs.umich.edu 9612623SN/A 9625315Sstever@gmail.comvoid 9635315Sstever@gmail.comTimingSimpleCPU::printAddr(Addr a) 9645315Sstever@gmail.com{ 9655315Sstever@gmail.com dcachePort.printAddr(a); 9665315Sstever@gmail.com} 9675315Sstever@gmail.com 9685315Sstever@gmail.com 9692623SN/A//////////////////////////////////////////////////////////////////////// 9702623SN/A// 9712623SN/A// TimingSimpleCPU Simulation Object 9722623SN/A// 9734762Snate@binkert.orgTimingSimpleCPU * 9744762Snate@binkert.orgTimingSimpleCPUParams::create() 9752623SN/A{ 9765529Snate@binkert.org return new TimingSimpleCPU(this); 9772623SN/A} 978