timing.cc revision 10913
12623SN/A/* 210596Sgabeblack@google.com * Copyright 2014 Google, Inc. 310030SAli.Saidi@ARM.com * Copyright (c) 2010-2013 ARM Limited 47725SAli.Saidi@ARM.com * All rights reserved 57725SAli.Saidi@ARM.com * 67725SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall 77725SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 87725SAli.Saidi@ARM.com * property including but not limited to intellectual property relating 97725SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software 107725SAli.Saidi@ARM.com * licensed hereunder. You may use the software subject to the license 117725SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated 127725SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software, 137725SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form. 147725SAli.Saidi@ARM.com * 152623SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 162623SN/A * All rights reserved. 172623SN/A * 182623SN/A * Redistribution and use in source and binary forms, with or without 192623SN/A * modification, are permitted provided that the following conditions are 202623SN/A * met: redistributions of source code must retain the above copyright 212623SN/A * notice, this list of conditions and the following disclaimer; 222623SN/A * redistributions in binary form must reproduce the above copyright 232623SN/A * notice, this list of conditions and the following disclaimer in the 242623SN/A * documentation and/or other materials provided with the distribution; 252623SN/A * neither the name of the copyright holders nor the names of its 262623SN/A * contributors may be used to endorse or promote products derived from 272623SN/A * this software without specific prior written permission. 282623SN/A * 292623SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 302623SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 312623SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 322623SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 332623SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 342623SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 352623SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 362623SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 372623SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 382623SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 392623SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402665Ssaidi@eecs.umich.edu * 412665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 422623SN/A */ 432623SN/A 443170Sstever@eecs.umich.edu#include "arch/locked_mem.hh" 458105Sgblack@eecs.umich.edu#include "arch/mmapped_ipr.hh" 462623SN/A#include "arch/utility.hh" 474040Ssaidi@eecs.umich.edu#include "base/bigint.hh" 486658Snate@binkert.org#include "config/the_isa.hh" 498229Snate@binkert.org#include "cpu/simple/timing.hh" 502623SN/A#include "cpu/exetrace.hh" 518232Snate@binkert.org#include "debug/Config.hh" 529152Satgutier@umich.edu#include "debug/Drain.hh" 538232Snate@binkert.org#include "debug/ExecFaulting.hh" 548232Snate@binkert.org#include "debug/SimpleCPU.hh" 553348Sbinkertn@umich.edu#include "mem/packet.hh" 563348Sbinkertn@umich.edu#include "mem/packet_access.hh" 574762Snate@binkert.org#include "params/TimingSimpleCPU.hh" 587678Sgblack@eecs.umich.edu#include "sim/faults.hh" 598779Sgblack@eecs.umich.edu#include "sim/full_system.hh" 602901Ssaidi@eecs.umich.edu#include "sim/system.hh" 612623SN/A 6210529Smorr@cs.wisc.edu#include "debug/Mwait.hh" 6310529Smorr@cs.wisc.edu 642623SN/Ausing namespace std; 652623SN/Ausing namespace TheISA; 662623SN/A 672623SN/Avoid 682623SN/ATimingSimpleCPU::init() 692623SN/A{ 702623SN/A BaseCPU::init(); 718921Sandreas.hansson@arm.com 728921Sandreas.hansson@arm.com // Initialise the ThreadContext's memory proxies 738921Sandreas.hansson@arm.com tcBase()->initMemProxies(tcBase()); 748921Sandreas.hansson@arm.com 759433SAndreas.Sandberg@ARM.com if (FullSystem && !params()->switched_out) { 768779Sgblack@eecs.umich.edu for (int i = 0; i < threadContexts.size(); ++i) { 778779Sgblack@eecs.umich.edu ThreadContext *tc = threadContexts[i]; 788779Sgblack@eecs.umich.edu // initialize CPU, including PC 798779Sgblack@eecs.umich.edu TheISA::initCPU(tc, _cpuId); 808779Sgblack@eecs.umich.edu } 812623SN/A } 822623SN/A} 832623SN/A 842623SN/Avoid 858707Sandreas.hansson@arm.comTimingSimpleCPU::TimingCPUPort::TickEvent::schedule(PacketPtr _pkt, Tick t) 862948Ssaidi@eecs.umich.edu{ 872948Ssaidi@eecs.umich.edu pkt = _pkt; 885606Snate@binkert.org cpu->schedule(this, t); 892948Ssaidi@eecs.umich.edu} 902948Ssaidi@eecs.umich.edu 915529Snate@binkert.orgTimingSimpleCPU::TimingSimpleCPU(TimingSimpleCPUParams *p) 928707Sandreas.hansson@arm.com : BaseSimpleCPU(p), fetchTranslation(this), icachePort(this), 939179Sandreas.hansson@arm.com dcachePort(this), ifetch_pkt(NULL), dcache_pkt(NULL), previousCycle(0), 9410913Sandreas.sandberg@arm.com fetchEvent(this) 952623SN/A{ 962623SN/A _status = Idle; 972623SN/A} 982623SN/A 992623SN/A 10010030SAli.Saidi@ARM.com 1012623SN/ATimingSimpleCPU::~TimingSimpleCPU() 1022623SN/A{ 1032623SN/A} 1042623SN/A 10510913Sandreas.sandberg@arm.comDrainState 10610913Sandreas.sandberg@arm.comTimingSimpleCPU::drain() 1072798Sktlim@umich.edu{ 1089448SAndreas.Sandberg@ARM.com if (switchedOut()) 10910913Sandreas.sandberg@arm.com return DrainState::Drained; 1109448SAndreas.Sandberg@ARM.com 1119342SAndreas.Sandberg@arm.com if (_status == Idle || 1129448SAndreas.Sandberg@ARM.com (_status == BaseSimpleCPU::Running && isDrained())) { 1139442SAndreas.Sandberg@ARM.com DPRINTF(Drain, "No need to drain.\n"); 11410913Sandreas.sandberg@arm.com return DrainState::Drained; 1152798Sktlim@umich.edu } else { 1169442SAndreas.Sandberg@ARM.com DPRINTF(Drain, "Requesting drain: %s\n", pcState()); 1179442SAndreas.Sandberg@ARM.com 1189442SAndreas.Sandberg@ARM.com // The fetch event can become descheduled if a drain didn't 1199442SAndreas.Sandberg@ARM.com // succeed on the first attempt. We need to reschedule it if 1209442SAndreas.Sandberg@ARM.com // the CPU is waiting for a microcode routine to complete. 1219448SAndreas.Sandberg@ARM.com if (_status == BaseSimpleCPU::Running && !fetchEvent.scheduled()) 1229648Sdam.sunwoo@arm.com schedule(fetchEvent, clockEdge()); 1239442SAndreas.Sandberg@ARM.com 12410913Sandreas.sandberg@arm.com return DrainState::Draining; 1252798Sktlim@umich.edu } 1262623SN/A} 1272623SN/A 1282623SN/Avoid 1299342SAndreas.Sandberg@arm.comTimingSimpleCPU::drainResume() 1302623SN/A{ 1319442SAndreas.Sandberg@ARM.com assert(!fetchEvent.scheduled()); 1329448SAndreas.Sandberg@ARM.com if (switchedOut()) 1339448SAndreas.Sandberg@ARM.com return; 1349442SAndreas.Sandberg@ARM.com 1355221Ssaidi@eecs.umich.edu DPRINTF(SimpleCPU, "Resume\n"); 1369523SAndreas.Sandberg@ARM.com verifyMemoryMode(); 1373201Shsul@eecs.umich.edu 1389448SAndreas.Sandberg@ARM.com assert(!threadContexts.empty()); 1399448SAndreas.Sandberg@ARM.com if (threadContexts.size() > 1) 1409448SAndreas.Sandberg@ARM.com fatal("The timing CPU only supports one thread.\n"); 1419448SAndreas.Sandberg@ARM.com 1429448SAndreas.Sandberg@ARM.com if (thread->status() == ThreadContext::Active) { 1435710Scws3k@cs.virginia.edu schedule(fetchEvent, nextCycle()); 1449448SAndreas.Sandberg@ARM.com _status = BaseSimpleCPU::Running; 1459837Slena@cs.wisc,edu notIdleFraction = 1; 1469448SAndreas.Sandberg@ARM.com } else { 1479448SAndreas.Sandberg@ARM.com _status = BaseSimpleCPU::Idle; 1489837Slena@cs.wisc,edu notIdleFraction = 0; 1492623SN/A } 1509442SAndreas.Sandberg@ARM.com} 1512798Sktlim@umich.edu 1529442SAndreas.Sandberg@ARM.combool 1539442SAndreas.Sandberg@ARM.comTimingSimpleCPU::tryCompleteDrain() 1549442SAndreas.Sandberg@ARM.com{ 15510913Sandreas.sandberg@arm.com if (drainState() != DrainState::Draining) 1569442SAndreas.Sandberg@ARM.com return false; 1579442SAndreas.Sandberg@ARM.com 1589442SAndreas.Sandberg@ARM.com DPRINTF(Drain, "tryCompleteDrain: %s\n", pcState()); 1599442SAndreas.Sandberg@ARM.com if (!isDrained()) 1609442SAndreas.Sandberg@ARM.com return false; 1619442SAndreas.Sandberg@ARM.com 1629442SAndreas.Sandberg@ARM.com DPRINTF(Drain, "CPU done draining, processing drain event\n"); 16310913Sandreas.sandberg@arm.com signalDrainDone(); 1649442SAndreas.Sandberg@ARM.com 1659442SAndreas.Sandberg@ARM.com return true; 1662798Sktlim@umich.edu} 1672798Sktlim@umich.edu 1682798Sktlim@umich.eduvoid 1692798Sktlim@umich.eduTimingSimpleCPU::switchOut() 1702798Sktlim@umich.edu{ 1719429SAndreas.Sandberg@ARM.com BaseSimpleCPU::switchOut(); 1729429SAndreas.Sandberg@ARM.com 1739442SAndreas.Sandberg@ARM.com assert(!fetchEvent.scheduled()); 1749342SAndreas.Sandberg@arm.com assert(_status == BaseSimpleCPU::Running || _status == Idle); 1759442SAndreas.Sandberg@ARM.com assert(!stayAtPC); 1769442SAndreas.Sandberg@ARM.com assert(microPC() == 0); 1779442SAndreas.Sandberg@ARM.com 17810464SAndreas.Sandberg@ARM.com updateCycleCounts(); 1792623SN/A} 1802623SN/A 1812623SN/A 1822623SN/Avoid 1832623SN/ATimingSimpleCPU::takeOverFrom(BaseCPU *oldCPU) 1842623SN/A{ 1859429SAndreas.Sandberg@ARM.com BaseSimpleCPU::takeOverFrom(oldCPU); 1862623SN/A 1879179Sandreas.hansson@arm.com previousCycle = curCycle(); 1882623SN/A} 1892623SN/A 1909523SAndreas.Sandberg@ARM.comvoid 1919523SAndreas.Sandberg@ARM.comTimingSimpleCPU::verifyMemoryMode() const 1929523SAndreas.Sandberg@ARM.com{ 1939524SAndreas.Sandberg@ARM.com if (!system->isTimingMode()) { 1949523SAndreas.Sandberg@ARM.com fatal("The timing CPU requires the memory system to be in " 1959523SAndreas.Sandberg@ARM.com "'timing' mode.\n"); 1969523SAndreas.Sandberg@ARM.com } 1979523SAndreas.Sandberg@ARM.com} 1982623SN/A 1992623SN/Avoid 20010407Smitch.hayenga@arm.comTimingSimpleCPU::activateContext(ThreadID thread_num) 2012623SN/A{ 20210407Smitch.hayenga@arm.com DPRINTF(SimpleCPU, "ActivateContext %d\n", thread_num); 2035221Ssaidi@eecs.umich.edu 2042623SN/A assert(thread_num == 0); 2052683Sktlim@umich.edu assert(thread); 2062623SN/A 2072623SN/A assert(_status == Idle); 2082623SN/A 2099837Slena@cs.wisc,edu notIdleFraction = 1; 2109342SAndreas.Sandberg@arm.com _status = BaseSimpleCPU::Running; 2113686Sktlim@umich.edu 2122623SN/A // kick things off by initiating the fetch of the next instruction 21310407Smitch.hayenga@arm.com schedule(fetchEvent, clockEdge(Cycles(0))); 2142623SN/A} 2152623SN/A 2162623SN/A 2172623SN/Avoid 2188737Skoansin.tan@gmail.comTimingSimpleCPU::suspendContext(ThreadID thread_num) 2192623SN/A{ 2205221Ssaidi@eecs.umich.edu DPRINTF(SimpleCPU, "SuspendContext %d\n", thread_num); 2215221Ssaidi@eecs.umich.edu 2222623SN/A assert(thread_num == 0); 2232683Sktlim@umich.edu assert(thread); 2242623SN/A 2256043Sgblack@eecs.umich.edu if (_status == Idle) 2266043Sgblack@eecs.umich.edu return; 2276043Sgblack@eecs.umich.edu 2289342SAndreas.Sandberg@arm.com assert(_status == BaseSimpleCPU::Running); 2292623SN/A 2302644Sstever@eecs.umich.edu // just change status to Idle... if status != Running, 2312644Sstever@eecs.umich.edu // completeInst() will not initiate fetch of next instruction. 2322623SN/A 2339837Slena@cs.wisc,edu notIdleFraction = 0; 2342623SN/A _status = Idle; 2352623SN/A} 2362623SN/A 2375728Sgblack@eecs.umich.edubool 2385728Sgblack@eecs.umich.eduTimingSimpleCPU::handleReadPacket(PacketPtr pkt) 2395728Sgblack@eecs.umich.edu{ 2405728Sgblack@eecs.umich.edu RequestPtr req = pkt->req; 24110533Sali.saidi@arm.com 24210533Sali.saidi@arm.com // We're about the issues a locked load, so tell the monitor 24310533Sali.saidi@arm.com // to start caring about this address 24410533Sali.saidi@arm.com if (pkt->isRead() && pkt->req->isLLSC()) { 24510533Sali.saidi@arm.com TheISA::handleLockedRead(thread, pkt->req); 24610533Sali.saidi@arm.com } 2478105Sgblack@eecs.umich.edu if (req->isMmappedIpr()) { 2489180Sandreas.hansson@arm.com Cycles delay = TheISA::handleIprRead(thread->getTC(), pkt); 2499179Sandreas.hansson@arm.com new IprEvent(pkt, this, clockEdge(delay)); 2505728Sgblack@eecs.umich.edu _status = DcacheWaitResponse; 2515728Sgblack@eecs.umich.edu dcache_pkt = NULL; 2528975Sandreas.hansson@arm.com } else if (!dcachePort.sendTimingReq(pkt)) { 2535728Sgblack@eecs.umich.edu _status = DcacheRetry; 2545728Sgblack@eecs.umich.edu dcache_pkt = pkt; 2555728Sgblack@eecs.umich.edu } else { 2565728Sgblack@eecs.umich.edu _status = DcacheWaitResponse; 2575728Sgblack@eecs.umich.edu // memory system takes ownership of packet 2585728Sgblack@eecs.umich.edu dcache_pkt = NULL; 2595728Sgblack@eecs.umich.edu } 2605728Sgblack@eecs.umich.edu return dcache_pkt == NULL; 2615728Sgblack@eecs.umich.edu} 2622623SN/A 2635894Sgblack@eecs.umich.eduvoid 2646973Stjones1@inf.ed.ac.ukTimingSimpleCPU::sendData(RequestPtr req, uint8_t *data, uint64_t *res, 2656973Stjones1@inf.ed.ac.uk bool read) 2665744Sgblack@eecs.umich.edu{ 26710653Sandreas.hansson@arm.com PacketPtr pkt = buildPacket(req, read); 26810566Sandreas.hansson@arm.com pkt->dataDynamic<uint8_t>(data); 2695894Sgblack@eecs.umich.edu if (req->getFlags().isSet(Request::NO_ACCESS)) { 2705894Sgblack@eecs.umich.edu assert(!dcache_pkt); 2715894Sgblack@eecs.umich.edu pkt->makeResponse(); 2725894Sgblack@eecs.umich.edu completeDataAccess(pkt); 2735894Sgblack@eecs.umich.edu } else if (read) { 2745894Sgblack@eecs.umich.edu handleReadPacket(pkt); 2755894Sgblack@eecs.umich.edu } else { 2765894Sgblack@eecs.umich.edu bool do_access = true; // flag to suppress cache access 2775894Sgblack@eecs.umich.edu 2786102Sgblack@eecs.umich.edu if (req->isLLSC()) { 27910030SAli.Saidi@ARM.com do_access = TheISA::handleLockedWrite(thread, req, dcachePort.cacheBlockMask); 2805894Sgblack@eecs.umich.edu } else if (req->isCondSwap()) { 2815894Sgblack@eecs.umich.edu assert(res); 2825894Sgblack@eecs.umich.edu req->setExtraData(*res); 2835894Sgblack@eecs.umich.edu } 2845894Sgblack@eecs.umich.edu 2855894Sgblack@eecs.umich.edu if (do_access) { 2865894Sgblack@eecs.umich.edu dcache_pkt = pkt; 2875894Sgblack@eecs.umich.edu handleWritePacket(); 2885894Sgblack@eecs.umich.edu } else { 2895894Sgblack@eecs.umich.edu _status = DcacheWaitResponse; 2905894Sgblack@eecs.umich.edu completeDataAccess(pkt); 2915894Sgblack@eecs.umich.edu } 2925894Sgblack@eecs.umich.edu } 2935894Sgblack@eecs.umich.edu} 2945894Sgblack@eecs.umich.edu 2955894Sgblack@eecs.umich.eduvoid 2966973Stjones1@inf.ed.ac.ukTimingSimpleCPU::sendSplitData(RequestPtr req1, RequestPtr req2, 2976973Stjones1@inf.ed.ac.uk RequestPtr req, uint8_t *data, bool read) 2985894Sgblack@eecs.umich.edu{ 2995894Sgblack@eecs.umich.edu PacketPtr pkt1, pkt2; 3005894Sgblack@eecs.umich.edu buildSplitPacket(pkt1, pkt2, req1, req2, req, data, read); 3015894Sgblack@eecs.umich.edu if (req->getFlags().isSet(Request::NO_ACCESS)) { 3025894Sgblack@eecs.umich.edu assert(!dcache_pkt); 3035894Sgblack@eecs.umich.edu pkt1->makeResponse(); 3045894Sgblack@eecs.umich.edu completeDataAccess(pkt1); 3055894Sgblack@eecs.umich.edu } else if (read) { 3067911Shestness@cs.utexas.edu SplitFragmentSenderState * send_state = 3077911Shestness@cs.utexas.edu dynamic_cast<SplitFragmentSenderState *>(pkt1->senderState); 3085894Sgblack@eecs.umich.edu if (handleReadPacket(pkt1)) { 3095894Sgblack@eecs.umich.edu send_state->clearFromParent(); 3107911Shestness@cs.utexas.edu send_state = dynamic_cast<SplitFragmentSenderState *>( 3117911Shestness@cs.utexas.edu pkt2->senderState); 3125894Sgblack@eecs.umich.edu if (handleReadPacket(pkt2)) { 3135894Sgblack@eecs.umich.edu send_state->clearFromParent(); 3145894Sgblack@eecs.umich.edu } 3155894Sgblack@eecs.umich.edu } 3165894Sgblack@eecs.umich.edu } else { 3175894Sgblack@eecs.umich.edu dcache_pkt = pkt1; 3187911Shestness@cs.utexas.edu SplitFragmentSenderState * send_state = 3197911Shestness@cs.utexas.edu dynamic_cast<SplitFragmentSenderState *>(pkt1->senderState); 3205894Sgblack@eecs.umich.edu if (handleWritePacket()) { 3215894Sgblack@eecs.umich.edu send_state->clearFromParent(); 3225894Sgblack@eecs.umich.edu dcache_pkt = pkt2; 3237911Shestness@cs.utexas.edu send_state = dynamic_cast<SplitFragmentSenderState *>( 3247911Shestness@cs.utexas.edu pkt2->senderState); 3255894Sgblack@eecs.umich.edu if (handleWritePacket()) { 3265894Sgblack@eecs.umich.edu send_state->clearFromParent(); 3275894Sgblack@eecs.umich.edu } 3285894Sgblack@eecs.umich.edu } 3295894Sgblack@eecs.umich.edu } 3305894Sgblack@eecs.umich.edu} 3315894Sgblack@eecs.umich.edu 3325894Sgblack@eecs.umich.eduvoid 33310379Sandreas.hansson@arm.comTimingSimpleCPU::translationFault(const Fault &fault) 3345894Sgblack@eecs.umich.edu{ 3356739Sgblack@eecs.umich.edu // fault may be NoFault in cases where a fault is suppressed, 3366739Sgblack@eecs.umich.edu // for instance prefetches. 33710464SAndreas.Sandberg@ARM.com updateCycleCounts(); 3385894Sgblack@eecs.umich.edu 3395894Sgblack@eecs.umich.edu if (traceData) { 3405894Sgblack@eecs.umich.edu // Since there was a fault, we shouldn't trace this instruction. 3415894Sgblack@eecs.umich.edu delete traceData; 3425894Sgblack@eecs.umich.edu traceData = NULL; 3435744Sgblack@eecs.umich.edu } 3445744Sgblack@eecs.umich.edu 3455894Sgblack@eecs.umich.edu postExecute(); 3465894Sgblack@eecs.umich.edu 3479442SAndreas.Sandberg@ARM.com advanceInst(fault); 3485894Sgblack@eecs.umich.edu} 3495894Sgblack@eecs.umich.edu 35010653Sandreas.hansson@arm.comPacketPtr 35110653Sandreas.hansson@arm.comTimingSimpleCPU::buildPacket(RequestPtr req, bool read) 3525894Sgblack@eecs.umich.edu{ 35310653Sandreas.hansson@arm.com return read ? Packet::createRead(req) : Packet::createWrite(req); 3545894Sgblack@eecs.umich.edu} 3555894Sgblack@eecs.umich.edu 3565894Sgblack@eecs.umich.eduvoid 3575894Sgblack@eecs.umich.eduTimingSimpleCPU::buildSplitPacket(PacketPtr &pkt1, PacketPtr &pkt2, 3585894Sgblack@eecs.umich.edu RequestPtr req1, RequestPtr req2, RequestPtr req, 3595894Sgblack@eecs.umich.edu uint8_t *data, bool read) 3605894Sgblack@eecs.umich.edu{ 3615894Sgblack@eecs.umich.edu pkt1 = pkt2 = NULL; 3625894Sgblack@eecs.umich.edu 3638105Sgblack@eecs.umich.edu assert(!req1->isMmappedIpr() && !req2->isMmappedIpr()); 3645744Sgblack@eecs.umich.edu 3655894Sgblack@eecs.umich.edu if (req->getFlags().isSet(Request::NO_ACCESS)) { 36610653Sandreas.hansson@arm.com pkt1 = buildPacket(req, read); 3675894Sgblack@eecs.umich.edu return; 3685894Sgblack@eecs.umich.edu } 3695894Sgblack@eecs.umich.edu 37010653Sandreas.hansson@arm.com pkt1 = buildPacket(req1, read); 37110653Sandreas.hansson@arm.com pkt2 = buildPacket(req2, read); 3725894Sgblack@eecs.umich.edu 3738949Sandreas.hansson@arm.com PacketPtr pkt = new Packet(req, pkt1->cmd.responseCommand()); 3745744Sgblack@eecs.umich.edu 37510566Sandreas.hansson@arm.com pkt->dataDynamic<uint8_t>(data); 3765744Sgblack@eecs.umich.edu pkt1->dataStatic<uint8_t>(data); 3775744Sgblack@eecs.umich.edu pkt2->dataStatic<uint8_t>(data + req1->getSize()); 3785744Sgblack@eecs.umich.edu 3795744Sgblack@eecs.umich.edu SplitMainSenderState * main_send_state = new SplitMainSenderState; 3805744Sgblack@eecs.umich.edu pkt->senderState = main_send_state; 3815744Sgblack@eecs.umich.edu main_send_state->fragments[0] = pkt1; 3825744Sgblack@eecs.umich.edu main_send_state->fragments[1] = pkt2; 3835744Sgblack@eecs.umich.edu main_send_state->outstanding = 2; 3845744Sgblack@eecs.umich.edu pkt1->senderState = new SplitFragmentSenderState(pkt, 0); 3855744Sgblack@eecs.umich.edu pkt2->senderState = new SplitFragmentSenderState(pkt, 1); 3865744Sgblack@eecs.umich.edu} 3875744Sgblack@eecs.umich.edu 3882623SN/AFault 3898444Sgblack@eecs.umich.eduTimingSimpleCPU::readMem(Addr addr, uint8_t *data, 3908444Sgblack@eecs.umich.edu unsigned size, unsigned flags) 3912623SN/A{ 3925728Sgblack@eecs.umich.edu Fault fault; 3935728Sgblack@eecs.umich.edu const int asid = 0; 3946221Snate@binkert.org const ThreadID tid = 0; 3957720Sgblack@eecs.umich.edu const Addr pc = thread->instAddr(); 3969814Sandreas.hansson@arm.com unsigned block_size = cacheLineSize(); 3976973Stjones1@inf.ed.ac.uk BaseTLB::Mode mode = BaseTLB::Read; 3982623SN/A 39910665SAli.Saidi@ARM.com if (traceData) 40010665SAli.Saidi@ARM.com traceData->setMem(addr, size, flags); 4017045Ssteve.reinhardt@amd.com 4027520Sgblack@eecs.umich.edu RequestPtr req = new Request(asid, addr, size, 4038832SAli.Saidi@ARM.com flags, dataMasterId(), pc, _cpuId, tid); 4045728Sgblack@eecs.umich.edu 40510024Sdam.sunwoo@arm.com req->taskId(taskId()); 40610024Sdam.sunwoo@arm.com 4077520Sgblack@eecs.umich.edu Addr split_addr = roundDown(addr + size - 1, block_size); 4085744Sgblack@eecs.umich.edu assert(split_addr <= addr || split_addr - addr < block_size); 4095728Sgblack@eecs.umich.edu 4105894Sgblack@eecs.umich.edu _status = DTBWaitResponse; 4115744Sgblack@eecs.umich.edu if (split_addr > addr) { 4125894Sgblack@eecs.umich.edu RequestPtr req1, req2; 4136102Sgblack@eecs.umich.edu assert(!req->isLLSC() && !req->isSwap()); 4145894Sgblack@eecs.umich.edu req->splitOnVaddr(split_addr, req1, req2); 4155894Sgblack@eecs.umich.edu 4166973Stjones1@inf.ed.ac.uk WholeTranslationState *state = 4177520Sgblack@eecs.umich.edu new WholeTranslationState(req, req1, req2, new uint8_t[size], 4186973Stjones1@inf.ed.ac.uk NULL, mode); 4198486Sgblack@eecs.umich.edu DataTranslation<TimingSimpleCPU *> *trans1 = 4208486Sgblack@eecs.umich.edu new DataTranslation<TimingSimpleCPU *>(this, state, 0); 4218486Sgblack@eecs.umich.edu DataTranslation<TimingSimpleCPU *> *trans2 = 4228486Sgblack@eecs.umich.edu new DataTranslation<TimingSimpleCPU *>(this, state, 1); 4236973Stjones1@inf.ed.ac.uk 4246973Stjones1@inf.ed.ac.uk thread->dtb->translateTiming(req1, tc, trans1, mode); 4256973Stjones1@inf.ed.ac.uk thread->dtb->translateTiming(req2, tc, trans2, mode); 4265744Sgblack@eecs.umich.edu } else { 4276973Stjones1@inf.ed.ac.uk WholeTranslationState *state = 4287520Sgblack@eecs.umich.edu new WholeTranslationState(req, new uint8_t[size], NULL, mode); 4298486Sgblack@eecs.umich.edu DataTranslation<TimingSimpleCPU *> *translation 4308486Sgblack@eecs.umich.edu = new DataTranslation<TimingSimpleCPU *>(this, state); 4316973Stjones1@inf.ed.ac.uk thread->dtb->translateTiming(req, tc, translation, mode); 4322623SN/A } 4332623SN/A 4345728Sgblack@eecs.umich.edu return NoFault; 4352623SN/A} 4362623SN/A 4375728Sgblack@eecs.umich.edubool 4385728Sgblack@eecs.umich.eduTimingSimpleCPU::handleWritePacket() 4395728Sgblack@eecs.umich.edu{ 4405728Sgblack@eecs.umich.edu RequestPtr req = dcache_pkt->req; 4418105Sgblack@eecs.umich.edu if (req->isMmappedIpr()) { 4429180Sandreas.hansson@arm.com Cycles delay = TheISA::handleIprWrite(thread->getTC(), dcache_pkt); 4439179Sandreas.hansson@arm.com new IprEvent(dcache_pkt, this, clockEdge(delay)); 4445728Sgblack@eecs.umich.edu _status = DcacheWaitResponse; 4455728Sgblack@eecs.umich.edu dcache_pkt = NULL; 4468975Sandreas.hansson@arm.com } else if (!dcachePort.sendTimingReq(dcache_pkt)) { 4475728Sgblack@eecs.umich.edu _status = DcacheRetry; 4485728Sgblack@eecs.umich.edu } else { 4495728Sgblack@eecs.umich.edu _status = DcacheWaitResponse; 4505728Sgblack@eecs.umich.edu // memory system takes ownership of packet 4515728Sgblack@eecs.umich.edu dcache_pkt = NULL; 4525728Sgblack@eecs.umich.edu } 4535728Sgblack@eecs.umich.edu return dcache_pkt == NULL; 4545728Sgblack@eecs.umich.edu} 4552623SN/A 4562623SN/AFault 4578444Sgblack@eecs.umich.eduTimingSimpleCPU::writeMem(uint8_t *data, unsigned size, 4588444Sgblack@eecs.umich.edu Addr addr, unsigned flags, uint64_t *res) 4592623SN/A{ 4608443Sgblack@eecs.umich.edu uint8_t *newData = new uint8_t[size]; 4615728Sgblack@eecs.umich.edu const int asid = 0; 4626221Snate@binkert.org const ThreadID tid = 0; 4637720Sgblack@eecs.umich.edu const Addr pc = thread->instAddr(); 4649814Sandreas.hansson@arm.com unsigned block_size = cacheLineSize(); 4656973Stjones1@inf.ed.ac.uk BaseTLB::Mode mode = BaseTLB::Write; 4663169Sstever@eecs.umich.edu 46710031SAli.Saidi@ARM.com if (data == NULL) { 46810031SAli.Saidi@ARM.com assert(flags & Request::CACHE_BLOCK_ZERO); 46910031SAli.Saidi@ARM.com // This must be a cache block cleaning request 47010031SAli.Saidi@ARM.com memset(newData, 0, size); 47110031SAli.Saidi@ARM.com } else { 47210031SAli.Saidi@ARM.com memcpy(newData, data, size); 47310031SAli.Saidi@ARM.com } 47410031SAli.Saidi@ARM.com 47510665SAli.Saidi@ARM.com if (traceData) 47610665SAli.Saidi@ARM.com traceData->setMem(addr, size, flags); 4777045Ssteve.reinhardt@amd.com 4787520Sgblack@eecs.umich.edu RequestPtr req = new Request(asid, addr, size, 4798832SAli.Saidi@ARM.com flags, dataMasterId(), pc, _cpuId, tid); 4805728Sgblack@eecs.umich.edu 48110024Sdam.sunwoo@arm.com req->taskId(taskId()); 48210024Sdam.sunwoo@arm.com 4837520Sgblack@eecs.umich.edu Addr split_addr = roundDown(addr + size - 1, block_size); 4845744Sgblack@eecs.umich.edu assert(split_addr <= addr || split_addr - addr < block_size); 4855728Sgblack@eecs.umich.edu 4865894Sgblack@eecs.umich.edu _status = DTBWaitResponse; 4875744Sgblack@eecs.umich.edu if (split_addr > addr) { 4885894Sgblack@eecs.umich.edu RequestPtr req1, req2; 4896102Sgblack@eecs.umich.edu assert(!req->isLLSC() && !req->isSwap()); 4905894Sgblack@eecs.umich.edu req->splitOnVaddr(split_addr, req1, req2); 4915894Sgblack@eecs.umich.edu 4926973Stjones1@inf.ed.ac.uk WholeTranslationState *state = 4938443Sgblack@eecs.umich.edu new WholeTranslationState(req, req1, req2, newData, res, mode); 4948486Sgblack@eecs.umich.edu DataTranslation<TimingSimpleCPU *> *trans1 = 4958486Sgblack@eecs.umich.edu new DataTranslation<TimingSimpleCPU *>(this, state, 0); 4968486Sgblack@eecs.umich.edu DataTranslation<TimingSimpleCPU *> *trans2 = 4978486Sgblack@eecs.umich.edu new DataTranslation<TimingSimpleCPU *>(this, state, 1); 4986973Stjones1@inf.ed.ac.uk 4996973Stjones1@inf.ed.ac.uk thread->dtb->translateTiming(req1, tc, trans1, mode); 5006973Stjones1@inf.ed.ac.uk thread->dtb->translateTiming(req2, tc, trans2, mode); 5015744Sgblack@eecs.umich.edu } else { 5026973Stjones1@inf.ed.ac.uk WholeTranslationState *state = 5038443Sgblack@eecs.umich.edu new WholeTranslationState(req, newData, res, mode); 5048486Sgblack@eecs.umich.edu DataTranslation<TimingSimpleCPU *> *translation = 5058486Sgblack@eecs.umich.edu new DataTranslation<TimingSimpleCPU *>(this, state); 5066973Stjones1@inf.ed.ac.uk thread->dtb->translateTiming(req, tc, translation, mode); 5072623SN/A } 5082623SN/A 5097045Ssteve.reinhardt@amd.com // Translation faults will be returned via finishTranslation() 5105728Sgblack@eecs.umich.edu return NoFault; 5112623SN/A} 5122623SN/A 5132623SN/A 5142623SN/Avoid 5156973Stjones1@inf.ed.ac.ukTimingSimpleCPU::finishTranslation(WholeTranslationState *state) 5166973Stjones1@inf.ed.ac.uk{ 5179342SAndreas.Sandberg@arm.com _status = BaseSimpleCPU::Running; 5186973Stjones1@inf.ed.ac.uk 5196973Stjones1@inf.ed.ac.uk if (state->getFault() != NoFault) { 5206973Stjones1@inf.ed.ac.uk if (state->isPrefetch()) { 5216973Stjones1@inf.ed.ac.uk state->setNoFault(); 5226973Stjones1@inf.ed.ac.uk } 5237691SAli.Saidi@ARM.com delete [] state->data; 5246973Stjones1@inf.ed.ac.uk state->deleteReqs(); 5256973Stjones1@inf.ed.ac.uk translationFault(state->getFault()); 5266973Stjones1@inf.ed.ac.uk } else { 5276973Stjones1@inf.ed.ac.uk if (!state->isSplit) { 5286973Stjones1@inf.ed.ac.uk sendData(state->mainReq, state->data, state->res, 5296973Stjones1@inf.ed.ac.uk state->mode == BaseTLB::Read); 5306973Stjones1@inf.ed.ac.uk } else { 5316973Stjones1@inf.ed.ac.uk sendSplitData(state->sreqLow, state->sreqHigh, state->mainReq, 5326973Stjones1@inf.ed.ac.uk state->data, state->mode == BaseTLB::Read); 5336973Stjones1@inf.ed.ac.uk } 5346973Stjones1@inf.ed.ac.uk } 5356973Stjones1@inf.ed.ac.uk 5366973Stjones1@inf.ed.ac.uk delete state; 5376973Stjones1@inf.ed.ac.uk} 5386973Stjones1@inf.ed.ac.uk 5396973Stjones1@inf.ed.ac.uk 5406973Stjones1@inf.ed.ac.ukvoid 5412623SN/ATimingSimpleCPU::fetch() 5422623SN/A{ 5435221Ssaidi@eecs.umich.edu DPRINTF(SimpleCPU, "Fetch\n"); 5445221Ssaidi@eecs.umich.edu 54510596Sgabeblack@google.com if (!curStaticInst || !curStaticInst->isDelayedCommit()) { 5463387Sgblack@eecs.umich.edu checkForInterrupts(); 54710596Sgabeblack@google.com checkPcEventQueue(); 54810596Sgabeblack@google.com } 5495348Ssaidi@eecs.umich.edu 5508143SAli.Saidi@ARM.com // We must have just got suspended by a PC event 5518143SAli.Saidi@ARM.com if (_status == Idle) 5528143SAli.Saidi@ARM.com return; 5538143SAli.Saidi@ARM.com 5547720Sgblack@eecs.umich.edu TheISA::PCState pcState = thread->pcState(); 5557720Sgblack@eecs.umich.edu bool needToFetch = !isRomMicroPC(pcState.microPC()) && !curMacroStaticInst; 5562623SN/A 5577720Sgblack@eecs.umich.edu if (needToFetch) { 5589342SAndreas.Sandberg@arm.com _status = BaseSimpleCPU::Running; 5595669Sgblack@eecs.umich.edu Request *ifetch_req = new Request(); 56010024Sdam.sunwoo@arm.com ifetch_req->taskId(taskId()); 5615712Shsul@eecs.umich.edu ifetch_req->setThreadContext(_cpuId, /* thread ID */ 0); 5625894Sgblack@eecs.umich.edu setupFetchRequest(ifetch_req); 5638277SAli.Saidi@ARM.com DPRINTF(SimpleCPU, "Translating address %#x\n", ifetch_req->getVaddr()); 5646023Snate@binkert.org thread->itb->translateTiming(ifetch_req, tc, &fetchTranslation, 5656023Snate@binkert.org BaseTLB::Execute); 5662623SN/A } else { 5675669Sgblack@eecs.umich.edu _status = IcacheWaitResponse; 5685669Sgblack@eecs.umich.edu completeIfetch(NULL); 5695894Sgblack@eecs.umich.edu 57010464SAndreas.Sandberg@ARM.com updateCycleCounts(); 5715894Sgblack@eecs.umich.edu } 5725894Sgblack@eecs.umich.edu} 5735894Sgblack@eecs.umich.edu 5745894Sgblack@eecs.umich.edu 5755894Sgblack@eecs.umich.eduvoid 57610379Sandreas.hansson@arm.comTimingSimpleCPU::sendFetch(const Fault &fault, RequestPtr req, 57710379Sandreas.hansson@arm.com ThreadContext *tc) 5785894Sgblack@eecs.umich.edu{ 5795894Sgblack@eecs.umich.edu if (fault == NoFault) { 5808277SAli.Saidi@ARM.com DPRINTF(SimpleCPU, "Sending fetch for addr %#x(pa: %#x)\n", 5818277SAli.Saidi@ARM.com req->getVaddr(), req->getPaddr()); 5828949Sandreas.hansson@arm.com ifetch_pkt = new Packet(req, MemCmd::ReadReq); 5835894Sgblack@eecs.umich.edu ifetch_pkt->dataStatic(&inst); 5848277SAli.Saidi@ARM.com DPRINTF(SimpleCPU, " -- pkt addr: %#x\n", ifetch_pkt->getAddr()); 5855894Sgblack@eecs.umich.edu 5868975Sandreas.hansson@arm.com if (!icachePort.sendTimingReq(ifetch_pkt)) { 5875894Sgblack@eecs.umich.edu // Need to wait for retry 5885894Sgblack@eecs.umich.edu _status = IcacheRetry; 5895894Sgblack@eecs.umich.edu } else { 5905894Sgblack@eecs.umich.edu // Need to wait for cache to respond 5915894Sgblack@eecs.umich.edu _status = IcacheWaitResponse; 5925894Sgblack@eecs.umich.edu // ownership of packet transferred to memory system 5935894Sgblack@eecs.umich.edu ifetch_pkt = NULL; 5945894Sgblack@eecs.umich.edu } 5955894Sgblack@eecs.umich.edu } else { 5968277SAli.Saidi@ARM.com DPRINTF(SimpleCPU, "Translation of addr %#x faulted\n", req->getVaddr()); 5975894Sgblack@eecs.umich.edu delete req; 5985894Sgblack@eecs.umich.edu // fetch fault: advance directly to next instruction (fault handler) 5999342SAndreas.Sandberg@arm.com _status = BaseSimpleCPU::Running; 6005894Sgblack@eecs.umich.edu advanceInst(fault); 6012623SN/A } 6023222Sktlim@umich.edu 60310464SAndreas.Sandberg@ARM.com updateCycleCounts(); 6042623SN/A} 6052623SN/A 6062623SN/A 6072623SN/Avoid 60810379Sandreas.hansson@arm.comTimingSimpleCPU::advanceInst(const Fault &fault) 6092623SN/A{ 6108276SAli.Saidi@ARM.com if (_status == Faulting) 6118276SAli.Saidi@ARM.com return; 6128276SAli.Saidi@ARM.com 6138276SAli.Saidi@ARM.com if (fault != NoFault) { 6148276SAli.Saidi@ARM.com advancePC(fault); 6158276SAli.Saidi@ARM.com DPRINTF(SimpleCPU, "Fault occured, scheduling fetch event\n"); 6169648Sdam.sunwoo@arm.com reschedule(fetchEvent, clockEdge(), true); 6178276SAli.Saidi@ARM.com _status = Faulting; 6188276SAli.Saidi@ARM.com return; 6198276SAli.Saidi@ARM.com } 6208276SAli.Saidi@ARM.com 6218276SAli.Saidi@ARM.com 6228276SAli.Saidi@ARM.com if (!stayAtPC) 6235726Sgblack@eecs.umich.edu advancePC(fault); 6242623SN/A 6259442SAndreas.Sandberg@ARM.com if (tryCompleteDrain()) 6269442SAndreas.Sandberg@ARM.com return; 6279442SAndreas.Sandberg@ARM.com 6289342SAndreas.Sandberg@arm.com if (_status == BaseSimpleCPU::Running) { 6292631SN/A // kick off fetch of next instruction... callback from icache 6302631SN/A // response will cause that instruction to be executed, 6312631SN/A // keeping the CPU running. 6322631SN/A fetch(); 6332631SN/A } 6342623SN/A} 6352623SN/A 6362623SN/A 6372623SN/Avoid 6383349Sbinkertn@umich.eduTimingSimpleCPU::completeIfetch(PacketPtr pkt) 6392623SN/A{ 6408277SAli.Saidi@ARM.com DPRINTF(SimpleCPU, "Complete ICache Fetch for addr %#x\n", pkt ? 6418277SAli.Saidi@ARM.com pkt->getAddr() : 0); 6428277SAli.Saidi@ARM.com 6432623SN/A // received a response from the icache: execute the received 6442623SN/A // instruction 6455669Sgblack@eecs.umich.edu assert(!pkt || !pkt->isError()); 6462623SN/A assert(_status == IcacheWaitResponse); 6472798Sktlim@umich.edu 6489342SAndreas.Sandberg@arm.com _status = BaseSimpleCPU::Running; 6492644Sstever@eecs.umich.edu 65010464SAndreas.Sandberg@ARM.com updateCycleCounts(); 6513222Sktlim@umich.edu 65210020Smatt.horsnell@ARM.com if (pkt) 65310020Smatt.horsnell@ARM.com pkt->req->setAccessLatency(); 65410020Smatt.horsnell@ARM.com 65510020Smatt.horsnell@ARM.com 6562623SN/A preExecute(); 6577725SAli.Saidi@ARM.com if (curStaticInst && curStaticInst->isMemRef()) { 6582623SN/A // load or store: just send to dcache 6592623SN/A Fault fault = curStaticInst->initiateAcc(this, traceData); 6607945SAli.Saidi@ARM.com 6617945SAli.Saidi@ARM.com // If we're not running now the instruction will complete in a dcache 6627945SAli.Saidi@ARM.com // response callback or the instruction faulted and has started an 6637945SAli.Saidi@ARM.com // ifetch 6649342SAndreas.Sandberg@arm.com if (_status == BaseSimpleCPU::Running) { 6655894Sgblack@eecs.umich.edu if (fault != NoFault && traceData) { 6665001Sgblack@eecs.umich.edu // If there was a fault, we shouldn't trace this instruction. 6675001Sgblack@eecs.umich.edu delete traceData; 6685001Sgblack@eecs.umich.edu traceData = NULL; 6693170Sstever@eecs.umich.edu } 6704998Sgblack@eecs.umich.edu 6712644Sstever@eecs.umich.edu postExecute(); 6725103Ssaidi@eecs.umich.edu // @todo remove me after debugging with legion done 6735103Ssaidi@eecs.umich.edu if (curStaticInst && (!curStaticInst->isMicroop() || 6745103Ssaidi@eecs.umich.edu curStaticInst->isFirstMicroop())) 6755103Ssaidi@eecs.umich.edu instCnt++; 6762644Sstever@eecs.umich.edu advanceInst(fault); 6772644Sstever@eecs.umich.edu } 6785726Sgblack@eecs.umich.edu } else if (curStaticInst) { 6792623SN/A // non-memory instruction: execute completely now 6802623SN/A Fault fault = curStaticInst->execute(this, traceData); 6814998Sgblack@eecs.umich.edu 6824998Sgblack@eecs.umich.edu // keep an instruction count 6834998Sgblack@eecs.umich.edu if (fault == NoFault) 6844998Sgblack@eecs.umich.edu countInst(); 6857655Sali.saidi@arm.com else if (traceData && !DTRACE(ExecFaulting)) { 6865001Sgblack@eecs.umich.edu delete traceData; 6875001Sgblack@eecs.umich.edu traceData = NULL; 6885001Sgblack@eecs.umich.edu } 6894998Sgblack@eecs.umich.edu 6902644Sstever@eecs.umich.edu postExecute(); 6915103Ssaidi@eecs.umich.edu // @todo remove me after debugging with legion done 6925103Ssaidi@eecs.umich.edu if (curStaticInst && (!curStaticInst->isMicroop() || 6935103Ssaidi@eecs.umich.edu curStaticInst->isFirstMicroop())) 6945103Ssaidi@eecs.umich.edu instCnt++; 6952644Sstever@eecs.umich.edu advanceInst(fault); 6965726Sgblack@eecs.umich.edu } else { 6975726Sgblack@eecs.umich.edu advanceInst(NoFault); 6982623SN/A } 6993658Sktlim@umich.edu 7005669Sgblack@eecs.umich.edu if (pkt) { 7015669Sgblack@eecs.umich.edu delete pkt->req; 7025669Sgblack@eecs.umich.edu delete pkt; 7035669Sgblack@eecs.umich.edu } 7042623SN/A} 7052623SN/A 7062948Ssaidi@eecs.umich.eduvoid 7072948Ssaidi@eecs.umich.eduTimingSimpleCPU::IcachePort::ITickEvent::process() 7082948Ssaidi@eecs.umich.edu{ 7092948Ssaidi@eecs.umich.edu cpu->completeIfetch(pkt); 7102948Ssaidi@eecs.umich.edu} 7112623SN/A 7122623SN/Abool 7138975Sandreas.hansson@arm.comTimingSimpleCPU::IcachePort::recvTimingResp(PacketPtr pkt) 7142623SN/A{ 71510669Sandreas.hansson@arm.com DPRINTF(SimpleCPU, "Received fetch response %#x\n", pkt->getAddr()); 71610669Sandreas.hansson@arm.com // we should only ever see one response per cycle since we only 71710669Sandreas.hansson@arm.com // issue a new request once this response is sunk 71810669Sandreas.hansson@arm.com assert(!tickEvent.scheduled()); 7199165Sandreas.hansson@arm.com // delay processing of returned data until next CPU clock edge 72010669Sandreas.hansson@arm.com tickEvent.schedule(pkt, cpu->clockEdge()); 7218948Sandreas.hansson@arm.com 7224433Ssaidi@eecs.umich.edu return true; 7232623SN/A} 7242623SN/A 7252657Ssaidi@eecs.umich.eduvoid 72610713Sandreas.hansson@arm.comTimingSimpleCPU::IcachePort::recvReqRetry() 7272623SN/A{ 7282623SN/A // we shouldn't get a retry unless we have a packet that we're 7292623SN/A // waiting to transmit 7302623SN/A assert(cpu->ifetch_pkt != NULL); 7312623SN/A assert(cpu->_status == IcacheRetry); 7323349Sbinkertn@umich.edu PacketPtr tmp = cpu->ifetch_pkt; 7338975Sandreas.hansson@arm.com if (sendTimingReq(tmp)) { 7342657Ssaidi@eecs.umich.edu cpu->_status = IcacheWaitResponse; 7352657Ssaidi@eecs.umich.edu cpu->ifetch_pkt = NULL; 7362657Ssaidi@eecs.umich.edu } 7372623SN/A} 7382623SN/A 7392623SN/Avoid 7403349Sbinkertn@umich.eduTimingSimpleCPU::completeDataAccess(PacketPtr pkt) 7412623SN/A{ 7422623SN/A // received a response from the dcache: complete the load or store 7432623SN/A // instruction 7444870Sstever@eecs.umich.edu assert(!pkt->isError()); 7457516Shestness@cs.utexas.edu assert(_status == DcacheWaitResponse || _status == DTBWaitResponse || 7467516Shestness@cs.utexas.edu pkt->req->getFlags().isSet(Request::NO_ACCESS)); 7472623SN/A 74810020Smatt.horsnell@ARM.com pkt->req->setAccessLatency(); 74910464SAndreas.Sandberg@ARM.com 75010464SAndreas.Sandberg@ARM.com updateCycleCounts(); 7513184Srdreslin@umich.edu 7525728Sgblack@eecs.umich.edu if (pkt->senderState) { 7535728Sgblack@eecs.umich.edu SplitFragmentSenderState * send_state = 7545728Sgblack@eecs.umich.edu dynamic_cast<SplitFragmentSenderState *>(pkt->senderState); 7555728Sgblack@eecs.umich.edu assert(send_state); 7565728Sgblack@eecs.umich.edu delete pkt->req; 7575728Sgblack@eecs.umich.edu delete pkt; 7585728Sgblack@eecs.umich.edu PacketPtr big_pkt = send_state->bigPkt; 7595728Sgblack@eecs.umich.edu delete send_state; 7605728Sgblack@eecs.umich.edu 7615728Sgblack@eecs.umich.edu SplitMainSenderState * main_send_state = 7625728Sgblack@eecs.umich.edu dynamic_cast<SplitMainSenderState *>(big_pkt->senderState); 7635728Sgblack@eecs.umich.edu assert(main_send_state); 7645728Sgblack@eecs.umich.edu // Record the fact that this packet is no longer outstanding. 7655728Sgblack@eecs.umich.edu assert(main_send_state->outstanding != 0); 7665728Sgblack@eecs.umich.edu main_send_state->outstanding--; 7675728Sgblack@eecs.umich.edu 7685728Sgblack@eecs.umich.edu if (main_send_state->outstanding) { 7695728Sgblack@eecs.umich.edu return; 7705728Sgblack@eecs.umich.edu } else { 7715728Sgblack@eecs.umich.edu delete main_send_state; 7725728Sgblack@eecs.umich.edu big_pkt->senderState = NULL; 7735728Sgblack@eecs.umich.edu pkt = big_pkt; 7745728Sgblack@eecs.umich.edu } 7755728Sgblack@eecs.umich.edu } 7765728Sgblack@eecs.umich.edu 7779342SAndreas.Sandberg@arm.com _status = BaseSimpleCPU::Running; 7785728Sgblack@eecs.umich.edu 7792623SN/A Fault fault = curStaticInst->completeAcc(pkt, this, traceData); 7802623SN/A 7814998Sgblack@eecs.umich.edu // keep an instruction count 7824998Sgblack@eecs.umich.edu if (fault == NoFault) 7834998Sgblack@eecs.umich.edu countInst(); 7845001Sgblack@eecs.umich.edu else if (traceData) { 7855001Sgblack@eecs.umich.edu // If there was a fault, we shouldn't trace this instruction. 7865001Sgblack@eecs.umich.edu delete traceData; 7875001Sgblack@eecs.umich.edu traceData = NULL; 7885001Sgblack@eecs.umich.edu } 7894998Sgblack@eecs.umich.edu 7902644Sstever@eecs.umich.edu delete pkt->req; 7912644Sstever@eecs.umich.edu delete pkt; 7922644Sstever@eecs.umich.edu 7933184Srdreslin@umich.edu postExecute(); 7943227Sktlim@umich.edu 7952644Sstever@eecs.umich.edu advanceInst(fault); 7962623SN/A} 7972623SN/A 79810030SAli.Saidi@ARM.comvoid 79910464SAndreas.Sandberg@ARM.comTimingSimpleCPU::updateCycleCounts() 80010464SAndreas.Sandberg@ARM.com{ 80110464SAndreas.Sandberg@ARM.com const Cycles delta(curCycle() - previousCycle); 80210464SAndreas.Sandberg@ARM.com 80310464SAndreas.Sandberg@ARM.com numCycles += delta; 80410464SAndreas.Sandberg@ARM.com ppCycles->notify(delta); 80510464SAndreas.Sandberg@ARM.com 80610464SAndreas.Sandberg@ARM.com previousCycle = curCycle(); 80710464SAndreas.Sandberg@ARM.com} 80810464SAndreas.Sandberg@ARM.com 80910464SAndreas.Sandberg@ARM.comvoid 81010030SAli.Saidi@ARM.comTimingSimpleCPU::DcachePort::recvTimingSnoopReq(PacketPtr pkt) 81110030SAli.Saidi@ARM.com{ 81210529Smorr@cs.wisc.edu // X86 ISA: Snooping an invalidation for monitor/mwait 81310529Smorr@cs.wisc.edu if(cpu->getAddrMonitor()->doMonitor(pkt)) { 81410529Smorr@cs.wisc.edu cpu->wakeup(); 81510529Smorr@cs.wisc.edu } 81610030SAli.Saidi@ARM.com TheISA::handleLockedSnoop(cpu->thread, pkt, cacheBlockMask); 81710030SAli.Saidi@ARM.com} 81810030SAli.Saidi@ARM.com 81910529Smorr@cs.wisc.eduvoid 82010529Smorr@cs.wisc.eduTimingSimpleCPU::DcachePort::recvFunctionalSnoop(PacketPtr pkt) 82110529Smorr@cs.wisc.edu{ 82210529Smorr@cs.wisc.edu // X86 ISA: Snooping an invalidation for monitor/mwait 82310529Smorr@cs.wisc.edu if(cpu->getAddrMonitor()->doMonitor(pkt)) { 82410529Smorr@cs.wisc.edu cpu->wakeup(); 82510529Smorr@cs.wisc.edu } 82610529Smorr@cs.wisc.edu} 82710030SAli.Saidi@ARM.com 8282623SN/Abool 8298975Sandreas.hansson@arm.comTimingSimpleCPU::DcachePort::recvTimingResp(PacketPtr pkt) 8302623SN/A{ 83110669Sandreas.hansson@arm.com DPRINTF(SimpleCPU, "Received load/store response %#x\n", pkt->getAddr()); 8322948Ssaidi@eecs.umich.edu 83310669Sandreas.hansson@arm.com // The timing CPU is not really ticked, instead it relies on the 83410669Sandreas.hansson@arm.com // memory system (fetch and load/store) to set the pace. 83510669Sandreas.hansson@arm.com if (!tickEvent.scheduled()) { 83610669Sandreas.hansson@arm.com // Delay processing of returned data until next CPU clock edge 83710669Sandreas.hansson@arm.com tickEvent.schedule(pkt, cpu->clockEdge()); 83810669Sandreas.hansson@arm.com return true; 8399165Sandreas.hansson@arm.com } else { 84010669Sandreas.hansson@arm.com // In the case of a split transaction and a cache that is 84110669Sandreas.hansson@arm.com // faster than a CPU we could get two responses in the 84210669Sandreas.hansson@arm.com // same tick, delay the second one 84310713Sandreas.hansson@arm.com if (!retryRespEvent.scheduled()) 84410713Sandreas.hansson@arm.com cpu->schedule(retryRespEvent, cpu->clockEdge(Cycles(1))); 84510669Sandreas.hansson@arm.com return false; 8463310Srdreslin@umich.edu } 8472948Ssaidi@eecs.umich.edu} 8482948Ssaidi@eecs.umich.edu 8492948Ssaidi@eecs.umich.eduvoid 8502948Ssaidi@eecs.umich.eduTimingSimpleCPU::DcachePort::DTickEvent::process() 8512948Ssaidi@eecs.umich.edu{ 8522630SN/A cpu->completeDataAccess(pkt); 8532623SN/A} 8542623SN/A 8552657Ssaidi@eecs.umich.eduvoid 85610713Sandreas.hansson@arm.comTimingSimpleCPU::DcachePort::recvReqRetry() 8572623SN/A{ 8582623SN/A // we shouldn't get a retry unless we have a packet that we're 8592623SN/A // waiting to transmit 8602623SN/A assert(cpu->dcache_pkt != NULL); 8612623SN/A assert(cpu->_status == DcacheRetry); 8623349Sbinkertn@umich.edu PacketPtr tmp = cpu->dcache_pkt; 8635728Sgblack@eecs.umich.edu if (tmp->senderState) { 8645728Sgblack@eecs.umich.edu // This is a packet from a split access. 8655728Sgblack@eecs.umich.edu SplitFragmentSenderState * send_state = 8665728Sgblack@eecs.umich.edu dynamic_cast<SplitFragmentSenderState *>(tmp->senderState); 8675728Sgblack@eecs.umich.edu assert(send_state); 8685728Sgblack@eecs.umich.edu PacketPtr big_pkt = send_state->bigPkt; 8695728Sgblack@eecs.umich.edu 8705728Sgblack@eecs.umich.edu SplitMainSenderState * main_send_state = 8715728Sgblack@eecs.umich.edu dynamic_cast<SplitMainSenderState *>(big_pkt->senderState); 8725728Sgblack@eecs.umich.edu assert(main_send_state); 8735728Sgblack@eecs.umich.edu 8748975Sandreas.hansson@arm.com if (sendTimingReq(tmp)) { 8755728Sgblack@eecs.umich.edu // If we were able to send without retrying, record that fact 8765728Sgblack@eecs.umich.edu // and try sending the other fragment. 8775728Sgblack@eecs.umich.edu send_state->clearFromParent(); 8785728Sgblack@eecs.umich.edu int other_index = main_send_state->getPendingFragment(); 8795728Sgblack@eecs.umich.edu if (other_index > 0) { 8805728Sgblack@eecs.umich.edu tmp = main_send_state->fragments[other_index]; 8815728Sgblack@eecs.umich.edu cpu->dcache_pkt = tmp; 8825728Sgblack@eecs.umich.edu if ((big_pkt->isRead() && cpu->handleReadPacket(tmp)) || 8835728Sgblack@eecs.umich.edu (big_pkt->isWrite() && cpu->handleWritePacket())) { 8845728Sgblack@eecs.umich.edu main_send_state->fragments[other_index] = NULL; 8855728Sgblack@eecs.umich.edu } 8865728Sgblack@eecs.umich.edu } else { 8875728Sgblack@eecs.umich.edu cpu->_status = DcacheWaitResponse; 8885728Sgblack@eecs.umich.edu // memory system takes ownership of packet 8895728Sgblack@eecs.umich.edu cpu->dcache_pkt = NULL; 8905728Sgblack@eecs.umich.edu } 8915728Sgblack@eecs.umich.edu } 8928975Sandreas.hansson@arm.com } else if (sendTimingReq(tmp)) { 8932657Ssaidi@eecs.umich.edu cpu->_status = DcacheWaitResponse; 8943170Sstever@eecs.umich.edu // memory system takes ownership of packet 8952657Ssaidi@eecs.umich.edu cpu->dcache_pkt = NULL; 8962657Ssaidi@eecs.umich.edu } 8972623SN/A} 8982623SN/A 8995606Snate@binkert.orgTimingSimpleCPU::IprEvent::IprEvent(Packet *_pkt, TimingSimpleCPU *_cpu, 9005606Snate@binkert.org Tick t) 9015606Snate@binkert.org : pkt(_pkt), cpu(_cpu) 9025103Ssaidi@eecs.umich.edu{ 9035606Snate@binkert.org cpu->schedule(this, t); 9045103Ssaidi@eecs.umich.edu} 9055103Ssaidi@eecs.umich.edu 9065103Ssaidi@eecs.umich.eduvoid 9075103Ssaidi@eecs.umich.eduTimingSimpleCPU::IprEvent::process() 9085103Ssaidi@eecs.umich.edu{ 9095103Ssaidi@eecs.umich.edu cpu->completeDataAccess(pkt); 9105103Ssaidi@eecs.umich.edu} 9115103Ssaidi@eecs.umich.edu 9125103Ssaidi@eecs.umich.educonst char * 9135336Shines@cs.fsu.eduTimingSimpleCPU::IprEvent::description() const 9145103Ssaidi@eecs.umich.edu{ 9155103Ssaidi@eecs.umich.edu return "Timing Simple CPU Delay IPR event"; 9165103Ssaidi@eecs.umich.edu} 9175103Ssaidi@eecs.umich.edu 9182623SN/A 9195315Sstever@gmail.comvoid 9205315Sstever@gmail.comTimingSimpleCPU::printAddr(Addr a) 9215315Sstever@gmail.com{ 9225315Sstever@gmail.com dcachePort.printAddr(a); 9235315Sstever@gmail.com} 9245315Sstever@gmail.com 9255315Sstever@gmail.com 9262623SN/A//////////////////////////////////////////////////////////////////////// 9272623SN/A// 9282623SN/A// TimingSimpleCPU Simulation Object 9292623SN/A// 9304762Snate@binkert.orgTimingSimpleCPU * 9314762Snate@binkert.orgTimingSimpleCPUParams::create() 9322623SN/A{ 9335529Snate@binkert.org numThreads = 1; 9348779Sgblack@eecs.umich.edu if (!FullSystem && workload.size() != 1) 9354762Snate@binkert.org panic("only one workload allowed"); 9365529Snate@binkert.org return new TimingSimpleCPU(this); 9372623SN/A} 938