timing.cc revision 10533
12623SN/A/* 210030SAli.Saidi@ARM.com * Copyright (c) 2010-2013 ARM Limited 37725SAli.Saidi@ARM.com * All rights reserved 47725SAli.Saidi@ARM.com * 57725SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall 67725SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 77725SAli.Saidi@ARM.com * property including but not limited to intellectual property relating 87725SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software 97725SAli.Saidi@ARM.com * licensed hereunder. You may use the software subject to the license 107725SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated 117725SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software, 127725SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form. 137725SAli.Saidi@ARM.com * 142623SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 152623SN/A * All rights reserved. 162623SN/A * 172623SN/A * Redistribution and use in source and binary forms, with or without 182623SN/A * modification, are permitted provided that the following conditions are 192623SN/A * met: redistributions of source code must retain the above copyright 202623SN/A * notice, this list of conditions and the following disclaimer; 212623SN/A * redistributions in binary form must reproduce the above copyright 222623SN/A * notice, this list of conditions and the following disclaimer in the 232623SN/A * documentation and/or other materials provided with the distribution; 242623SN/A * neither the name of the copyright holders nor the names of its 252623SN/A * contributors may be used to endorse or promote products derived from 262623SN/A * this software without specific prior written permission. 272623SN/A * 282623SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292623SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302623SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312623SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322623SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332623SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342623SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352623SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362623SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372623SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382623SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392665Ssaidi@eecs.umich.edu * 402665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 412623SN/A */ 422623SN/A 433170Sstever@eecs.umich.edu#include "arch/locked_mem.hh" 448105Sgblack@eecs.umich.edu#include "arch/mmapped_ipr.hh" 452623SN/A#include "arch/utility.hh" 464040Ssaidi@eecs.umich.edu#include "base/bigint.hh" 476658Snate@binkert.org#include "config/the_isa.hh" 488229Snate@binkert.org#include "cpu/simple/timing.hh" 492623SN/A#include "cpu/exetrace.hh" 508232Snate@binkert.org#include "debug/Config.hh" 519152Satgutier@umich.edu#include "debug/Drain.hh" 528232Snate@binkert.org#include "debug/ExecFaulting.hh" 538232Snate@binkert.org#include "debug/SimpleCPU.hh" 543348Sbinkertn@umich.edu#include "mem/packet.hh" 553348Sbinkertn@umich.edu#include "mem/packet_access.hh" 564762Snate@binkert.org#include "params/TimingSimpleCPU.hh" 577678Sgblack@eecs.umich.edu#include "sim/faults.hh" 588779Sgblack@eecs.umich.edu#include "sim/full_system.hh" 592901Ssaidi@eecs.umich.edu#include "sim/system.hh" 602623SN/A 6110529Smorr@cs.wisc.edu#include "debug/Mwait.hh" 6210529Smorr@cs.wisc.edu 632623SN/Ausing namespace std; 642623SN/Ausing namespace TheISA; 652623SN/A 662623SN/Avoid 672623SN/ATimingSimpleCPU::init() 682623SN/A{ 692623SN/A BaseCPU::init(); 708921Sandreas.hansson@arm.com 718921Sandreas.hansson@arm.com // Initialise the ThreadContext's memory proxies 728921Sandreas.hansson@arm.com tcBase()->initMemProxies(tcBase()); 738921Sandreas.hansson@arm.com 749433SAndreas.Sandberg@ARM.com if (FullSystem && !params()->switched_out) { 758779Sgblack@eecs.umich.edu for (int i = 0; i < threadContexts.size(); ++i) { 768779Sgblack@eecs.umich.edu ThreadContext *tc = threadContexts[i]; 778779Sgblack@eecs.umich.edu // initialize CPU, including PC 788779Sgblack@eecs.umich.edu TheISA::initCPU(tc, _cpuId); 798779Sgblack@eecs.umich.edu } 802623SN/A } 812623SN/A} 822623SN/A 832623SN/Avoid 848707Sandreas.hansson@arm.comTimingSimpleCPU::TimingCPUPort::TickEvent::schedule(PacketPtr _pkt, Tick t) 852948Ssaidi@eecs.umich.edu{ 862948Ssaidi@eecs.umich.edu pkt = _pkt; 875606Snate@binkert.org cpu->schedule(this, t); 882948Ssaidi@eecs.umich.edu} 892948Ssaidi@eecs.umich.edu 905529Snate@binkert.orgTimingSimpleCPU::TimingSimpleCPU(TimingSimpleCPUParams *p) 918707Sandreas.hansson@arm.com : BaseSimpleCPU(p), fetchTranslation(this), icachePort(this), 929179Sandreas.hansson@arm.com dcachePort(this), ifetch_pkt(NULL), dcache_pkt(NULL), previousCycle(0), 939442SAndreas.Sandberg@ARM.com fetchEvent(this), drainManager(NULL) 942623SN/A{ 952623SN/A _status = Idle; 963647Srdreslin@umich.edu 977897Shestness@cs.utexas.edu system->totalNumInsts = 0; 982623SN/A} 992623SN/A 1002623SN/A 10110030SAli.Saidi@ARM.com 1022623SN/ATimingSimpleCPU::~TimingSimpleCPU() 1032623SN/A{ 1042623SN/A} 1052623SN/A 1062901Ssaidi@eecs.umich.eduunsigned int 1079342SAndreas.Sandberg@arm.comTimingSimpleCPU::drain(DrainManager *drain_manager) 1082798Sktlim@umich.edu{ 1099448SAndreas.Sandberg@ARM.com assert(!drainManager); 1109448SAndreas.Sandberg@ARM.com if (switchedOut()) 1119448SAndreas.Sandberg@ARM.com return 0; 1129448SAndreas.Sandberg@ARM.com 1139342SAndreas.Sandberg@arm.com if (_status == Idle || 1149448SAndreas.Sandberg@ARM.com (_status == BaseSimpleCPU::Running && isDrained())) { 1159442SAndreas.Sandberg@ARM.com DPRINTF(Drain, "No need to drain.\n"); 1162901Ssaidi@eecs.umich.edu return 0; 1172798Sktlim@umich.edu } else { 1189342SAndreas.Sandberg@arm.com drainManager = drain_manager; 1199442SAndreas.Sandberg@ARM.com DPRINTF(Drain, "Requesting drain: %s\n", pcState()); 1209442SAndreas.Sandberg@ARM.com 1219442SAndreas.Sandberg@ARM.com // The fetch event can become descheduled if a drain didn't 1229442SAndreas.Sandberg@ARM.com // succeed on the first attempt. We need to reschedule it if 1239442SAndreas.Sandberg@ARM.com // the CPU is waiting for a microcode routine to complete. 1249448SAndreas.Sandberg@ARM.com if (_status == BaseSimpleCPU::Running && !fetchEvent.scheduled()) 1259648Sdam.sunwoo@arm.com schedule(fetchEvent, clockEdge()); 1269442SAndreas.Sandberg@ARM.com 1272901Ssaidi@eecs.umich.edu return 1; 1282798Sktlim@umich.edu } 1292623SN/A} 1302623SN/A 1312623SN/Avoid 1329342SAndreas.Sandberg@arm.comTimingSimpleCPU::drainResume() 1332623SN/A{ 1349442SAndreas.Sandberg@ARM.com assert(!fetchEvent.scheduled()); 1359448SAndreas.Sandberg@ARM.com assert(!drainManager); 1369448SAndreas.Sandberg@ARM.com if (switchedOut()) 1379448SAndreas.Sandberg@ARM.com return; 1389442SAndreas.Sandberg@ARM.com 1395221Ssaidi@eecs.umich.edu DPRINTF(SimpleCPU, "Resume\n"); 1409523SAndreas.Sandberg@ARM.com verifyMemoryMode(); 1413201Shsul@eecs.umich.edu 1429448SAndreas.Sandberg@ARM.com assert(!threadContexts.empty()); 1439448SAndreas.Sandberg@ARM.com if (threadContexts.size() > 1) 1449448SAndreas.Sandberg@ARM.com fatal("The timing CPU only supports one thread.\n"); 1459448SAndreas.Sandberg@ARM.com 1469448SAndreas.Sandberg@ARM.com if (thread->status() == ThreadContext::Active) { 1475710Scws3k@cs.virginia.edu schedule(fetchEvent, nextCycle()); 1489448SAndreas.Sandberg@ARM.com _status = BaseSimpleCPU::Running; 1499837Slena@cs.wisc,edu notIdleFraction = 1; 1509448SAndreas.Sandberg@ARM.com } else { 1519448SAndreas.Sandberg@ARM.com _status = BaseSimpleCPU::Idle; 1529837Slena@cs.wisc,edu notIdleFraction = 0; 1532623SN/A } 1549442SAndreas.Sandberg@ARM.com} 1552798Sktlim@umich.edu 1569442SAndreas.Sandberg@ARM.combool 1579442SAndreas.Sandberg@ARM.comTimingSimpleCPU::tryCompleteDrain() 1589442SAndreas.Sandberg@ARM.com{ 1599442SAndreas.Sandberg@ARM.com if (!drainManager) 1609442SAndreas.Sandberg@ARM.com return false; 1619442SAndreas.Sandberg@ARM.com 1629442SAndreas.Sandberg@ARM.com DPRINTF(Drain, "tryCompleteDrain: %s\n", pcState()); 1639442SAndreas.Sandberg@ARM.com if (!isDrained()) 1649442SAndreas.Sandberg@ARM.com return false; 1659442SAndreas.Sandberg@ARM.com 1669442SAndreas.Sandberg@ARM.com DPRINTF(Drain, "CPU done draining, processing drain event\n"); 1679442SAndreas.Sandberg@ARM.com drainManager->signalDrainDone(); 1689442SAndreas.Sandberg@ARM.com drainManager = NULL; 1699442SAndreas.Sandberg@ARM.com 1709442SAndreas.Sandberg@ARM.com return true; 1712798Sktlim@umich.edu} 1722798Sktlim@umich.edu 1732798Sktlim@umich.eduvoid 1742798Sktlim@umich.eduTimingSimpleCPU::switchOut() 1752798Sktlim@umich.edu{ 1769429SAndreas.Sandberg@ARM.com BaseSimpleCPU::switchOut(); 1779429SAndreas.Sandberg@ARM.com 1789442SAndreas.Sandberg@ARM.com assert(!fetchEvent.scheduled()); 1799342SAndreas.Sandberg@arm.com assert(_status == BaseSimpleCPU::Running || _status == Idle); 1809442SAndreas.Sandberg@ARM.com assert(!stayAtPC); 1819442SAndreas.Sandberg@ARM.com assert(microPC() == 0); 1829442SAndreas.Sandberg@ARM.com 18310464SAndreas.Sandberg@ARM.com updateCycleCounts(); 1842623SN/A} 1852623SN/A 1862623SN/A 1872623SN/Avoid 1882623SN/ATimingSimpleCPU::takeOverFrom(BaseCPU *oldCPU) 1892623SN/A{ 1909429SAndreas.Sandberg@ARM.com BaseSimpleCPU::takeOverFrom(oldCPU); 1912623SN/A 1929179Sandreas.hansson@arm.com previousCycle = curCycle(); 1932623SN/A} 1942623SN/A 1959523SAndreas.Sandberg@ARM.comvoid 1969523SAndreas.Sandberg@ARM.comTimingSimpleCPU::verifyMemoryMode() const 1979523SAndreas.Sandberg@ARM.com{ 1989524SAndreas.Sandberg@ARM.com if (!system->isTimingMode()) { 1999523SAndreas.Sandberg@ARM.com fatal("The timing CPU requires the memory system to be in " 2009523SAndreas.Sandberg@ARM.com "'timing' mode.\n"); 2019523SAndreas.Sandberg@ARM.com } 2029523SAndreas.Sandberg@ARM.com} 2032623SN/A 2042623SN/Avoid 20510407Smitch.hayenga@arm.comTimingSimpleCPU::activateContext(ThreadID thread_num) 2062623SN/A{ 20710407Smitch.hayenga@arm.com DPRINTF(SimpleCPU, "ActivateContext %d\n", thread_num); 2085221Ssaidi@eecs.umich.edu 2092623SN/A assert(thread_num == 0); 2102683Sktlim@umich.edu assert(thread); 2112623SN/A 2122623SN/A assert(_status == Idle); 2132623SN/A 2149837Slena@cs.wisc,edu notIdleFraction = 1; 2159342SAndreas.Sandberg@arm.com _status = BaseSimpleCPU::Running; 2163686Sktlim@umich.edu 2172623SN/A // kick things off by initiating the fetch of the next instruction 21810407Smitch.hayenga@arm.com schedule(fetchEvent, clockEdge(Cycles(0))); 2192623SN/A} 2202623SN/A 2212623SN/A 2222623SN/Avoid 2238737Skoansin.tan@gmail.comTimingSimpleCPU::suspendContext(ThreadID thread_num) 2242623SN/A{ 2255221Ssaidi@eecs.umich.edu DPRINTF(SimpleCPU, "SuspendContext %d\n", thread_num); 2265221Ssaidi@eecs.umich.edu 2272623SN/A assert(thread_num == 0); 2282683Sktlim@umich.edu assert(thread); 2292623SN/A 2306043Sgblack@eecs.umich.edu if (_status == Idle) 2316043Sgblack@eecs.umich.edu return; 2326043Sgblack@eecs.umich.edu 2339342SAndreas.Sandberg@arm.com assert(_status == BaseSimpleCPU::Running); 2342623SN/A 2352644Sstever@eecs.umich.edu // just change status to Idle... if status != Running, 2362644Sstever@eecs.umich.edu // completeInst() will not initiate fetch of next instruction. 2372623SN/A 2389837Slena@cs.wisc,edu notIdleFraction = 0; 2392623SN/A _status = Idle; 2402623SN/A} 2412623SN/A 2425728Sgblack@eecs.umich.edubool 2435728Sgblack@eecs.umich.eduTimingSimpleCPU::handleReadPacket(PacketPtr pkt) 2445728Sgblack@eecs.umich.edu{ 2455728Sgblack@eecs.umich.edu RequestPtr req = pkt->req; 24610533Sali.saidi@arm.com 24710533Sali.saidi@arm.com // We're about the issues a locked load, so tell the monitor 24810533Sali.saidi@arm.com // to start caring about this address 24910533Sali.saidi@arm.com if (pkt->isRead() && pkt->req->isLLSC()) { 25010533Sali.saidi@arm.com TheISA::handleLockedRead(thread, pkt->req); 25110533Sali.saidi@arm.com } 2528105Sgblack@eecs.umich.edu if (req->isMmappedIpr()) { 2539180Sandreas.hansson@arm.com Cycles delay = TheISA::handleIprRead(thread->getTC(), pkt); 2549179Sandreas.hansson@arm.com new IprEvent(pkt, this, clockEdge(delay)); 2555728Sgblack@eecs.umich.edu _status = DcacheWaitResponse; 2565728Sgblack@eecs.umich.edu dcache_pkt = NULL; 2578975Sandreas.hansson@arm.com } else if (!dcachePort.sendTimingReq(pkt)) { 2585728Sgblack@eecs.umich.edu _status = DcacheRetry; 2595728Sgblack@eecs.umich.edu dcache_pkt = pkt; 2605728Sgblack@eecs.umich.edu } else { 2615728Sgblack@eecs.umich.edu _status = DcacheWaitResponse; 2625728Sgblack@eecs.umich.edu // memory system takes ownership of packet 2635728Sgblack@eecs.umich.edu dcache_pkt = NULL; 2645728Sgblack@eecs.umich.edu } 2655728Sgblack@eecs.umich.edu return dcache_pkt == NULL; 2665728Sgblack@eecs.umich.edu} 2672623SN/A 2685894Sgblack@eecs.umich.eduvoid 2696973Stjones1@inf.ed.ac.ukTimingSimpleCPU::sendData(RequestPtr req, uint8_t *data, uint64_t *res, 2706973Stjones1@inf.ed.ac.uk bool read) 2715744Sgblack@eecs.umich.edu{ 2725894Sgblack@eecs.umich.edu PacketPtr pkt; 2735894Sgblack@eecs.umich.edu buildPacket(pkt, req, read); 2747691SAli.Saidi@ARM.com pkt->dataDynamicArray<uint8_t>(data); 2755894Sgblack@eecs.umich.edu if (req->getFlags().isSet(Request::NO_ACCESS)) { 2765894Sgblack@eecs.umich.edu assert(!dcache_pkt); 2775894Sgblack@eecs.umich.edu pkt->makeResponse(); 2785894Sgblack@eecs.umich.edu completeDataAccess(pkt); 2795894Sgblack@eecs.umich.edu } else if (read) { 2805894Sgblack@eecs.umich.edu handleReadPacket(pkt); 2815894Sgblack@eecs.umich.edu } else { 2825894Sgblack@eecs.umich.edu bool do_access = true; // flag to suppress cache access 2835894Sgblack@eecs.umich.edu 2846102Sgblack@eecs.umich.edu if (req->isLLSC()) { 28510030SAli.Saidi@ARM.com do_access = TheISA::handleLockedWrite(thread, req, dcachePort.cacheBlockMask); 2865894Sgblack@eecs.umich.edu } else if (req->isCondSwap()) { 2875894Sgblack@eecs.umich.edu assert(res); 2885894Sgblack@eecs.umich.edu req->setExtraData(*res); 2895894Sgblack@eecs.umich.edu } 2905894Sgblack@eecs.umich.edu 2915894Sgblack@eecs.umich.edu if (do_access) { 2925894Sgblack@eecs.umich.edu dcache_pkt = pkt; 2935894Sgblack@eecs.umich.edu handleWritePacket(); 2945894Sgblack@eecs.umich.edu } else { 2955894Sgblack@eecs.umich.edu _status = DcacheWaitResponse; 2965894Sgblack@eecs.umich.edu completeDataAccess(pkt); 2975894Sgblack@eecs.umich.edu } 2985894Sgblack@eecs.umich.edu } 2995894Sgblack@eecs.umich.edu} 3005894Sgblack@eecs.umich.edu 3015894Sgblack@eecs.umich.eduvoid 3026973Stjones1@inf.ed.ac.ukTimingSimpleCPU::sendSplitData(RequestPtr req1, RequestPtr req2, 3036973Stjones1@inf.ed.ac.uk RequestPtr req, uint8_t *data, bool read) 3045894Sgblack@eecs.umich.edu{ 3055894Sgblack@eecs.umich.edu PacketPtr pkt1, pkt2; 3065894Sgblack@eecs.umich.edu buildSplitPacket(pkt1, pkt2, req1, req2, req, data, read); 3075894Sgblack@eecs.umich.edu if (req->getFlags().isSet(Request::NO_ACCESS)) { 3085894Sgblack@eecs.umich.edu assert(!dcache_pkt); 3095894Sgblack@eecs.umich.edu pkt1->makeResponse(); 3105894Sgblack@eecs.umich.edu completeDataAccess(pkt1); 3115894Sgblack@eecs.umich.edu } else if (read) { 3127911Shestness@cs.utexas.edu SplitFragmentSenderState * send_state = 3137911Shestness@cs.utexas.edu dynamic_cast<SplitFragmentSenderState *>(pkt1->senderState); 3145894Sgblack@eecs.umich.edu if (handleReadPacket(pkt1)) { 3155894Sgblack@eecs.umich.edu send_state->clearFromParent(); 3167911Shestness@cs.utexas.edu send_state = dynamic_cast<SplitFragmentSenderState *>( 3177911Shestness@cs.utexas.edu pkt2->senderState); 3185894Sgblack@eecs.umich.edu if (handleReadPacket(pkt2)) { 3195894Sgblack@eecs.umich.edu send_state->clearFromParent(); 3205894Sgblack@eecs.umich.edu } 3215894Sgblack@eecs.umich.edu } 3225894Sgblack@eecs.umich.edu } else { 3235894Sgblack@eecs.umich.edu dcache_pkt = pkt1; 3247911Shestness@cs.utexas.edu SplitFragmentSenderState * send_state = 3257911Shestness@cs.utexas.edu dynamic_cast<SplitFragmentSenderState *>(pkt1->senderState); 3265894Sgblack@eecs.umich.edu if (handleWritePacket()) { 3275894Sgblack@eecs.umich.edu send_state->clearFromParent(); 3285894Sgblack@eecs.umich.edu dcache_pkt = pkt2; 3297911Shestness@cs.utexas.edu send_state = dynamic_cast<SplitFragmentSenderState *>( 3307911Shestness@cs.utexas.edu pkt2->senderState); 3315894Sgblack@eecs.umich.edu if (handleWritePacket()) { 3325894Sgblack@eecs.umich.edu send_state->clearFromParent(); 3335894Sgblack@eecs.umich.edu } 3345894Sgblack@eecs.umich.edu } 3355894Sgblack@eecs.umich.edu } 3365894Sgblack@eecs.umich.edu} 3375894Sgblack@eecs.umich.edu 3385894Sgblack@eecs.umich.eduvoid 33910379Sandreas.hansson@arm.comTimingSimpleCPU::translationFault(const Fault &fault) 3405894Sgblack@eecs.umich.edu{ 3416739Sgblack@eecs.umich.edu // fault may be NoFault in cases where a fault is suppressed, 3426739Sgblack@eecs.umich.edu // for instance prefetches. 34310464SAndreas.Sandberg@ARM.com updateCycleCounts(); 3445894Sgblack@eecs.umich.edu 3455894Sgblack@eecs.umich.edu if (traceData) { 3465894Sgblack@eecs.umich.edu // Since there was a fault, we shouldn't trace this instruction. 3475894Sgblack@eecs.umich.edu delete traceData; 3485894Sgblack@eecs.umich.edu traceData = NULL; 3495744Sgblack@eecs.umich.edu } 3505744Sgblack@eecs.umich.edu 3515894Sgblack@eecs.umich.edu postExecute(); 3525894Sgblack@eecs.umich.edu 3539442SAndreas.Sandberg@ARM.com advanceInst(fault); 3545894Sgblack@eecs.umich.edu} 3555894Sgblack@eecs.umich.edu 3565894Sgblack@eecs.umich.eduvoid 3575894Sgblack@eecs.umich.eduTimingSimpleCPU::buildPacket(PacketPtr &pkt, RequestPtr req, bool read) 3585894Sgblack@eecs.umich.edu{ 35910342SCurtis.Dunham@arm.com pkt = read ? Packet::createRead(req) : Packet::createWrite(req); 3605894Sgblack@eecs.umich.edu} 3615894Sgblack@eecs.umich.edu 3625894Sgblack@eecs.umich.eduvoid 3635894Sgblack@eecs.umich.eduTimingSimpleCPU::buildSplitPacket(PacketPtr &pkt1, PacketPtr &pkt2, 3645894Sgblack@eecs.umich.edu RequestPtr req1, RequestPtr req2, RequestPtr req, 3655894Sgblack@eecs.umich.edu uint8_t *data, bool read) 3665894Sgblack@eecs.umich.edu{ 3675894Sgblack@eecs.umich.edu pkt1 = pkt2 = NULL; 3685894Sgblack@eecs.umich.edu 3698105Sgblack@eecs.umich.edu assert(!req1->isMmappedIpr() && !req2->isMmappedIpr()); 3705744Sgblack@eecs.umich.edu 3715894Sgblack@eecs.umich.edu if (req->getFlags().isSet(Request::NO_ACCESS)) { 3725894Sgblack@eecs.umich.edu buildPacket(pkt1, req, read); 3735894Sgblack@eecs.umich.edu return; 3745894Sgblack@eecs.umich.edu } 3755894Sgblack@eecs.umich.edu 3765894Sgblack@eecs.umich.edu buildPacket(pkt1, req1, read); 3775894Sgblack@eecs.umich.edu buildPacket(pkt2, req2, read); 3785894Sgblack@eecs.umich.edu 3798832SAli.Saidi@ARM.com req->setPhys(req1->getPaddr(), req->getSize(), req1->getFlags(), dataMasterId()); 3808949Sandreas.hansson@arm.com PacketPtr pkt = new Packet(req, pkt1->cmd.responseCommand()); 3815744Sgblack@eecs.umich.edu 3827691SAli.Saidi@ARM.com pkt->dataDynamicArray<uint8_t>(data); 3835744Sgblack@eecs.umich.edu pkt1->dataStatic<uint8_t>(data); 3845744Sgblack@eecs.umich.edu pkt2->dataStatic<uint8_t>(data + req1->getSize()); 3855744Sgblack@eecs.umich.edu 3865744Sgblack@eecs.umich.edu SplitMainSenderState * main_send_state = new SplitMainSenderState; 3875744Sgblack@eecs.umich.edu pkt->senderState = main_send_state; 3885744Sgblack@eecs.umich.edu main_send_state->fragments[0] = pkt1; 3895744Sgblack@eecs.umich.edu main_send_state->fragments[1] = pkt2; 3905744Sgblack@eecs.umich.edu main_send_state->outstanding = 2; 3915744Sgblack@eecs.umich.edu pkt1->senderState = new SplitFragmentSenderState(pkt, 0); 3925744Sgblack@eecs.umich.edu pkt2->senderState = new SplitFragmentSenderState(pkt, 1); 3935744Sgblack@eecs.umich.edu} 3945744Sgblack@eecs.umich.edu 3952623SN/AFault 3968444Sgblack@eecs.umich.eduTimingSimpleCPU::readMem(Addr addr, uint8_t *data, 3978444Sgblack@eecs.umich.edu unsigned size, unsigned flags) 3982623SN/A{ 3995728Sgblack@eecs.umich.edu Fault fault; 4005728Sgblack@eecs.umich.edu const int asid = 0; 4016221Snate@binkert.org const ThreadID tid = 0; 4027720Sgblack@eecs.umich.edu const Addr pc = thread->instAddr(); 4039814Sandreas.hansson@arm.com unsigned block_size = cacheLineSize(); 4046973Stjones1@inf.ed.ac.uk BaseTLB::Mode mode = BaseTLB::Read; 4052623SN/A 4067045Ssteve.reinhardt@amd.com if (traceData) { 4077045Ssteve.reinhardt@amd.com traceData->setAddr(addr); 4087045Ssteve.reinhardt@amd.com } 4097045Ssteve.reinhardt@amd.com 4107520Sgblack@eecs.umich.edu RequestPtr req = new Request(asid, addr, size, 4118832SAli.Saidi@ARM.com flags, dataMasterId(), pc, _cpuId, tid); 4125728Sgblack@eecs.umich.edu 41310024Sdam.sunwoo@arm.com req->taskId(taskId()); 41410024Sdam.sunwoo@arm.com 4157520Sgblack@eecs.umich.edu Addr split_addr = roundDown(addr + size - 1, block_size); 4165744Sgblack@eecs.umich.edu assert(split_addr <= addr || split_addr - addr < block_size); 4175728Sgblack@eecs.umich.edu 4185894Sgblack@eecs.umich.edu _status = DTBWaitResponse; 4195744Sgblack@eecs.umich.edu if (split_addr > addr) { 4205894Sgblack@eecs.umich.edu RequestPtr req1, req2; 4216102Sgblack@eecs.umich.edu assert(!req->isLLSC() && !req->isSwap()); 4225894Sgblack@eecs.umich.edu req->splitOnVaddr(split_addr, req1, req2); 4235894Sgblack@eecs.umich.edu 4246973Stjones1@inf.ed.ac.uk WholeTranslationState *state = 4257520Sgblack@eecs.umich.edu new WholeTranslationState(req, req1, req2, new uint8_t[size], 4266973Stjones1@inf.ed.ac.uk NULL, mode); 4278486Sgblack@eecs.umich.edu DataTranslation<TimingSimpleCPU *> *trans1 = 4288486Sgblack@eecs.umich.edu new DataTranslation<TimingSimpleCPU *>(this, state, 0); 4298486Sgblack@eecs.umich.edu DataTranslation<TimingSimpleCPU *> *trans2 = 4308486Sgblack@eecs.umich.edu new DataTranslation<TimingSimpleCPU *>(this, state, 1); 4316973Stjones1@inf.ed.ac.uk 4326973Stjones1@inf.ed.ac.uk thread->dtb->translateTiming(req1, tc, trans1, mode); 4336973Stjones1@inf.ed.ac.uk thread->dtb->translateTiming(req2, tc, trans2, mode); 4345744Sgblack@eecs.umich.edu } else { 4356973Stjones1@inf.ed.ac.uk WholeTranslationState *state = 4367520Sgblack@eecs.umich.edu new WholeTranslationState(req, new uint8_t[size], NULL, mode); 4378486Sgblack@eecs.umich.edu DataTranslation<TimingSimpleCPU *> *translation 4388486Sgblack@eecs.umich.edu = new DataTranslation<TimingSimpleCPU *>(this, state); 4396973Stjones1@inf.ed.ac.uk thread->dtb->translateTiming(req, tc, translation, mode); 4402623SN/A } 4412623SN/A 4425728Sgblack@eecs.umich.edu return NoFault; 4432623SN/A} 4442623SN/A 4455728Sgblack@eecs.umich.edubool 4465728Sgblack@eecs.umich.eduTimingSimpleCPU::handleWritePacket() 4475728Sgblack@eecs.umich.edu{ 4485728Sgblack@eecs.umich.edu RequestPtr req = dcache_pkt->req; 4498105Sgblack@eecs.umich.edu if (req->isMmappedIpr()) { 4509180Sandreas.hansson@arm.com Cycles delay = TheISA::handleIprWrite(thread->getTC(), dcache_pkt); 4519179Sandreas.hansson@arm.com new IprEvent(dcache_pkt, this, clockEdge(delay)); 4525728Sgblack@eecs.umich.edu _status = DcacheWaitResponse; 4535728Sgblack@eecs.umich.edu dcache_pkt = NULL; 4548975Sandreas.hansson@arm.com } else if (!dcachePort.sendTimingReq(dcache_pkt)) { 4555728Sgblack@eecs.umich.edu _status = DcacheRetry; 4565728Sgblack@eecs.umich.edu } else { 4575728Sgblack@eecs.umich.edu _status = DcacheWaitResponse; 4585728Sgblack@eecs.umich.edu // memory system takes ownership of packet 4595728Sgblack@eecs.umich.edu dcache_pkt = NULL; 4605728Sgblack@eecs.umich.edu } 4615728Sgblack@eecs.umich.edu return dcache_pkt == NULL; 4625728Sgblack@eecs.umich.edu} 4632623SN/A 4642623SN/AFault 4658444Sgblack@eecs.umich.eduTimingSimpleCPU::writeMem(uint8_t *data, unsigned size, 4668444Sgblack@eecs.umich.edu Addr addr, unsigned flags, uint64_t *res) 4672623SN/A{ 4688443Sgblack@eecs.umich.edu uint8_t *newData = new uint8_t[size]; 4695728Sgblack@eecs.umich.edu const int asid = 0; 4706221Snate@binkert.org const ThreadID tid = 0; 4717720Sgblack@eecs.umich.edu const Addr pc = thread->instAddr(); 4729814Sandreas.hansson@arm.com unsigned block_size = cacheLineSize(); 4736973Stjones1@inf.ed.ac.uk BaseTLB::Mode mode = BaseTLB::Write; 4743169Sstever@eecs.umich.edu 47510031SAli.Saidi@ARM.com if (data == NULL) { 47610031SAli.Saidi@ARM.com assert(flags & Request::CACHE_BLOCK_ZERO); 47710031SAli.Saidi@ARM.com // This must be a cache block cleaning request 47810031SAli.Saidi@ARM.com memset(newData, 0, size); 47910031SAli.Saidi@ARM.com } else { 48010031SAli.Saidi@ARM.com memcpy(newData, data, size); 48110031SAli.Saidi@ARM.com } 48210031SAli.Saidi@ARM.com 4837045Ssteve.reinhardt@amd.com if (traceData) { 4847045Ssteve.reinhardt@amd.com traceData->setAddr(addr); 4857045Ssteve.reinhardt@amd.com } 4867045Ssteve.reinhardt@amd.com 4877520Sgblack@eecs.umich.edu RequestPtr req = new Request(asid, addr, size, 4888832SAli.Saidi@ARM.com flags, dataMasterId(), pc, _cpuId, tid); 4895728Sgblack@eecs.umich.edu 49010024Sdam.sunwoo@arm.com req->taskId(taskId()); 49110024Sdam.sunwoo@arm.com 4927520Sgblack@eecs.umich.edu Addr split_addr = roundDown(addr + size - 1, block_size); 4935744Sgblack@eecs.umich.edu assert(split_addr <= addr || split_addr - addr < block_size); 4945728Sgblack@eecs.umich.edu 4955894Sgblack@eecs.umich.edu _status = DTBWaitResponse; 4965744Sgblack@eecs.umich.edu if (split_addr > addr) { 4975894Sgblack@eecs.umich.edu RequestPtr req1, req2; 4986102Sgblack@eecs.umich.edu assert(!req->isLLSC() && !req->isSwap()); 4995894Sgblack@eecs.umich.edu req->splitOnVaddr(split_addr, req1, req2); 5005894Sgblack@eecs.umich.edu 5016973Stjones1@inf.ed.ac.uk WholeTranslationState *state = 5028443Sgblack@eecs.umich.edu new WholeTranslationState(req, req1, req2, newData, res, mode); 5038486Sgblack@eecs.umich.edu DataTranslation<TimingSimpleCPU *> *trans1 = 5048486Sgblack@eecs.umich.edu new DataTranslation<TimingSimpleCPU *>(this, state, 0); 5058486Sgblack@eecs.umich.edu DataTranslation<TimingSimpleCPU *> *trans2 = 5068486Sgblack@eecs.umich.edu new DataTranslation<TimingSimpleCPU *>(this, state, 1); 5076973Stjones1@inf.ed.ac.uk 5086973Stjones1@inf.ed.ac.uk thread->dtb->translateTiming(req1, tc, trans1, mode); 5096973Stjones1@inf.ed.ac.uk thread->dtb->translateTiming(req2, tc, trans2, mode); 5105744Sgblack@eecs.umich.edu } else { 5116973Stjones1@inf.ed.ac.uk WholeTranslationState *state = 5128443Sgblack@eecs.umich.edu new WholeTranslationState(req, newData, res, mode); 5138486Sgblack@eecs.umich.edu DataTranslation<TimingSimpleCPU *> *translation = 5148486Sgblack@eecs.umich.edu new DataTranslation<TimingSimpleCPU *>(this, state); 5156973Stjones1@inf.ed.ac.uk thread->dtb->translateTiming(req, tc, translation, mode); 5162623SN/A } 5172623SN/A 5187045Ssteve.reinhardt@amd.com // Translation faults will be returned via finishTranslation() 5195728Sgblack@eecs.umich.edu return NoFault; 5202623SN/A} 5212623SN/A 5222623SN/A 5232623SN/Avoid 5246973Stjones1@inf.ed.ac.ukTimingSimpleCPU::finishTranslation(WholeTranslationState *state) 5256973Stjones1@inf.ed.ac.uk{ 5269342SAndreas.Sandberg@arm.com _status = BaseSimpleCPU::Running; 5276973Stjones1@inf.ed.ac.uk 5286973Stjones1@inf.ed.ac.uk if (state->getFault() != NoFault) { 5296973Stjones1@inf.ed.ac.uk if (state->isPrefetch()) { 5306973Stjones1@inf.ed.ac.uk state->setNoFault(); 5316973Stjones1@inf.ed.ac.uk } 5327691SAli.Saidi@ARM.com delete [] state->data; 5336973Stjones1@inf.ed.ac.uk state->deleteReqs(); 5346973Stjones1@inf.ed.ac.uk translationFault(state->getFault()); 5356973Stjones1@inf.ed.ac.uk } else { 5366973Stjones1@inf.ed.ac.uk if (!state->isSplit) { 5376973Stjones1@inf.ed.ac.uk sendData(state->mainReq, state->data, state->res, 5386973Stjones1@inf.ed.ac.uk state->mode == BaseTLB::Read); 5396973Stjones1@inf.ed.ac.uk } else { 5406973Stjones1@inf.ed.ac.uk sendSplitData(state->sreqLow, state->sreqHigh, state->mainReq, 5416973Stjones1@inf.ed.ac.uk state->data, state->mode == BaseTLB::Read); 5426973Stjones1@inf.ed.ac.uk } 5436973Stjones1@inf.ed.ac.uk } 5446973Stjones1@inf.ed.ac.uk 5456973Stjones1@inf.ed.ac.uk delete state; 5466973Stjones1@inf.ed.ac.uk} 5476973Stjones1@inf.ed.ac.uk 5486973Stjones1@inf.ed.ac.uk 5496973Stjones1@inf.ed.ac.ukvoid 5502623SN/ATimingSimpleCPU::fetch() 5512623SN/A{ 5525221Ssaidi@eecs.umich.edu DPRINTF(SimpleCPU, "Fetch\n"); 5535221Ssaidi@eecs.umich.edu 5543387Sgblack@eecs.umich.edu if (!curStaticInst || !curStaticInst->isDelayedCommit()) 5553387Sgblack@eecs.umich.edu checkForInterrupts(); 5562631SN/A 5575348Ssaidi@eecs.umich.edu checkPcEventQueue(); 5585348Ssaidi@eecs.umich.edu 5598143SAli.Saidi@ARM.com // We must have just got suspended by a PC event 5608143SAli.Saidi@ARM.com if (_status == Idle) 5618143SAli.Saidi@ARM.com return; 5628143SAli.Saidi@ARM.com 5637720Sgblack@eecs.umich.edu TheISA::PCState pcState = thread->pcState(); 5647720Sgblack@eecs.umich.edu bool needToFetch = !isRomMicroPC(pcState.microPC()) && !curMacroStaticInst; 5652623SN/A 5667720Sgblack@eecs.umich.edu if (needToFetch) { 5679342SAndreas.Sandberg@arm.com _status = BaseSimpleCPU::Running; 5685669Sgblack@eecs.umich.edu Request *ifetch_req = new Request(); 56910024Sdam.sunwoo@arm.com ifetch_req->taskId(taskId()); 5705712Shsul@eecs.umich.edu ifetch_req->setThreadContext(_cpuId, /* thread ID */ 0); 5715894Sgblack@eecs.umich.edu setupFetchRequest(ifetch_req); 5728277SAli.Saidi@ARM.com DPRINTF(SimpleCPU, "Translating address %#x\n", ifetch_req->getVaddr()); 5736023Snate@binkert.org thread->itb->translateTiming(ifetch_req, tc, &fetchTranslation, 5746023Snate@binkert.org BaseTLB::Execute); 5752623SN/A } else { 5765669Sgblack@eecs.umich.edu _status = IcacheWaitResponse; 5775669Sgblack@eecs.umich.edu completeIfetch(NULL); 5785894Sgblack@eecs.umich.edu 57910464SAndreas.Sandberg@ARM.com updateCycleCounts(); 5805894Sgblack@eecs.umich.edu } 5815894Sgblack@eecs.umich.edu} 5825894Sgblack@eecs.umich.edu 5835894Sgblack@eecs.umich.edu 5845894Sgblack@eecs.umich.eduvoid 58510379Sandreas.hansson@arm.comTimingSimpleCPU::sendFetch(const Fault &fault, RequestPtr req, 58610379Sandreas.hansson@arm.com ThreadContext *tc) 5875894Sgblack@eecs.umich.edu{ 5885894Sgblack@eecs.umich.edu if (fault == NoFault) { 5898277SAli.Saidi@ARM.com DPRINTF(SimpleCPU, "Sending fetch for addr %#x(pa: %#x)\n", 5908277SAli.Saidi@ARM.com req->getVaddr(), req->getPaddr()); 5918949Sandreas.hansson@arm.com ifetch_pkt = new Packet(req, MemCmd::ReadReq); 5925894Sgblack@eecs.umich.edu ifetch_pkt->dataStatic(&inst); 5938277SAli.Saidi@ARM.com DPRINTF(SimpleCPU, " -- pkt addr: %#x\n", ifetch_pkt->getAddr()); 5945894Sgblack@eecs.umich.edu 5958975Sandreas.hansson@arm.com if (!icachePort.sendTimingReq(ifetch_pkt)) { 5965894Sgblack@eecs.umich.edu // Need to wait for retry 5975894Sgblack@eecs.umich.edu _status = IcacheRetry; 5985894Sgblack@eecs.umich.edu } else { 5995894Sgblack@eecs.umich.edu // Need to wait for cache to respond 6005894Sgblack@eecs.umich.edu _status = IcacheWaitResponse; 6015894Sgblack@eecs.umich.edu // ownership of packet transferred to memory system 6025894Sgblack@eecs.umich.edu ifetch_pkt = NULL; 6035894Sgblack@eecs.umich.edu } 6045894Sgblack@eecs.umich.edu } else { 6058277SAli.Saidi@ARM.com DPRINTF(SimpleCPU, "Translation of addr %#x faulted\n", req->getVaddr()); 6065894Sgblack@eecs.umich.edu delete req; 6075894Sgblack@eecs.umich.edu // fetch fault: advance directly to next instruction (fault handler) 6089342SAndreas.Sandberg@arm.com _status = BaseSimpleCPU::Running; 6095894Sgblack@eecs.umich.edu advanceInst(fault); 6102623SN/A } 6113222Sktlim@umich.edu 61210464SAndreas.Sandberg@ARM.com updateCycleCounts(); 6132623SN/A} 6142623SN/A 6152623SN/A 6162623SN/Avoid 61710379Sandreas.hansson@arm.comTimingSimpleCPU::advanceInst(const Fault &fault) 6182623SN/A{ 6198276SAli.Saidi@ARM.com if (_status == Faulting) 6208276SAli.Saidi@ARM.com return; 6218276SAli.Saidi@ARM.com 6228276SAli.Saidi@ARM.com if (fault != NoFault) { 6238276SAli.Saidi@ARM.com advancePC(fault); 6248276SAli.Saidi@ARM.com DPRINTF(SimpleCPU, "Fault occured, scheduling fetch event\n"); 6259648Sdam.sunwoo@arm.com reschedule(fetchEvent, clockEdge(), true); 6268276SAli.Saidi@ARM.com _status = Faulting; 6278276SAli.Saidi@ARM.com return; 6288276SAli.Saidi@ARM.com } 6298276SAli.Saidi@ARM.com 6308276SAli.Saidi@ARM.com 6318276SAli.Saidi@ARM.com if (!stayAtPC) 6325726Sgblack@eecs.umich.edu advancePC(fault); 6332623SN/A 6349442SAndreas.Sandberg@ARM.com if (tryCompleteDrain()) 6359442SAndreas.Sandberg@ARM.com return; 6369442SAndreas.Sandberg@ARM.com 6379342SAndreas.Sandberg@arm.com if (_status == BaseSimpleCPU::Running) { 6382631SN/A // kick off fetch of next instruction... callback from icache 6392631SN/A // response will cause that instruction to be executed, 6402631SN/A // keeping the CPU running. 6412631SN/A fetch(); 6422631SN/A } 6432623SN/A} 6442623SN/A 6452623SN/A 6462623SN/Avoid 6473349Sbinkertn@umich.eduTimingSimpleCPU::completeIfetch(PacketPtr pkt) 6482623SN/A{ 6498277SAli.Saidi@ARM.com DPRINTF(SimpleCPU, "Complete ICache Fetch for addr %#x\n", pkt ? 6508277SAli.Saidi@ARM.com pkt->getAddr() : 0); 6518277SAli.Saidi@ARM.com 6522623SN/A // received a response from the icache: execute the received 6532623SN/A // instruction 6545669Sgblack@eecs.umich.edu assert(!pkt || !pkt->isError()); 6552623SN/A assert(_status == IcacheWaitResponse); 6562798Sktlim@umich.edu 6579342SAndreas.Sandberg@arm.com _status = BaseSimpleCPU::Running; 6582644Sstever@eecs.umich.edu 65910464SAndreas.Sandberg@ARM.com updateCycleCounts(); 6603222Sktlim@umich.edu 66110020Smatt.horsnell@ARM.com if (pkt) 66210020Smatt.horsnell@ARM.com pkt->req->setAccessLatency(); 66310020Smatt.horsnell@ARM.com 66410020Smatt.horsnell@ARM.com 6652623SN/A preExecute(); 6667725SAli.Saidi@ARM.com if (curStaticInst && curStaticInst->isMemRef()) { 6672623SN/A // load or store: just send to dcache 6682623SN/A Fault fault = curStaticInst->initiateAcc(this, traceData); 6697945SAli.Saidi@ARM.com 6707945SAli.Saidi@ARM.com // If we're not running now the instruction will complete in a dcache 6717945SAli.Saidi@ARM.com // response callback or the instruction faulted and has started an 6727945SAli.Saidi@ARM.com // ifetch 6739342SAndreas.Sandberg@arm.com if (_status == BaseSimpleCPU::Running) { 6745894Sgblack@eecs.umich.edu if (fault != NoFault && traceData) { 6755001Sgblack@eecs.umich.edu // If there was a fault, we shouldn't trace this instruction. 6765001Sgblack@eecs.umich.edu delete traceData; 6775001Sgblack@eecs.umich.edu traceData = NULL; 6783170Sstever@eecs.umich.edu } 6794998Sgblack@eecs.umich.edu 6802644Sstever@eecs.umich.edu postExecute(); 6815103Ssaidi@eecs.umich.edu // @todo remove me after debugging with legion done 6825103Ssaidi@eecs.umich.edu if (curStaticInst && (!curStaticInst->isMicroop() || 6835103Ssaidi@eecs.umich.edu curStaticInst->isFirstMicroop())) 6845103Ssaidi@eecs.umich.edu instCnt++; 6852644Sstever@eecs.umich.edu advanceInst(fault); 6862644Sstever@eecs.umich.edu } 6875726Sgblack@eecs.umich.edu } else if (curStaticInst) { 6882623SN/A // non-memory instruction: execute completely now 6892623SN/A Fault fault = curStaticInst->execute(this, traceData); 6904998Sgblack@eecs.umich.edu 6914998Sgblack@eecs.umich.edu // keep an instruction count 6924998Sgblack@eecs.umich.edu if (fault == NoFault) 6934998Sgblack@eecs.umich.edu countInst(); 6947655Sali.saidi@arm.com else if (traceData && !DTRACE(ExecFaulting)) { 6955001Sgblack@eecs.umich.edu delete traceData; 6965001Sgblack@eecs.umich.edu traceData = NULL; 6975001Sgblack@eecs.umich.edu } 6984998Sgblack@eecs.umich.edu 6992644Sstever@eecs.umich.edu postExecute(); 7005103Ssaidi@eecs.umich.edu // @todo remove me after debugging with legion done 7015103Ssaidi@eecs.umich.edu if (curStaticInst && (!curStaticInst->isMicroop() || 7025103Ssaidi@eecs.umich.edu curStaticInst->isFirstMicroop())) 7035103Ssaidi@eecs.umich.edu instCnt++; 7042644Sstever@eecs.umich.edu advanceInst(fault); 7055726Sgblack@eecs.umich.edu } else { 7065726Sgblack@eecs.umich.edu advanceInst(NoFault); 7072623SN/A } 7083658Sktlim@umich.edu 7095669Sgblack@eecs.umich.edu if (pkt) { 7105669Sgblack@eecs.umich.edu delete pkt->req; 7115669Sgblack@eecs.umich.edu delete pkt; 7125669Sgblack@eecs.umich.edu } 7132623SN/A} 7142623SN/A 7152948Ssaidi@eecs.umich.eduvoid 7162948Ssaidi@eecs.umich.eduTimingSimpleCPU::IcachePort::ITickEvent::process() 7172948Ssaidi@eecs.umich.edu{ 7182948Ssaidi@eecs.umich.edu cpu->completeIfetch(pkt); 7192948Ssaidi@eecs.umich.edu} 7202623SN/A 7212623SN/Abool 7228975Sandreas.hansson@arm.comTimingSimpleCPU::IcachePort::recvTimingResp(PacketPtr pkt) 7232623SN/A{ 7249165Sandreas.hansson@arm.com DPRINTF(SimpleCPU, "Received timing response %#x\n", pkt->getAddr()); 7259165Sandreas.hansson@arm.com // delay processing of returned data until next CPU clock edge 7269648Sdam.sunwoo@arm.com Tick next_tick = cpu->clockEdge(); 7272948Ssaidi@eecs.umich.edu 7289165Sandreas.hansson@arm.com if (next_tick == curTick()) 7299165Sandreas.hansson@arm.com cpu->completeIfetch(pkt); 7309165Sandreas.hansson@arm.com else 7319165Sandreas.hansson@arm.com tickEvent.schedule(pkt, next_tick); 7328948Sandreas.hansson@arm.com 7334433Ssaidi@eecs.umich.edu return true; 7342623SN/A} 7352623SN/A 7362657Ssaidi@eecs.umich.eduvoid 7372623SN/ATimingSimpleCPU::IcachePort::recvRetry() 7382623SN/A{ 7392623SN/A // we shouldn't get a retry unless we have a packet that we're 7402623SN/A // waiting to transmit 7412623SN/A assert(cpu->ifetch_pkt != NULL); 7422623SN/A assert(cpu->_status == IcacheRetry); 7433349Sbinkertn@umich.edu PacketPtr tmp = cpu->ifetch_pkt; 7448975Sandreas.hansson@arm.com if (sendTimingReq(tmp)) { 7452657Ssaidi@eecs.umich.edu cpu->_status = IcacheWaitResponse; 7462657Ssaidi@eecs.umich.edu cpu->ifetch_pkt = NULL; 7472657Ssaidi@eecs.umich.edu } 7482623SN/A} 7492623SN/A 7502623SN/Avoid 7513349Sbinkertn@umich.eduTimingSimpleCPU::completeDataAccess(PacketPtr pkt) 7522623SN/A{ 7532623SN/A // received a response from the dcache: complete the load or store 7542623SN/A // instruction 7554870Sstever@eecs.umich.edu assert(!pkt->isError()); 7567516Shestness@cs.utexas.edu assert(_status == DcacheWaitResponse || _status == DTBWaitResponse || 7577516Shestness@cs.utexas.edu pkt->req->getFlags().isSet(Request::NO_ACCESS)); 7582623SN/A 75910020Smatt.horsnell@ARM.com pkt->req->setAccessLatency(); 76010464SAndreas.Sandberg@ARM.com 76110464SAndreas.Sandberg@ARM.com updateCycleCounts(); 7623184Srdreslin@umich.edu 7635728Sgblack@eecs.umich.edu if (pkt->senderState) { 7645728Sgblack@eecs.umich.edu SplitFragmentSenderState * send_state = 7655728Sgblack@eecs.umich.edu dynamic_cast<SplitFragmentSenderState *>(pkt->senderState); 7665728Sgblack@eecs.umich.edu assert(send_state); 7675728Sgblack@eecs.umich.edu delete pkt->req; 7685728Sgblack@eecs.umich.edu delete pkt; 7695728Sgblack@eecs.umich.edu PacketPtr big_pkt = send_state->bigPkt; 7705728Sgblack@eecs.umich.edu delete send_state; 7715728Sgblack@eecs.umich.edu 7725728Sgblack@eecs.umich.edu SplitMainSenderState * main_send_state = 7735728Sgblack@eecs.umich.edu dynamic_cast<SplitMainSenderState *>(big_pkt->senderState); 7745728Sgblack@eecs.umich.edu assert(main_send_state); 7755728Sgblack@eecs.umich.edu // Record the fact that this packet is no longer outstanding. 7765728Sgblack@eecs.umich.edu assert(main_send_state->outstanding != 0); 7775728Sgblack@eecs.umich.edu main_send_state->outstanding--; 7785728Sgblack@eecs.umich.edu 7795728Sgblack@eecs.umich.edu if (main_send_state->outstanding) { 7805728Sgblack@eecs.umich.edu return; 7815728Sgblack@eecs.umich.edu } else { 7825728Sgblack@eecs.umich.edu delete main_send_state; 7835728Sgblack@eecs.umich.edu big_pkt->senderState = NULL; 7845728Sgblack@eecs.umich.edu pkt = big_pkt; 7855728Sgblack@eecs.umich.edu } 7865728Sgblack@eecs.umich.edu } 7875728Sgblack@eecs.umich.edu 7889342SAndreas.Sandberg@arm.com _status = BaseSimpleCPU::Running; 7895728Sgblack@eecs.umich.edu 7902623SN/A Fault fault = curStaticInst->completeAcc(pkt, this, traceData); 7912623SN/A 7924998Sgblack@eecs.umich.edu // keep an instruction count 7934998Sgblack@eecs.umich.edu if (fault == NoFault) 7944998Sgblack@eecs.umich.edu countInst(); 7955001Sgblack@eecs.umich.edu else if (traceData) { 7965001Sgblack@eecs.umich.edu // If there was a fault, we shouldn't trace this instruction. 7975001Sgblack@eecs.umich.edu delete traceData; 7985001Sgblack@eecs.umich.edu traceData = NULL; 7995001Sgblack@eecs.umich.edu } 8004998Sgblack@eecs.umich.edu 8012644Sstever@eecs.umich.edu delete pkt->req; 8022644Sstever@eecs.umich.edu delete pkt; 8032644Sstever@eecs.umich.edu 8043184Srdreslin@umich.edu postExecute(); 8053227Sktlim@umich.edu 8062644Sstever@eecs.umich.edu advanceInst(fault); 8072623SN/A} 8082623SN/A 80910030SAli.Saidi@ARM.comvoid 81010464SAndreas.Sandberg@ARM.comTimingSimpleCPU::updateCycleCounts() 81110464SAndreas.Sandberg@ARM.com{ 81210464SAndreas.Sandberg@ARM.com const Cycles delta(curCycle() - previousCycle); 81310464SAndreas.Sandberg@ARM.com 81410464SAndreas.Sandberg@ARM.com numCycles += delta; 81510464SAndreas.Sandberg@ARM.com ppCycles->notify(delta); 81610464SAndreas.Sandberg@ARM.com 81710464SAndreas.Sandberg@ARM.com previousCycle = curCycle(); 81810464SAndreas.Sandberg@ARM.com} 81910464SAndreas.Sandberg@ARM.com 82010464SAndreas.Sandberg@ARM.comvoid 82110030SAli.Saidi@ARM.comTimingSimpleCPU::DcachePort::recvTimingSnoopReq(PacketPtr pkt) 82210030SAli.Saidi@ARM.com{ 82310529Smorr@cs.wisc.edu // X86 ISA: Snooping an invalidation for monitor/mwait 82410529Smorr@cs.wisc.edu if(cpu->getAddrMonitor()->doMonitor(pkt)) { 82510529Smorr@cs.wisc.edu cpu->wakeup(); 82610529Smorr@cs.wisc.edu } 82710030SAli.Saidi@ARM.com TheISA::handleLockedSnoop(cpu->thread, pkt, cacheBlockMask); 82810030SAli.Saidi@ARM.com} 82910030SAli.Saidi@ARM.com 83010529Smorr@cs.wisc.eduvoid 83110529Smorr@cs.wisc.eduTimingSimpleCPU::DcachePort::recvFunctionalSnoop(PacketPtr pkt) 83210529Smorr@cs.wisc.edu{ 83310529Smorr@cs.wisc.edu // X86 ISA: Snooping an invalidation for monitor/mwait 83410529Smorr@cs.wisc.edu if(cpu->getAddrMonitor()->doMonitor(pkt)) { 83510529Smorr@cs.wisc.edu cpu->wakeup(); 83610529Smorr@cs.wisc.edu } 83710529Smorr@cs.wisc.edu} 83810030SAli.Saidi@ARM.com 8392623SN/Abool 8408975Sandreas.hansson@arm.comTimingSimpleCPU::DcachePort::recvTimingResp(PacketPtr pkt) 8412623SN/A{ 8429165Sandreas.hansson@arm.com // delay processing of returned data until next CPU clock edge 8439648Sdam.sunwoo@arm.com Tick next_tick = cpu->clockEdge(); 8442948Ssaidi@eecs.umich.edu 8459165Sandreas.hansson@arm.com if (next_tick == curTick()) { 8469165Sandreas.hansson@arm.com cpu->completeDataAccess(pkt); 8479165Sandreas.hansson@arm.com } else { 8489165Sandreas.hansson@arm.com if (!tickEvent.scheduled()) { 8499165Sandreas.hansson@arm.com tickEvent.schedule(pkt, next_tick); 8505728Sgblack@eecs.umich.edu } else { 8519165Sandreas.hansson@arm.com // In the case of a split transaction and a cache that is 8529165Sandreas.hansson@arm.com // faster than a CPU we could get two responses before 8539165Sandreas.hansson@arm.com // next_tick expires 8549165Sandreas.hansson@arm.com if (!retryEvent.scheduled()) 8559165Sandreas.hansson@arm.com cpu->schedule(retryEvent, next_tick); 8569165Sandreas.hansson@arm.com return false; 8574433Ssaidi@eecs.umich.edu } 8583310Srdreslin@umich.edu } 8598948Sandreas.hansson@arm.com 8604433Ssaidi@eecs.umich.edu return true; 8612948Ssaidi@eecs.umich.edu} 8622948Ssaidi@eecs.umich.edu 8632948Ssaidi@eecs.umich.eduvoid 8642948Ssaidi@eecs.umich.eduTimingSimpleCPU::DcachePort::DTickEvent::process() 8652948Ssaidi@eecs.umich.edu{ 8662630SN/A cpu->completeDataAccess(pkt); 8672623SN/A} 8682623SN/A 8692657Ssaidi@eecs.umich.eduvoid 8702623SN/ATimingSimpleCPU::DcachePort::recvRetry() 8712623SN/A{ 8722623SN/A // we shouldn't get a retry unless we have a packet that we're 8732623SN/A // waiting to transmit 8742623SN/A assert(cpu->dcache_pkt != NULL); 8752623SN/A assert(cpu->_status == DcacheRetry); 8763349Sbinkertn@umich.edu PacketPtr tmp = cpu->dcache_pkt; 8775728Sgblack@eecs.umich.edu if (tmp->senderState) { 8785728Sgblack@eecs.umich.edu // This is a packet from a split access. 8795728Sgblack@eecs.umich.edu SplitFragmentSenderState * send_state = 8805728Sgblack@eecs.umich.edu dynamic_cast<SplitFragmentSenderState *>(tmp->senderState); 8815728Sgblack@eecs.umich.edu assert(send_state); 8825728Sgblack@eecs.umich.edu PacketPtr big_pkt = send_state->bigPkt; 8835728Sgblack@eecs.umich.edu 8845728Sgblack@eecs.umich.edu SplitMainSenderState * main_send_state = 8855728Sgblack@eecs.umich.edu dynamic_cast<SplitMainSenderState *>(big_pkt->senderState); 8865728Sgblack@eecs.umich.edu assert(main_send_state); 8875728Sgblack@eecs.umich.edu 8888975Sandreas.hansson@arm.com if (sendTimingReq(tmp)) { 8895728Sgblack@eecs.umich.edu // If we were able to send without retrying, record that fact 8905728Sgblack@eecs.umich.edu // and try sending the other fragment. 8915728Sgblack@eecs.umich.edu send_state->clearFromParent(); 8925728Sgblack@eecs.umich.edu int other_index = main_send_state->getPendingFragment(); 8935728Sgblack@eecs.umich.edu if (other_index > 0) { 8945728Sgblack@eecs.umich.edu tmp = main_send_state->fragments[other_index]; 8955728Sgblack@eecs.umich.edu cpu->dcache_pkt = tmp; 8965728Sgblack@eecs.umich.edu if ((big_pkt->isRead() && cpu->handleReadPacket(tmp)) || 8975728Sgblack@eecs.umich.edu (big_pkt->isWrite() && cpu->handleWritePacket())) { 8985728Sgblack@eecs.umich.edu main_send_state->fragments[other_index] = NULL; 8995728Sgblack@eecs.umich.edu } 9005728Sgblack@eecs.umich.edu } else { 9015728Sgblack@eecs.umich.edu cpu->_status = DcacheWaitResponse; 9025728Sgblack@eecs.umich.edu // memory system takes ownership of packet 9035728Sgblack@eecs.umich.edu cpu->dcache_pkt = NULL; 9045728Sgblack@eecs.umich.edu } 9055728Sgblack@eecs.umich.edu } 9068975Sandreas.hansson@arm.com } else if (sendTimingReq(tmp)) { 9072657Ssaidi@eecs.umich.edu cpu->_status = DcacheWaitResponse; 9083170Sstever@eecs.umich.edu // memory system takes ownership of packet 9092657Ssaidi@eecs.umich.edu cpu->dcache_pkt = NULL; 9102657Ssaidi@eecs.umich.edu } 9112623SN/A} 9122623SN/A 9135606Snate@binkert.orgTimingSimpleCPU::IprEvent::IprEvent(Packet *_pkt, TimingSimpleCPU *_cpu, 9145606Snate@binkert.org Tick t) 9155606Snate@binkert.org : pkt(_pkt), cpu(_cpu) 9165103Ssaidi@eecs.umich.edu{ 9175606Snate@binkert.org cpu->schedule(this, t); 9185103Ssaidi@eecs.umich.edu} 9195103Ssaidi@eecs.umich.edu 9205103Ssaidi@eecs.umich.eduvoid 9215103Ssaidi@eecs.umich.eduTimingSimpleCPU::IprEvent::process() 9225103Ssaidi@eecs.umich.edu{ 9235103Ssaidi@eecs.umich.edu cpu->completeDataAccess(pkt); 9245103Ssaidi@eecs.umich.edu} 9255103Ssaidi@eecs.umich.edu 9265103Ssaidi@eecs.umich.educonst char * 9275336Shines@cs.fsu.eduTimingSimpleCPU::IprEvent::description() const 9285103Ssaidi@eecs.umich.edu{ 9295103Ssaidi@eecs.umich.edu return "Timing Simple CPU Delay IPR event"; 9305103Ssaidi@eecs.umich.edu} 9315103Ssaidi@eecs.umich.edu 9322623SN/A 9335315Sstever@gmail.comvoid 9345315Sstever@gmail.comTimingSimpleCPU::printAddr(Addr a) 9355315Sstever@gmail.com{ 9365315Sstever@gmail.com dcachePort.printAddr(a); 9375315Sstever@gmail.com} 9385315Sstever@gmail.com 9395315Sstever@gmail.com 9402623SN/A//////////////////////////////////////////////////////////////////////// 9412623SN/A// 9422623SN/A// TimingSimpleCPU Simulation Object 9432623SN/A// 9444762Snate@binkert.orgTimingSimpleCPU * 9454762Snate@binkert.orgTimingSimpleCPUParams::create() 9462623SN/A{ 9475529Snate@binkert.org numThreads = 1; 9488779Sgblack@eecs.umich.edu if (!FullSystem && workload.size() != 1) 9494762Snate@binkert.org panic("only one workload allowed"); 9505529Snate@binkert.org return new TimingSimpleCPU(this); 9512623SN/A} 952