timing.cc revision 10407
12623SN/A/* 210030SAli.Saidi@ARM.com * Copyright (c) 2010-2013 ARM Limited 37725SAli.Saidi@ARM.com * All rights reserved 47725SAli.Saidi@ARM.com * 57725SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall 67725SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 77725SAli.Saidi@ARM.com * property including but not limited to intellectual property relating 87725SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software 97725SAli.Saidi@ARM.com * licensed hereunder. You may use the software subject to the license 107725SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated 117725SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software, 127725SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form. 137725SAli.Saidi@ARM.com * 142623SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 152623SN/A * All rights reserved. 162623SN/A * 172623SN/A * Redistribution and use in source and binary forms, with or without 182623SN/A * modification, are permitted provided that the following conditions are 192623SN/A * met: redistributions of source code must retain the above copyright 202623SN/A * notice, this list of conditions and the following disclaimer; 212623SN/A * redistributions in binary form must reproduce the above copyright 222623SN/A * notice, this list of conditions and the following disclaimer in the 232623SN/A * documentation and/or other materials provided with the distribution; 242623SN/A * neither the name of the copyright holders nor the names of its 252623SN/A * contributors may be used to endorse or promote products derived from 262623SN/A * this software without specific prior written permission. 272623SN/A * 282623SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292623SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302623SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312623SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322623SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332623SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342623SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352623SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362623SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372623SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382623SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392665Ssaidi@eecs.umich.edu * 402665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 412623SN/A */ 422623SN/A 433170Sstever@eecs.umich.edu#include "arch/locked_mem.hh" 448105Sgblack@eecs.umich.edu#include "arch/mmapped_ipr.hh" 452623SN/A#include "arch/utility.hh" 464040Ssaidi@eecs.umich.edu#include "base/bigint.hh" 476658Snate@binkert.org#include "config/the_isa.hh" 488229Snate@binkert.org#include "cpu/simple/timing.hh" 492623SN/A#include "cpu/exetrace.hh" 508232Snate@binkert.org#include "debug/Config.hh" 519152Satgutier@umich.edu#include "debug/Drain.hh" 528232Snate@binkert.org#include "debug/ExecFaulting.hh" 538232Snate@binkert.org#include "debug/SimpleCPU.hh" 543348Sbinkertn@umich.edu#include "mem/packet.hh" 553348Sbinkertn@umich.edu#include "mem/packet_access.hh" 564762Snate@binkert.org#include "params/TimingSimpleCPU.hh" 577678Sgblack@eecs.umich.edu#include "sim/faults.hh" 588779Sgblack@eecs.umich.edu#include "sim/full_system.hh" 592901Ssaidi@eecs.umich.edu#include "sim/system.hh" 602623SN/A 612623SN/Ausing namespace std; 622623SN/Ausing namespace TheISA; 632623SN/A 642623SN/Avoid 652623SN/ATimingSimpleCPU::init() 662623SN/A{ 672623SN/A BaseCPU::init(); 688921Sandreas.hansson@arm.com 698921Sandreas.hansson@arm.com // Initialise the ThreadContext's memory proxies 708921Sandreas.hansson@arm.com tcBase()->initMemProxies(tcBase()); 718921Sandreas.hansson@arm.com 729433SAndreas.Sandberg@ARM.com if (FullSystem && !params()->switched_out) { 738779Sgblack@eecs.umich.edu for (int i = 0; i < threadContexts.size(); ++i) { 748779Sgblack@eecs.umich.edu ThreadContext *tc = threadContexts[i]; 758779Sgblack@eecs.umich.edu // initialize CPU, including PC 768779Sgblack@eecs.umich.edu TheISA::initCPU(tc, _cpuId); 778779Sgblack@eecs.umich.edu } 782623SN/A } 792623SN/A} 802623SN/A 812623SN/Avoid 828707Sandreas.hansson@arm.comTimingSimpleCPU::TimingCPUPort::TickEvent::schedule(PacketPtr _pkt, Tick t) 832948Ssaidi@eecs.umich.edu{ 842948Ssaidi@eecs.umich.edu pkt = _pkt; 855606Snate@binkert.org cpu->schedule(this, t); 862948Ssaidi@eecs.umich.edu} 872948Ssaidi@eecs.umich.edu 885529Snate@binkert.orgTimingSimpleCPU::TimingSimpleCPU(TimingSimpleCPUParams *p) 898707Sandreas.hansson@arm.com : BaseSimpleCPU(p), fetchTranslation(this), icachePort(this), 909179Sandreas.hansson@arm.com dcachePort(this), ifetch_pkt(NULL), dcache_pkt(NULL), previousCycle(0), 919442SAndreas.Sandberg@ARM.com fetchEvent(this), drainManager(NULL) 922623SN/A{ 932623SN/A _status = Idle; 943647Srdreslin@umich.edu 957897Shestness@cs.utexas.edu system->totalNumInsts = 0; 962623SN/A} 972623SN/A 982623SN/A 9910030SAli.Saidi@ARM.com 1002623SN/ATimingSimpleCPU::~TimingSimpleCPU() 1012623SN/A{ 1022623SN/A} 1032623SN/A 1042901Ssaidi@eecs.umich.eduunsigned int 1059342SAndreas.Sandberg@arm.comTimingSimpleCPU::drain(DrainManager *drain_manager) 1062798Sktlim@umich.edu{ 1079448SAndreas.Sandberg@ARM.com assert(!drainManager); 1089448SAndreas.Sandberg@ARM.com if (switchedOut()) 1099448SAndreas.Sandberg@ARM.com return 0; 1109448SAndreas.Sandberg@ARM.com 1119342SAndreas.Sandberg@arm.com if (_status == Idle || 1129448SAndreas.Sandberg@ARM.com (_status == BaseSimpleCPU::Running && isDrained())) { 1139442SAndreas.Sandberg@ARM.com DPRINTF(Drain, "No need to drain.\n"); 1142901Ssaidi@eecs.umich.edu return 0; 1152798Sktlim@umich.edu } else { 1169342SAndreas.Sandberg@arm.com drainManager = drain_manager; 1179442SAndreas.Sandberg@ARM.com DPRINTF(Drain, "Requesting drain: %s\n", pcState()); 1189442SAndreas.Sandberg@ARM.com 1199442SAndreas.Sandberg@ARM.com // The fetch event can become descheduled if a drain didn't 1209442SAndreas.Sandberg@ARM.com // succeed on the first attempt. We need to reschedule it if 1219442SAndreas.Sandberg@ARM.com // the CPU is waiting for a microcode routine to complete. 1229448SAndreas.Sandberg@ARM.com if (_status == BaseSimpleCPU::Running && !fetchEvent.scheduled()) 1239648Sdam.sunwoo@arm.com schedule(fetchEvent, clockEdge()); 1249442SAndreas.Sandberg@ARM.com 1252901Ssaidi@eecs.umich.edu return 1; 1262798Sktlim@umich.edu } 1272623SN/A} 1282623SN/A 1292623SN/Avoid 1309342SAndreas.Sandberg@arm.comTimingSimpleCPU::drainResume() 1312623SN/A{ 1329442SAndreas.Sandberg@ARM.com assert(!fetchEvent.scheduled()); 1339448SAndreas.Sandberg@ARM.com assert(!drainManager); 1349448SAndreas.Sandberg@ARM.com if (switchedOut()) 1359448SAndreas.Sandberg@ARM.com return; 1369442SAndreas.Sandberg@ARM.com 1375221Ssaidi@eecs.umich.edu DPRINTF(SimpleCPU, "Resume\n"); 1389523SAndreas.Sandberg@ARM.com verifyMemoryMode(); 1393201Shsul@eecs.umich.edu 1409448SAndreas.Sandberg@ARM.com assert(!threadContexts.empty()); 1419448SAndreas.Sandberg@ARM.com if (threadContexts.size() > 1) 1429448SAndreas.Sandberg@ARM.com fatal("The timing CPU only supports one thread.\n"); 1439448SAndreas.Sandberg@ARM.com 1449448SAndreas.Sandberg@ARM.com if (thread->status() == ThreadContext::Active) { 1455710Scws3k@cs.virginia.edu schedule(fetchEvent, nextCycle()); 1469448SAndreas.Sandberg@ARM.com _status = BaseSimpleCPU::Running; 1479837Slena@cs.wisc,edu notIdleFraction = 1; 1489448SAndreas.Sandberg@ARM.com } else { 1499448SAndreas.Sandberg@ARM.com _status = BaseSimpleCPU::Idle; 1509837Slena@cs.wisc,edu notIdleFraction = 0; 1512623SN/A } 1529442SAndreas.Sandberg@ARM.com} 1532798Sktlim@umich.edu 1549442SAndreas.Sandberg@ARM.combool 1559442SAndreas.Sandberg@ARM.comTimingSimpleCPU::tryCompleteDrain() 1569442SAndreas.Sandberg@ARM.com{ 1579442SAndreas.Sandberg@ARM.com if (!drainManager) 1589442SAndreas.Sandberg@ARM.com return false; 1599442SAndreas.Sandberg@ARM.com 1609442SAndreas.Sandberg@ARM.com DPRINTF(Drain, "tryCompleteDrain: %s\n", pcState()); 1619442SAndreas.Sandberg@ARM.com if (!isDrained()) 1629442SAndreas.Sandberg@ARM.com return false; 1639442SAndreas.Sandberg@ARM.com 1649442SAndreas.Sandberg@ARM.com DPRINTF(Drain, "CPU done draining, processing drain event\n"); 1659442SAndreas.Sandberg@ARM.com drainManager->signalDrainDone(); 1669442SAndreas.Sandberg@ARM.com drainManager = NULL; 1679442SAndreas.Sandberg@ARM.com 1689442SAndreas.Sandberg@ARM.com return true; 1692798Sktlim@umich.edu} 1702798Sktlim@umich.edu 1712798Sktlim@umich.eduvoid 1722798Sktlim@umich.eduTimingSimpleCPU::switchOut() 1732798Sktlim@umich.edu{ 1749429SAndreas.Sandberg@ARM.com BaseSimpleCPU::switchOut(); 1759429SAndreas.Sandberg@ARM.com 1769442SAndreas.Sandberg@ARM.com assert(!fetchEvent.scheduled()); 1779342SAndreas.Sandberg@arm.com assert(_status == BaseSimpleCPU::Running || _status == Idle); 1789442SAndreas.Sandberg@ARM.com assert(!stayAtPC); 1799442SAndreas.Sandberg@ARM.com assert(microPC() == 0); 1809442SAndreas.Sandberg@ARM.com 1819179Sandreas.hansson@arm.com numCycles += curCycle() - previousCycle; 1822623SN/A} 1832623SN/A 1842623SN/A 1852623SN/Avoid 1862623SN/ATimingSimpleCPU::takeOverFrom(BaseCPU *oldCPU) 1872623SN/A{ 1889429SAndreas.Sandberg@ARM.com BaseSimpleCPU::takeOverFrom(oldCPU); 1892623SN/A 1909179Sandreas.hansson@arm.com previousCycle = curCycle(); 1912623SN/A} 1922623SN/A 1939523SAndreas.Sandberg@ARM.comvoid 1949523SAndreas.Sandberg@ARM.comTimingSimpleCPU::verifyMemoryMode() const 1959523SAndreas.Sandberg@ARM.com{ 1969524SAndreas.Sandberg@ARM.com if (!system->isTimingMode()) { 1979523SAndreas.Sandberg@ARM.com fatal("The timing CPU requires the memory system to be in " 1989523SAndreas.Sandberg@ARM.com "'timing' mode.\n"); 1999523SAndreas.Sandberg@ARM.com } 2009523SAndreas.Sandberg@ARM.com} 2012623SN/A 2022623SN/Avoid 20310407Smitch.hayenga@arm.comTimingSimpleCPU::activateContext(ThreadID thread_num) 2042623SN/A{ 20510407Smitch.hayenga@arm.com DPRINTF(SimpleCPU, "ActivateContext %d\n", thread_num); 2065221Ssaidi@eecs.umich.edu 2072623SN/A assert(thread_num == 0); 2082683Sktlim@umich.edu assert(thread); 2092623SN/A 2102623SN/A assert(_status == Idle); 2112623SN/A 2129837Slena@cs.wisc,edu notIdleFraction = 1; 2139342SAndreas.Sandberg@arm.com _status = BaseSimpleCPU::Running; 2143686Sktlim@umich.edu 2152623SN/A // kick things off by initiating the fetch of the next instruction 21610407Smitch.hayenga@arm.com schedule(fetchEvent, clockEdge(Cycles(0))); 2172623SN/A} 2182623SN/A 2192623SN/A 2202623SN/Avoid 2218737Skoansin.tan@gmail.comTimingSimpleCPU::suspendContext(ThreadID thread_num) 2222623SN/A{ 2235221Ssaidi@eecs.umich.edu DPRINTF(SimpleCPU, "SuspendContext %d\n", thread_num); 2245221Ssaidi@eecs.umich.edu 2252623SN/A assert(thread_num == 0); 2262683Sktlim@umich.edu assert(thread); 2272623SN/A 2286043Sgblack@eecs.umich.edu if (_status == Idle) 2296043Sgblack@eecs.umich.edu return; 2306043Sgblack@eecs.umich.edu 2319342SAndreas.Sandberg@arm.com assert(_status == BaseSimpleCPU::Running); 2322623SN/A 2332644Sstever@eecs.umich.edu // just change status to Idle... if status != Running, 2342644Sstever@eecs.umich.edu // completeInst() will not initiate fetch of next instruction. 2352623SN/A 2369837Slena@cs.wisc,edu notIdleFraction = 0; 2372623SN/A _status = Idle; 2382623SN/A} 2392623SN/A 2405728Sgblack@eecs.umich.edubool 2415728Sgblack@eecs.umich.eduTimingSimpleCPU::handleReadPacket(PacketPtr pkt) 2425728Sgblack@eecs.umich.edu{ 2435728Sgblack@eecs.umich.edu RequestPtr req = pkt->req; 2448105Sgblack@eecs.umich.edu if (req->isMmappedIpr()) { 2459180Sandreas.hansson@arm.com Cycles delay = TheISA::handleIprRead(thread->getTC(), pkt); 2469179Sandreas.hansson@arm.com new IprEvent(pkt, this, clockEdge(delay)); 2475728Sgblack@eecs.umich.edu _status = DcacheWaitResponse; 2485728Sgblack@eecs.umich.edu dcache_pkt = NULL; 2498975Sandreas.hansson@arm.com } else if (!dcachePort.sendTimingReq(pkt)) { 2505728Sgblack@eecs.umich.edu _status = DcacheRetry; 2515728Sgblack@eecs.umich.edu dcache_pkt = pkt; 2525728Sgblack@eecs.umich.edu } else { 2535728Sgblack@eecs.umich.edu _status = DcacheWaitResponse; 2545728Sgblack@eecs.umich.edu // memory system takes ownership of packet 2555728Sgblack@eecs.umich.edu dcache_pkt = NULL; 2565728Sgblack@eecs.umich.edu } 2575728Sgblack@eecs.umich.edu return dcache_pkt == NULL; 2585728Sgblack@eecs.umich.edu} 2592623SN/A 2605894Sgblack@eecs.umich.eduvoid 2616973Stjones1@inf.ed.ac.ukTimingSimpleCPU::sendData(RequestPtr req, uint8_t *data, uint64_t *res, 2626973Stjones1@inf.ed.ac.uk bool read) 2635744Sgblack@eecs.umich.edu{ 2645894Sgblack@eecs.umich.edu PacketPtr pkt; 2655894Sgblack@eecs.umich.edu buildPacket(pkt, req, read); 2667691SAli.Saidi@ARM.com pkt->dataDynamicArray<uint8_t>(data); 2675894Sgblack@eecs.umich.edu if (req->getFlags().isSet(Request::NO_ACCESS)) { 2685894Sgblack@eecs.umich.edu assert(!dcache_pkt); 2695894Sgblack@eecs.umich.edu pkt->makeResponse(); 2705894Sgblack@eecs.umich.edu completeDataAccess(pkt); 2715894Sgblack@eecs.umich.edu } else if (read) { 2725894Sgblack@eecs.umich.edu handleReadPacket(pkt); 2735894Sgblack@eecs.umich.edu } else { 2745894Sgblack@eecs.umich.edu bool do_access = true; // flag to suppress cache access 2755894Sgblack@eecs.umich.edu 2766102Sgblack@eecs.umich.edu if (req->isLLSC()) { 27710030SAli.Saidi@ARM.com do_access = TheISA::handleLockedWrite(thread, req, dcachePort.cacheBlockMask); 2785894Sgblack@eecs.umich.edu } else if (req->isCondSwap()) { 2795894Sgblack@eecs.umich.edu assert(res); 2805894Sgblack@eecs.umich.edu req->setExtraData(*res); 2815894Sgblack@eecs.umich.edu } 2825894Sgblack@eecs.umich.edu 2835894Sgblack@eecs.umich.edu if (do_access) { 2845894Sgblack@eecs.umich.edu dcache_pkt = pkt; 2855894Sgblack@eecs.umich.edu handleWritePacket(); 2865894Sgblack@eecs.umich.edu } else { 2875894Sgblack@eecs.umich.edu _status = DcacheWaitResponse; 2885894Sgblack@eecs.umich.edu completeDataAccess(pkt); 2895894Sgblack@eecs.umich.edu } 2905894Sgblack@eecs.umich.edu } 2915894Sgblack@eecs.umich.edu} 2925894Sgblack@eecs.umich.edu 2935894Sgblack@eecs.umich.eduvoid 2946973Stjones1@inf.ed.ac.ukTimingSimpleCPU::sendSplitData(RequestPtr req1, RequestPtr req2, 2956973Stjones1@inf.ed.ac.uk RequestPtr req, uint8_t *data, bool read) 2965894Sgblack@eecs.umich.edu{ 2975894Sgblack@eecs.umich.edu PacketPtr pkt1, pkt2; 2985894Sgblack@eecs.umich.edu buildSplitPacket(pkt1, pkt2, req1, req2, req, data, read); 2995894Sgblack@eecs.umich.edu if (req->getFlags().isSet(Request::NO_ACCESS)) { 3005894Sgblack@eecs.umich.edu assert(!dcache_pkt); 3015894Sgblack@eecs.umich.edu pkt1->makeResponse(); 3025894Sgblack@eecs.umich.edu completeDataAccess(pkt1); 3035894Sgblack@eecs.umich.edu } else if (read) { 3047911Shestness@cs.utexas.edu SplitFragmentSenderState * send_state = 3057911Shestness@cs.utexas.edu dynamic_cast<SplitFragmentSenderState *>(pkt1->senderState); 3065894Sgblack@eecs.umich.edu if (handleReadPacket(pkt1)) { 3075894Sgblack@eecs.umich.edu send_state->clearFromParent(); 3087911Shestness@cs.utexas.edu send_state = dynamic_cast<SplitFragmentSenderState *>( 3097911Shestness@cs.utexas.edu pkt2->senderState); 3105894Sgblack@eecs.umich.edu if (handleReadPacket(pkt2)) { 3115894Sgblack@eecs.umich.edu send_state->clearFromParent(); 3125894Sgblack@eecs.umich.edu } 3135894Sgblack@eecs.umich.edu } 3145894Sgblack@eecs.umich.edu } else { 3155894Sgblack@eecs.umich.edu dcache_pkt = pkt1; 3167911Shestness@cs.utexas.edu SplitFragmentSenderState * send_state = 3177911Shestness@cs.utexas.edu dynamic_cast<SplitFragmentSenderState *>(pkt1->senderState); 3185894Sgblack@eecs.umich.edu if (handleWritePacket()) { 3195894Sgblack@eecs.umich.edu send_state->clearFromParent(); 3205894Sgblack@eecs.umich.edu dcache_pkt = pkt2; 3217911Shestness@cs.utexas.edu send_state = dynamic_cast<SplitFragmentSenderState *>( 3227911Shestness@cs.utexas.edu pkt2->senderState); 3235894Sgblack@eecs.umich.edu if (handleWritePacket()) { 3245894Sgblack@eecs.umich.edu send_state->clearFromParent(); 3255894Sgblack@eecs.umich.edu } 3265894Sgblack@eecs.umich.edu } 3275894Sgblack@eecs.umich.edu } 3285894Sgblack@eecs.umich.edu} 3295894Sgblack@eecs.umich.edu 3305894Sgblack@eecs.umich.eduvoid 33110379Sandreas.hansson@arm.comTimingSimpleCPU::translationFault(const Fault &fault) 3325894Sgblack@eecs.umich.edu{ 3336739Sgblack@eecs.umich.edu // fault may be NoFault in cases where a fault is suppressed, 3346739Sgblack@eecs.umich.edu // for instance prefetches. 3359179Sandreas.hansson@arm.com numCycles += curCycle() - previousCycle; 3369179Sandreas.hansson@arm.com previousCycle = curCycle(); 3375894Sgblack@eecs.umich.edu 3385894Sgblack@eecs.umich.edu if (traceData) { 3395894Sgblack@eecs.umich.edu // Since there was a fault, we shouldn't trace this instruction. 3405894Sgblack@eecs.umich.edu delete traceData; 3415894Sgblack@eecs.umich.edu traceData = NULL; 3425744Sgblack@eecs.umich.edu } 3435744Sgblack@eecs.umich.edu 3445894Sgblack@eecs.umich.edu postExecute(); 3455894Sgblack@eecs.umich.edu 3469442SAndreas.Sandberg@ARM.com advanceInst(fault); 3475894Sgblack@eecs.umich.edu} 3485894Sgblack@eecs.umich.edu 3495894Sgblack@eecs.umich.eduvoid 3505894Sgblack@eecs.umich.eduTimingSimpleCPU::buildPacket(PacketPtr &pkt, RequestPtr req, bool read) 3515894Sgblack@eecs.umich.edu{ 35210342SCurtis.Dunham@arm.com pkt = read ? Packet::createRead(req) : Packet::createWrite(req); 3535894Sgblack@eecs.umich.edu} 3545894Sgblack@eecs.umich.edu 3555894Sgblack@eecs.umich.eduvoid 3565894Sgblack@eecs.umich.eduTimingSimpleCPU::buildSplitPacket(PacketPtr &pkt1, PacketPtr &pkt2, 3575894Sgblack@eecs.umich.edu RequestPtr req1, RequestPtr req2, RequestPtr req, 3585894Sgblack@eecs.umich.edu uint8_t *data, bool read) 3595894Sgblack@eecs.umich.edu{ 3605894Sgblack@eecs.umich.edu pkt1 = pkt2 = NULL; 3615894Sgblack@eecs.umich.edu 3628105Sgblack@eecs.umich.edu assert(!req1->isMmappedIpr() && !req2->isMmappedIpr()); 3635744Sgblack@eecs.umich.edu 3645894Sgblack@eecs.umich.edu if (req->getFlags().isSet(Request::NO_ACCESS)) { 3655894Sgblack@eecs.umich.edu buildPacket(pkt1, req, read); 3665894Sgblack@eecs.umich.edu return; 3675894Sgblack@eecs.umich.edu } 3685894Sgblack@eecs.umich.edu 3695894Sgblack@eecs.umich.edu buildPacket(pkt1, req1, read); 3705894Sgblack@eecs.umich.edu buildPacket(pkt2, req2, read); 3715894Sgblack@eecs.umich.edu 3728832SAli.Saidi@ARM.com req->setPhys(req1->getPaddr(), req->getSize(), req1->getFlags(), dataMasterId()); 3738949Sandreas.hansson@arm.com PacketPtr pkt = new Packet(req, pkt1->cmd.responseCommand()); 3745744Sgblack@eecs.umich.edu 3757691SAli.Saidi@ARM.com pkt->dataDynamicArray<uint8_t>(data); 3765744Sgblack@eecs.umich.edu pkt1->dataStatic<uint8_t>(data); 3775744Sgblack@eecs.umich.edu pkt2->dataStatic<uint8_t>(data + req1->getSize()); 3785744Sgblack@eecs.umich.edu 3795744Sgblack@eecs.umich.edu SplitMainSenderState * main_send_state = new SplitMainSenderState; 3805744Sgblack@eecs.umich.edu pkt->senderState = main_send_state; 3815744Sgblack@eecs.umich.edu main_send_state->fragments[0] = pkt1; 3825744Sgblack@eecs.umich.edu main_send_state->fragments[1] = pkt2; 3835744Sgblack@eecs.umich.edu main_send_state->outstanding = 2; 3845744Sgblack@eecs.umich.edu pkt1->senderState = new SplitFragmentSenderState(pkt, 0); 3855744Sgblack@eecs.umich.edu pkt2->senderState = new SplitFragmentSenderState(pkt, 1); 3865744Sgblack@eecs.umich.edu} 3875744Sgblack@eecs.umich.edu 3882623SN/AFault 3898444Sgblack@eecs.umich.eduTimingSimpleCPU::readMem(Addr addr, uint8_t *data, 3908444Sgblack@eecs.umich.edu unsigned size, unsigned flags) 3912623SN/A{ 3925728Sgblack@eecs.umich.edu Fault fault; 3935728Sgblack@eecs.umich.edu const int asid = 0; 3946221Snate@binkert.org const ThreadID tid = 0; 3957720Sgblack@eecs.umich.edu const Addr pc = thread->instAddr(); 3969814Sandreas.hansson@arm.com unsigned block_size = cacheLineSize(); 3976973Stjones1@inf.ed.ac.uk BaseTLB::Mode mode = BaseTLB::Read; 3982623SN/A 3997045Ssteve.reinhardt@amd.com if (traceData) { 4007045Ssteve.reinhardt@amd.com traceData->setAddr(addr); 4017045Ssteve.reinhardt@amd.com } 4027045Ssteve.reinhardt@amd.com 4037520Sgblack@eecs.umich.edu RequestPtr req = new Request(asid, addr, size, 4048832SAli.Saidi@ARM.com flags, dataMasterId(), pc, _cpuId, tid); 4055728Sgblack@eecs.umich.edu 40610024Sdam.sunwoo@arm.com req->taskId(taskId()); 40710024Sdam.sunwoo@arm.com 4087520Sgblack@eecs.umich.edu Addr split_addr = roundDown(addr + size - 1, block_size); 4095744Sgblack@eecs.umich.edu assert(split_addr <= addr || split_addr - addr < block_size); 4105728Sgblack@eecs.umich.edu 4115894Sgblack@eecs.umich.edu _status = DTBWaitResponse; 4125744Sgblack@eecs.umich.edu if (split_addr > addr) { 4135894Sgblack@eecs.umich.edu RequestPtr req1, req2; 4146102Sgblack@eecs.umich.edu assert(!req->isLLSC() && !req->isSwap()); 4155894Sgblack@eecs.umich.edu req->splitOnVaddr(split_addr, req1, req2); 4165894Sgblack@eecs.umich.edu 4176973Stjones1@inf.ed.ac.uk WholeTranslationState *state = 4187520Sgblack@eecs.umich.edu new WholeTranslationState(req, req1, req2, new uint8_t[size], 4196973Stjones1@inf.ed.ac.uk NULL, mode); 4208486Sgblack@eecs.umich.edu DataTranslation<TimingSimpleCPU *> *trans1 = 4218486Sgblack@eecs.umich.edu new DataTranslation<TimingSimpleCPU *>(this, state, 0); 4228486Sgblack@eecs.umich.edu DataTranslation<TimingSimpleCPU *> *trans2 = 4238486Sgblack@eecs.umich.edu new DataTranslation<TimingSimpleCPU *>(this, state, 1); 4246973Stjones1@inf.ed.ac.uk 4256973Stjones1@inf.ed.ac.uk thread->dtb->translateTiming(req1, tc, trans1, mode); 4266973Stjones1@inf.ed.ac.uk thread->dtb->translateTiming(req2, tc, trans2, mode); 4275744Sgblack@eecs.umich.edu } else { 4286973Stjones1@inf.ed.ac.uk WholeTranslationState *state = 4297520Sgblack@eecs.umich.edu new WholeTranslationState(req, new uint8_t[size], NULL, mode); 4308486Sgblack@eecs.umich.edu DataTranslation<TimingSimpleCPU *> *translation 4318486Sgblack@eecs.umich.edu = new DataTranslation<TimingSimpleCPU *>(this, state); 4326973Stjones1@inf.ed.ac.uk thread->dtb->translateTiming(req, tc, translation, mode); 4332623SN/A } 4342623SN/A 4355728Sgblack@eecs.umich.edu return NoFault; 4362623SN/A} 4372623SN/A 4385728Sgblack@eecs.umich.edubool 4395728Sgblack@eecs.umich.eduTimingSimpleCPU::handleWritePacket() 4405728Sgblack@eecs.umich.edu{ 4415728Sgblack@eecs.umich.edu RequestPtr req = dcache_pkt->req; 4428105Sgblack@eecs.umich.edu if (req->isMmappedIpr()) { 4439180Sandreas.hansson@arm.com Cycles delay = TheISA::handleIprWrite(thread->getTC(), dcache_pkt); 4449179Sandreas.hansson@arm.com new IprEvent(dcache_pkt, this, clockEdge(delay)); 4455728Sgblack@eecs.umich.edu _status = DcacheWaitResponse; 4465728Sgblack@eecs.umich.edu dcache_pkt = NULL; 4478975Sandreas.hansson@arm.com } else if (!dcachePort.sendTimingReq(dcache_pkt)) { 4485728Sgblack@eecs.umich.edu _status = DcacheRetry; 4495728Sgblack@eecs.umich.edu } else { 4505728Sgblack@eecs.umich.edu _status = DcacheWaitResponse; 4515728Sgblack@eecs.umich.edu // memory system takes ownership of packet 4525728Sgblack@eecs.umich.edu dcache_pkt = NULL; 4535728Sgblack@eecs.umich.edu } 4545728Sgblack@eecs.umich.edu return dcache_pkt == NULL; 4555728Sgblack@eecs.umich.edu} 4562623SN/A 4572623SN/AFault 4588444Sgblack@eecs.umich.eduTimingSimpleCPU::writeMem(uint8_t *data, unsigned size, 4598444Sgblack@eecs.umich.edu Addr addr, unsigned flags, uint64_t *res) 4602623SN/A{ 4618443Sgblack@eecs.umich.edu uint8_t *newData = new uint8_t[size]; 4625728Sgblack@eecs.umich.edu const int asid = 0; 4636221Snate@binkert.org const ThreadID tid = 0; 4647720Sgblack@eecs.umich.edu const Addr pc = thread->instAddr(); 4659814Sandreas.hansson@arm.com unsigned block_size = cacheLineSize(); 4666973Stjones1@inf.ed.ac.uk BaseTLB::Mode mode = BaseTLB::Write; 4673169Sstever@eecs.umich.edu 46810031SAli.Saidi@ARM.com if (data == NULL) { 46910031SAli.Saidi@ARM.com assert(flags & Request::CACHE_BLOCK_ZERO); 47010031SAli.Saidi@ARM.com // This must be a cache block cleaning request 47110031SAli.Saidi@ARM.com memset(newData, 0, size); 47210031SAli.Saidi@ARM.com } else { 47310031SAli.Saidi@ARM.com memcpy(newData, data, size); 47410031SAli.Saidi@ARM.com } 47510031SAli.Saidi@ARM.com 4767045Ssteve.reinhardt@amd.com if (traceData) { 4777045Ssteve.reinhardt@amd.com traceData->setAddr(addr); 4787045Ssteve.reinhardt@amd.com } 4797045Ssteve.reinhardt@amd.com 4807520Sgblack@eecs.umich.edu RequestPtr req = new Request(asid, addr, size, 4818832SAli.Saidi@ARM.com flags, dataMasterId(), pc, _cpuId, tid); 4825728Sgblack@eecs.umich.edu 48310024Sdam.sunwoo@arm.com req->taskId(taskId()); 48410024Sdam.sunwoo@arm.com 4857520Sgblack@eecs.umich.edu Addr split_addr = roundDown(addr + size - 1, block_size); 4865744Sgblack@eecs.umich.edu assert(split_addr <= addr || split_addr - addr < block_size); 4875728Sgblack@eecs.umich.edu 4885894Sgblack@eecs.umich.edu _status = DTBWaitResponse; 4895744Sgblack@eecs.umich.edu if (split_addr > addr) { 4905894Sgblack@eecs.umich.edu RequestPtr req1, req2; 4916102Sgblack@eecs.umich.edu assert(!req->isLLSC() && !req->isSwap()); 4925894Sgblack@eecs.umich.edu req->splitOnVaddr(split_addr, req1, req2); 4935894Sgblack@eecs.umich.edu 4946973Stjones1@inf.ed.ac.uk WholeTranslationState *state = 4958443Sgblack@eecs.umich.edu new WholeTranslationState(req, req1, req2, newData, res, mode); 4968486Sgblack@eecs.umich.edu DataTranslation<TimingSimpleCPU *> *trans1 = 4978486Sgblack@eecs.umich.edu new DataTranslation<TimingSimpleCPU *>(this, state, 0); 4988486Sgblack@eecs.umich.edu DataTranslation<TimingSimpleCPU *> *trans2 = 4998486Sgblack@eecs.umich.edu new DataTranslation<TimingSimpleCPU *>(this, state, 1); 5006973Stjones1@inf.ed.ac.uk 5016973Stjones1@inf.ed.ac.uk thread->dtb->translateTiming(req1, tc, trans1, mode); 5026973Stjones1@inf.ed.ac.uk thread->dtb->translateTiming(req2, tc, trans2, mode); 5035744Sgblack@eecs.umich.edu } else { 5046973Stjones1@inf.ed.ac.uk WholeTranslationState *state = 5058443Sgblack@eecs.umich.edu new WholeTranslationState(req, newData, res, mode); 5068486Sgblack@eecs.umich.edu DataTranslation<TimingSimpleCPU *> *translation = 5078486Sgblack@eecs.umich.edu new DataTranslation<TimingSimpleCPU *>(this, state); 5086973Stjones1@inf.ed.ac.uk thread->dtb->translateTiming(req, tc, translation, mode); 5092623SN/A } 5102623SN/A 5117045Ssteve.reinhardt@amd.com // Translation faults will be returned via finishTranslation() 5125728Sgblack@eecs.umich.edu return NoFault; 5132623SN/A} 5142623SN/A 5152623SN/A 5162623SN/Avoid 5176973Stjones1@inf.ed.ac.ukTimingSimpleCPU::finishTranslation(WholeTranslationState *state) 5186973Stjones1@inf.ed.ac.uk{ 5199342SAndreas.Sandberg@arm.com _status = BaseSimpleCPU::Running; 5206973Stjones1@inf.ed.ac.uk 5216973Stjones1@inf.ed.ac.uk if (state->getFault() != NoFault) { 5226973Stjones1@inf.ed.ac.uk if (state->isPrefetch()) { 5236973Stjones1@inf.ed.ac.uk state->setNoFault(); 5246973Stjones1@inf.ed.ac.uk } 5257691SAli.Saidi@ARM.com delete [] state->data; 5266973Stjones1@inf.ed.ac.uk state->deleteReqs(); 5276973Stjones1@inf.ed.ac.uk translationFault(state->getFault()); 5286973Stjones1@inf.ed.ac.uk } else { 5296973Stjones1@inf.ed.ac.uk if (!state->isSplit) { 5306973Stjones1@inf.ed.ac.uk sendData(state->mainReq, state->data, state->res, 5316973Stjones1@inf.ed.ac.uk state->mode == BaseTLB::Read); 5326973Stjones1@inf.ed.ac.uk } else { 5336973Stjones1@inf.ed.ac.uk sendSplitData(state->sreqLow, state->sreqHigh, state->mainReq, 5346973Stjones1@inf.ed.ac.uk state->data, state->mode == BaseTLB::Read); 5356973Stjones1@inf.ed.ac.uk } 5366973Stjones1@inf.ed.ac.uk } 5376973Stjones1@inf.ed.ac.uk 5386973Stjones1@inf.ed.ac.uk delete state; 5396973Stjones1@inf.ed.ac.uk} 5406973Stjones1@inf.ed.ac.uk 5416973Stjones1@inf.ed.ac.uk 5426973Stjones1@inf.ed.ac.ukvoid 5432623SN/ATimingSimpleCPU::fetch() 5442623SN/A{ 5455221Ssaidi@eecs.umich.edu DPRINTF(SimpleCPU, "Fetch\n"); 5465221Ssaidi@eecs.umich.edu 5473387Sgblack@eecs.umich.edu if (!curStaticInst || !curStaticInst->isDelayedCommit()) 5483387Sgblack@eecs.umich.edu checkForInterrupts(); 5492631SN/A 5505348Ssaidi@eecs.umich.edu checkPcEventQueue(); 5515348Ssaidi@eecs.umich.edu 5528143SAli.Saidi@ARM.com // We must have just got suspended by a PC event 5538143SAli.Saidi@ARM.com if (_status == Idle) 5548143SAli.Saidi@ARM.com return; 5558143SAli.Saidi@ARM.com 5567720Sgblack@eecs.umich.edu TheISA::PCState pcState = thread->pcState(); 5577720Sgblack@eecs.umich.edu bool needToFetch = !isRomMicroPC(pcState.microPC()) && !curMacroStaticInst; 5582623SN/A 5597720Sgblack@eecs.umich.edu if (needToFetch) { 5609342SAndreas.Sandberg@arm.com _status = BaseSimpleCPU::Running; 5615669Sgblack@eecs.umich.edu Request *ifetch_req = new Request(); 56210024Sdam.sunwoo@arm.com ifetch_req->taskId(taskId()); 5635712Shsul@eecs.umich.edu ifetch_req->setThreadContext(_cpuId, /* thread ID */ 0); 5645894Sgblack@eecs.umich.edu setupFetchRequest(ifetch_req); 5658277SAli.Saidi@ARM.com DPRINTF(SimpleCPU, "Translating address %#x\n", ifetch_req->getVaddr()); 5666023Snate@binkert.org thread->itb->translateTiming(ifetch_req, tc, &fetchTranslation, 5676023Snate@binkert.org BaseTLB::Execute); 5682623SN/A } else { 5695669Sgblack@eecs.umich.edu _status = IcacheWaitResponse; 5705669Sgblack@eecs.umich.edu completeIfetch(NULL); 5715894Sgblack@eecs.umich.edu 5729179Sandreas.hansson@arm.com numCycles += curCycle() - previousCycle; 5739179Sandreas.hansson@arm.com previousCycle = curCycle(); 5745894Sgblack@eecs.umich.edu } 5755894Sgblack@eecs.umich.edu} 5765894Sgblack@eecs.umich.edu 5775894Sgblack@eecs.umich.edu 5785894Sgblack@eecs.umich.eduvoid 57910379Sandreas.hansson@arm.comTimingSimpleCPU::sendFetch(const Fault &fault, RequestPtr req, 58010379Sandreas.hansson@arm.com ThreadContext *tc) 5815894Sgblack@eecs.umich.edu{ 5825894Sgblack@eecs.umich.edu if (fault == NoFault) { 5838277SAli.Saidi@ARM.com DPRINTF(SimpleCPU, "Sending fetch for addr %#x(pa: %#x)\n", 5848277SAli.Saidi@ARM.com req->getVaddr(), req->getPaddr()); 5858949Sandreas.hansson@arm.com ifetch_pkt = new Packet(req, MemCmd::ReadReq); 5865894Sgblack@eecs.umich.edu ifetch_pkt->dataStatic(&inst); 5878277SAli.Saidi@ARM.com DPRINTF(SimpleCPU, " -- pkt addr: %#x\n", ifetch_pkt->getAddr()); 5885894Sgblack@eecs.umich.edu 5898975Sandreas.hansson@arm.com if (!icachePort.sendTimingReq(ifetch_pkt)) { 5905894Sgblack@eecs.umich.edu // Need to wait for retry 5915894Sgblack@eecs.umich.edu _status = IcacheRetry; 5925894Sgblack@eecs.umich.edu } else { 5935894Sgblack@eecs.umich.edu // Need to wait for cache to respond 5945894Sgblack@eecs.umich.edu _status = IcacheWaitResponse; 5955894Sgblack@eecs.umich.edu // ownership of packet transferred to memory system 5965894Sgblack@eecs.umich.edu ifetch_pkt = NULL; 5975894Sgblack@eecs.umich.edu } 5985894Sgblack@eecs.umich.edu } else { 5998277SAli.Saidi@ARM.com DPRINTF(SimpleCPU, "Translation of addr %#x faulted\n", req->getVaddr()); 6005894Sgblack@eecs.umich.edu delete req; 6015894Sgblack@eecs.umich.edu // fetch fault: advance directly to next instruction (fault handler) 6029342SAndreas.Sandberg@arm.com _status = BaseSimpleCPU::Running; 6035894Sgblack@eecs.umich.edu advanceInst(fault); 6042623SN/A } 6053222Sktlim@umich.edu 6069179Sandreas.hansson@arm.com numCycles += curCycle() - previousCycle; 6079179Sandreas.hansson@arm.com previousCycle = curCycle(); 6082623SN/A} 6092623SN/A 6102623SN/A 6112623SN/Avoid 61210379Sandreas.hansson@arm.comTimingSimpleCPU::advanceInst(const Fault &fault) 6132623SN/A{ 6148276SAli.Saidi@ARM.com if (_status == Faulting) 6158276SAli.Saidi@ARM.com return; 6168276SAli.Saidi@ARM.com 6178276SAli.Saidi@ARM.com if (fault != NoFault) { 6188276SAli.Saidi@ARM.com advancePC(fault); 6198276SAli.Saidi@ARM.com DPRINTF(SimpleCPU, "Fault occured, scheduling fetch event\n"); 6209648Sdam.sunwoo@arm.com reschedule(fetchEvent, clockEdge(), true); 6218276SAli.Saidi@ARM.com _status = Faulting; 6228276SAli.Saidi@ARM.com return; 6238276SAli.Saidi@ARM.com } 6248276SAli.Saidi@ARM.com 6258276SAli.Saidi@ARM.com 6268276SAli.Saidi@ARM.com if (!stayAtPC) 6275726Sgblack@eecs.umich.edu advancePC(fault); 6282623SN/A 6299442SAndreas.Sandberg@ARM.com if (tryCompleteDrain()) 6309442SAndreas.Sandberg@ARM.com return; 6319442SAndreas.Sandberg@ARM.com 6329342SAndreas.Sandberg@arm.com if (_status == BaseSimpleCPU::Running) { 6332631SN/A // kick off fetch of next instruction... callback from icache 6342631SN/A // response will cause that instruction to be executed, 6352631SN/A // keeping the CPU running. 6362631SN/A fetch(); 6372631SN/A } 6382623SN/A} 6392623SN/A 6402623SN/A 6412623SN/Avoid 6423349Sbinkertn@umich.eduTimingSimpleCPU::completeIfetch(PacketPtr pkt) 6432623SN/A{ 6448277SAli.Saidi@ARM.com DPRINTF(SimpleCPU, "Complete ICache Fetch for addr %#x\n", pkt ? 6458277SAli.Saidi@ARM.com pkt->getAddr() : 0); 6468277SAli.Saidi@ARM.com 6472623SN/A // received a response from the icache: execute the received 6482623SN/A // instruction 6495669Sgblack@eecs.umich.edu assert(!pkt || !pkt->isError()); 6502623SN/A assert(_status == IcacheWaitResponse); 6512798Sktlim@umich.edu 6529342SAndreas.Sandberg@arm.com _status = BaseSimpleCPU::Running; 6532644Sstever@eecs.umich.edu 6549179Sandreas.hansson@arm.com numCycles += curCycle() - previousCycle; 6559179Sandreas.hansson@arm.com previousCycle = curCycle(); 6563222Sktlim@umich.edu 65710020Smatt.horsnell@ARM.com if (pkt) 65810020Smatt.horsnell@ARM.com pkt->req->setAccessLatency(); 65910020Smatt.horsnell@ARM.com 66010020Smatt.horsnell@ARM.com 6612623SN/A preExecute(); 6627725SAli.Saidi@ARM.com if (curStaticInst && curStaticInst->isMemRef()) { 6632623SN/A // load or store: just send to dcache 6642623SN/A Fault fault = curStaticInst->initiateAcc(this, traceData); 6657945SAli.Saidi@ARM.com 6667945SAli.Saidi@ARM.com // If we're not running now the instruction will complete in a dcache 6677945SAli.Saidi@ARM.com // response callback or the instruction faulted and has started an 6687945SAli.Saidi@ARM.com // ifetch 6699342SAndreas.Sandberg@arm.com if (_status == BaseSimpleCPU::Running) { 6705894Sgblack@eecs.umich.edu if (fault != NoFault && traceData) { 6715001Sgblack@eecs.umich.edu // If there was a fault, we shouldn't trace this instruction. 6725001Sgblack@eecs.umich.edu delete traceData; 6735001Sgblack@eecs.umich.edu traceData = NULL; 6743170Sstever@eecs.umich.edu } 6754998Sgblack@eecs.umich.edu 6762644Sstever@eecs.umich.edu postExecute(); 6775103Ssaidi@eecs.umich.edu // @todo remove me after debugging with legion done 6785103Ssaidi@eecs.umich.edu if (curStaticInst && (!curStaticInst->isMicroop() || 6795103Ssaidi@eecs.umich.edu curStaticInst->isFirstMicroop())) 6805103Ssaidi@eecs.umich.edu instCnt++; 6812644Sstever@eecs.umich.edu advanceInst(fault); 6822644Sstever@eecs.umich.edu } 6835726Sgblack@eecs.umich.edu } else if (curStaticInst) { 6842623SN/A // non-memory instruction: execute completely now 6852623SN/A Fault fault = curStaticInst->execute(this, traceData); 6864998Sgblack@eecs.umich.edu 6874998Sgblack@eecs.umich.edu // keep an instruction count 6884998Sgblack@eecs.umich.edu if (fault == NoFault) 6894998Sgblack@eecs.umich.edu countInst(); 6907655Sali.saidi@arm.com else if (traceData && !DTRACE(ExecFaulting)) { 6915001Sgblack@eecs.umich.edu delete traceData; 6925001Sgblack@eecs.umich.edu traceData = NULL; 6935001Sgblack@eecs.umich.edu } 6944998Sgblack@eecs.umich.edu 6952644Sstever@eecs.umich.edu postExecute(); 6965103Ssaidi@eecs.umich.edu // @todo remove me after debugging with legion done 6975103Ssaidi@eecs.umich.edu if (curStaticInst && (!curStaticInst->isMicroop() || 6985103Ssaidi@eecs.umich.edu curStaticInst->isFirstMicroop())) 6995103Ssaidi@eecs.umich.edu instCnt++; 7002644Sstever@eecs.umich.edu advanceInst(fault); 7015726Sgblack@eecs.umich.edu } else { 7025726Sgblack@eecs.umich.edu advanceInst(NoFault); 7032623SN/A } 7043658Sktlim@umich.edu 7055669Sgblack@eecs.umich.edu if (pkt) { 7065669Sgblack@eecs.umich.edu delete pkt->req; 7075669Sgblack@eecs.umich.edu delete pkt; 7085669Sgblack@eecs.umich.edu } 7092623SN/A} 7102623SN/A 7112948Ssaidi@eecs.umich.eduvoid 7122948Ssaidi@eecs.umich.eduTimingSimpleCPU::IcachePort::ITickEvent::process() 7132948Ssaidi@eecs.umich.edu{ 7142948Ssaidi@eecs.umich.edu cpu->completeIfetch(pkt); 7152948Ssaidi@eecs.umich.edu} 7162623SN/A 7172623SN/Abool 7188975Sandreas.hansson@arm.comTimingSimpleCPU::IcachePort::recvTimingResp(PacketPtr pkt) 7192623SN/A{ 7209165Sandreas.hansson@arm.com DPRINTF(SimpleCPU, "Received timing response %#x\n", pkt->getAddr()); 7219165Sandreas.hansson@arm.com // delay processing of returned data until next CPU clock edge 7229648Sdam.sunwoo@arm.com Tick next_tick = cpu->clockEdge(); 7232948Ssaidi@eecs.umich.edu 7249165Sandreas.hansson@arm.com if (next_tick == curTick()) 7259165Sandreas.hansson@arm.com cpu->completeIfetch(pkt); 7269165Sandreas.hansson@arm.com else 7279165Sandreas.hansson@arm.com tickEvent.schedule(pkt, next_tick); 7288948Sandreas.hansson@arm.com 7294433Ssaidi@eecs.umich.edu return true; 7302623SN/A} 7312623SN/A 7322657Ssaidi@eecs.umich.eduvoid 7332623SN/ATimingSimpleCPU::IcachePort::recvRetry() 7342623SN/A{ 7352623SN/A // we shouldn't get a retry unless we have a packet that we're 7362623SN/A // waiting to transmit 7372623SN/A assert(cpu->ifetch_pkt != NULL); 7382623SN/A assert(cpu->_status == IcacheRetry); 7393349Sbinkertn@umich.edu PacketPtr tmp = cpu->ifetch_pkt; 7408975Sandreas.hansson@arm.com if (sendTimingReq(tmp)) { 7412657Ssaidi@eecs.umich.edu cpu->_status = IcacheWaitResponse; 7422657Ssaidi@eecs.umich.edu cpu->ifetch_pkt = NULL; 7432657Ssaidi@eecs.umich.edu } 7442623SN/A} 7452623SN/A 7462623SN/Avoid 7473349Sbinkertn@umich.eduTimingSimpleCPU::completeDataAccess(PacketPtr pkt) 7482623SN/A{ 7492623SN/A // received a response from the dcache: complete the load or store 7502623SN/A // instruction 7514870Sstever@eecs.umich.edu assert(!pkt->isError()); 7527516Shestness@cs.utexas.edu assert(_status == DcacheWaitResponse || _status == DTBWaitResponse || 7537516Shestness@cs.utexas.edu pkt->req->getFlags().isSet(Request::NO_ACCESS)); 7542623SN/A 75510020Smatt.horsnell@ARM.com pkt->req->setAccessLatency(); 7569179Sandreas.hansson@arm.com numCycles += curCycle() - previousCycle; 7579179Sandreas.hansson@arm.com previousCycle = curCycle(); 7583184Srdreslin@umich.edu 7595728Sgblack@eecs.umich.edu if (pkt->senderState) { 7605728Sgblack@eecs.umich.edu SplitFragmentSenderState * send_state = 7615728Sgblack@eecs.umich.edu dynamic_cast<SplitFragmentSenderState *>(pkt->senderState); 7625728Sgblack@eecs.umich.edu assert(send_state); 7635728Sgblack@eecs.umich.edu delete pkt->req; 7645728Sgblack@eecs.umich.edu delete pkt; 7655728Sgblack@eecs.umich.edu PacketPtr big_pkt = send_state->bigPkt; 7665728Sgblack@eecs.umich.edu delete send_state; 7675728Sgblack@eecs.umich.edu 7685728Sgblack@eecs.umich.edu SplitMainSenderState * main_send_state = 7695728Sgblack@eecs.umich.edu dynamic_cast<SplitMainSenderState *>(big_pkt->senderState); 7705728Sgblack@eecs.umich.edu assert(main_send_state); 7715728Sgblack@eecs.umich.edu // Record the fact that this packet is no longer outstanding. 7725728Sgblack@eecs.umich.edu assert(main_send_state->outstanding != 0); 7735728Sgblack@eecs.umich.edu main_send_state->outstanding--; 7745728Sgblack@eecs.umich.edu 7755728Sgblack@eecs.umich.edu if (main_send_state->outstanding) { 7765728Sgblack@eecs.umich.edu return; 7775728Sgblack@eecs.umich.edu } else { 7785728Sgblack@eecs.umich.edu delete main_send_state; 7795728Sgblack@eecs.umich.edu big_pkt->senderState = NULL; 7805728Sgblack@eecs.umich.edu pkt = big_pkt; 7815728Sgblack@eecs.umich.edu } 7825728Sgblack@eecs.umich.edu } 7835728Sgblack@eecs.umich.edu 7849342SAndreas.Sandberg@arm.com _status = BaseSimpleCPU::Running; 7855728Sgblack@eecs.umich.edu 7862623SN/A Fault fault = curStaticInst->completeAcc(pkt, this, traceData); 7872623SN/A 7884998Sgblack@eecs.umich.edu // keep an instruction count 7894998Sgblack@eecs.umich.edu if (fault == NoFault) 7904998Sgblack@eecs.umich.edu countInst(); 7915001Sgblack@eecs.umich.edu else if (traceData) { 7925001Sgblack@eecs.umich.edu // If there was a fault, we shouldn't trace this instruction. 7935001Sgblack@eecs.umich.edu delete traceData; 7945001Sgblack@eecs.umich.edu traceData = NULL; 7955001Sgblack@eecs.umich.edu } 7964998Sgblack@eecs.umich.edu 7975507Sstever@gmail.com // the locked flag may be cleared on the response packet, so check 7985507Sstever@gmail.com // pkt->req and not pkt to see if it was a load-locked 7996102Sgblack@eecs.umich.edu if (pkt->isRead() && pkt->req->isLLSC()) { 8003170Sstever@eecs.umich.edu TheISA::handleLockedRead(thread, pkt->req); 8013170Sstever@eecs.umich.edu } 8023170Sstever@eecs.umich.edu 8032644Sstever@eecs.umich.edu delete pkt->req; 8042644Sstever@eecs.umich.edu delete pkt; 8052644Sstever@eecs.umich.edu 8063184Srdreslin@umich.edu postExecute(); 8073227Sktlim@umich.edu 8082644Sstever@eecs.umich.edu advanceInst(fault); 8092623SN/A} 8102623SN/A 81110030SAli.Saidi@ARM.comvoid 81210030SAli.Saidi@ARM.comTimingSimpleCPU::DcachePort::recvTimingSnoopReq(PacketPtr pkt) 81310030SAli.Saidi@ARM.com{ 81410030SAli.Saidi@ARM.com TheISA::handleLockedSnoop(cpu->thread, pkt, cacheBlockMask); 81510030SAli.Saidi@ARM.com} 81610030SAli.Saidi@ARM.com 81710030SAli.Saidi@ARM.com 8182623SN/Abool 8198975Sandreas.hansson@arm.comTimingSimpleCPU::DcachePort::recvTimingResp(PacketPtr pkt) 8202623SN/A{ 8219165Sandreas.hansson@arm.com // delay processing of returned data until next CPU clock edge 8229648Sdam.sunwoo@arm.com Tick next_tick = cpu->clockEdge(); 8232948Ssaidi@eecs.umich.edu 8249165Sandreas.hansson@arm.com if (next_tick == curTick()) { 8259165Sandreas.hansson@arm.com cpu->completeDataAccess(pkt); 8269165Sandreas.hansson@arm.com } else { 8279165Sandreas.hansson@arm.com if (!tickEvent.scheduled()) { 8289165Sandreas.hansson@arm.com tickEvent.schedule(pkt, next_tick); 8295728Sgblack@eecs.umich.edu } else { 8309165Sandreas.hansson@arm.com // In the case of a split transaction and a cache that is 8319165Sandreas.hansson@arm.com // faster than a CPU we could get two responses before 8329165Sandreas.hansson@arm.com // next_tick expires 8339165Sandreas.hansson@arm.com if (!retryEvent.scheduled()) 8349165Sandreas.hansson@arm.com cpu->schedule(retryEvent, next_tick); 8359165Sandreas.hansson@arm.com return false; 8364433Ssaidi@eecs.umich.edu } 8373310Srdreslin@umich.edu } 8388948Sandreas.hansson@arm.com 8394433Ssaidi@eecs.umich.edu return true; 8402948Ssaidi@eecs.umich.edu} 8412948Ssaidi@eecs.umich.edu 8422948Ssaidi@eecs.umich.eduvoid 8432948Ssaidi@eecs.umich.eduTimingSimpleCPU::DcachePort::DTickEvent::process() 8442948Ssaidi@eecs.umich.edu{ 8452630SN/A cpu->completeDataAccess(pkt); 8462623SN/A} 8472623SN/A 8482657Ssaidi@eecs.umich.eduvoid 8492623SN/ATimingSimpleCPU::DcachePort::recvRetry() 8502623SN/A{ 8512623SN/A // we shouldn't get a retry unless we have a packet that we're 8522623SN/A // waiting to transmit 8532623SN/A assert(cpu->dcache_pkt != NULL); 8542623SN/A assert(cpu->_status == DcacheRetry); 8553349Sbinkertn@umich.edu PacketPtr tmp = cpu->dcache_pkt; 8565728Sgblack@eecs.umich.edu if (tmp->senderState) { 8575728Sgblack@eecs.umich.edu // This is a packet from a split access. 8585728Sgblack@eecs.umich.edu SplitFragmentSenderState * send_state = 8595728Sgblack@eecs.umich.edu dynamic_cast<SplitFragmentSenderState *>(tmp->senderState); 8605728Sgblack@eecs.umich.edu assert(send_state); 8615728Sgblack@eecs.umich.edu PacketPtr big_pkt = send_state->bigPkt; 8625728Sgblack@eecs.umich.edu 8635728Sgblack@eecs.umich.edu SplitMainSenderState * main_send_state = 8645728Sgblack@eecs.umich.edu dynamic_cast<SplitMainSenderState *>(big_pkt->senderState); 8655728Sgblack@eecs.umich.edu assert(main_send_state); 8665728Sgblack@eecs.umich.edu 8678975Sandreas.hansson@arm.com if (sendTimingReq(tmp)) { 8685728Sgblack@eecs.umich.edu // If we were able to send without retrying, record that fact 8695728Sgblack@eecs.umich.edu // and try sending the other fragment. 8705728Sgblack@eecs.umich.edu send_state->clearFromParent(); 8715728Sgblack@eecs.umich.edu int other_index = main_send_state->getPendingFragment(); 8725728Sgblack@eecs.umich.edu if (other_index > 0) { 8735728Sgblack@eecs.umich.edu tmp = main_send_state->fragments[other_index]; 8745728Sgblack@eecs.umich.edu cpu->dcache_pkt = tmp; 8755728Sgblack@eecs.umich.edu if ((big_pkt->isRead() && cpu->handleReadPacket(tmp)) || 8765728Sgblack@eecs.umich.edu (big_pkt->isWrite() && cpu->handleWritePacket())) { 8775728Sgblack@eecs.umich.edu main_send_state->fragments[other_index] = NULL; 8785728Sgblack@eecs.umich.edu } 8795728Sgblack@eecs.umich.edu } else { 8805728Sgblack@eecs.umich.edu cpu->_status = DcacheWaitResponse; 8815728Sgblack@eecs.umich.edu // memory system takes ownership of packet 8825728Sgblack@eecs.umich.edu cpu->dcache_pkt = NULL; 8835728Sgblack@eecs.umich.edu } 8845728Sgblack@eecs.umich.edu } 8858975Sandreas.hansson@arm.com } else if (sendTimingReq(tmp)) { 8862657Ssaidi@eecs.umich.edu cpu->_status = DcacheWaitResponse; 8873170Sstever@eecs.umich.edu // memory system takes ownership of packet 8882657Ssaidi@eecs.umich.edu cpu->dcache_pkt = NULL; 8892657Ssaidi@eecs.umich.edu } 8902623SN/A} 8912623SN/A 8925606Snate@binkert.orgTimingSimpleCPU::IprEvent::IprEvent(Packet *_pkt, TimingSimpleCPU *_cpu, 8935606Snate@binkert.org Tick t) 8945606Snate@binkert.org : pkt(_pkt), cpu(_cpu) 8955103Ssaidi@eecs.umich.edu{ 8965606Snate@binkert.org cpu->schedule(this, t); 8975103Ssaidi@eecs.umich.edu} 8985103Ssaidi@eecs.umich.edu 8995103Ssaidi@eecs.umich.eduvoid 9005103Ssaidi@eecs.umich.eduTimingSimpleCPU::IprEvent::process() 9015103Ssaidi@eecs.umich.edu{ 9025103Ssaidi@eecs.umich.edu cpu->completeDataAccess(pkt); 9035103Ssaidi@eecs.umich.edu} 9045103Ssaidi@eecs.umich.edu 9055103Ssaidi@eecs.umich.educonst char * 9065336Shines@cs.fsu.eduTimingSimpleCPU::IprEvent::description() const 9075103Ssaidi@eecs.umich.edu{ 9085103Ssaidi@eecs.umich.edu return "Timing Simple CPU Delay IPR event"; 9095103Ssaidi@eecs.umich.edu} 9105103Ssaidi@eecs.umich.edu 9112623SN/A 9125315Sstever@gmail.comvoid 9135315Sstever@gmail.comTimingSimpleCPU::printAddr(Addr a) 9145315Sstever@gmail.com{ 9155315Sstever@gmail.com dcachePort.printAddr(a); 9165315Sstever@gmail.com} 9175315Sstever@gmail.com 9185315Sstever@gmail.com 9192623SN/A//////////////////////////////////////////////////////////////////////// 9202623SN/A// 9212623SN/A// TimingSimpleCPU Simulation Object 9222623SN/A// 9234762Snate@binkert.orgTimingSimpleCPU * 9244762Snate@binkert.orgTimingSimpleCPUParams::create() 9252623SN/A{ 9265529Snate@binkert.org numThreads = 1; 9278779Sgblack@eecs.umich.edu if (!FullSystem && workload.size() != 1) 9284762Snate@binkert.org panic("only one workload allowed"); 9295529Snate@binkert.org return new TimingSimpleCPU(this); 9302623SN/A} 931