timing.cc revision 10020
12623SN/A/* 28948Sandreas.hansson@arm.com * Copyright (c) 2010-2012 ARM Limited 37725SAli.Saidi@ARM.com * All rights reserved 47725SAli.Saidi@ARM.com * 57725SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall 67725SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 77725SAli.Saidi@ARM.com * property including but not limited to intellectual property relating 87725SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software 97725SAli.Saidi@ARM.com * licensed hereunder. You may use the software subject to the license 107725SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated 117725SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software, 127725SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form. 137725SAli.Saidi@ARM.com * 142623SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 152623SN/A * All rights reserved. 162623SN/A * 172623SN/A * Redistribution and use in source and binary forms, with or without 182623SN/A * modification, are permitted provided that the following conditions are 192623SN/A * met: redistributions of source code must retain the above copyright 202623SN/A * notice, this list of conditions and the following disclaimer; 212623SN/A * redistributions in binary form must reproduce the above copyright 222623SN/A * notice, this list of conditions and the following disclaimer in the 232623SN/A * documentation and/or other materials provided with the distribution; 242623SN/A * neither the name of the copyright holders nor the names of its 252623SN/A * contributors may be used to endorse or promote products derived from 262623SN/A * this software without specific prior written permission. 272623SN/A * 282623SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292623SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302623SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312623SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322623SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332623SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342623SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352623SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362623SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372623SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382623SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392665Ssaidi@eecs.umich.edu * 402665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 412623SN/A */ 422623SN/A 433170Sstever@eecs.umich.edu#include "arch/locked_mem.hh" 448105Sgblack@eecs.umich.edu#include "arch/mmapped_ipr.hh" 452623SN/A#include "arch/utility.hh" 464040Ssaidi@eecs.umich.edu#include "base/bigint.hh" 476658Snate@binkert.org#include "config/the_isa.hh" 488229Snate@binkert.org#include "cpu/simple/timing.hh" 492623SN/A#include "cpu/exetrace.hh" 508232Snate@binkert.org#include "debug/Config.hh" 519152Satgutier@umich.edu#include "debug/Drain.hh" 528232Snate@binkert.org#include "debug/ExecFaulting.hh" 538232Snate@binkert.org#include "debug/SimpleCPU.hh" 543348Sbinkertn@umich.edu#include "mem/packet.hh" 553348Sbinkertn@umich.edu#include "mem/packet_access.hh" 564762Snate@binkert.org#include "params/TimingSimpleCPU.hh" 577678Sgblack@eecs.umich.edu#include "sim/faults.hh" 588779Sgblack@eecs.umich.edu#include "sim/full_system.hh" 592901Ssaidi@eecs.umich.edu#include "sim/system.hh" 602623SN/A 612623SN/Ausing namespace std; 622623SN/Ausing namespace TheISA; 632623SN/A 642623SN/Avoid 652623SN/ATimingSimpleCPU::init() 662623SN/A{ 672623SN/A BaseCPU::init(); 688921Sandreas.hansson@arm.com 698921Sandreas.hansson@arm.com // Initialise the ThreadContext's memory proxies 708921Sandreas.hansson@arm.com tcBase()->initMemProxies(tcBase()); 718921Sandreas.hansson@arm.com 729433SAndreas.Sandberg@ARM.com if (FullSystem && !params()->switched_out) { 738779Sgblack@eecs.umich.edu for (int i = 0; i < threadContexts.size(); ++i) { 748779Sgblack@eecs.umich.edu ThreadContext *tc = threadContexts[i]; 758779Sgblack@eecs.umich.edu // initialize CPU, including PC 768779Sgblack@eecs.umich.edu TheISA::initCPU(tc, _cpuId); 778779Sgblack@eecs.umich.edu } 782623SN/A } 792623SN/A} 802623SN/A 812623SN/Avoid 828707Sandreas.hansson@arm.comTimingSimpleCPU::TimingCPUPort::TickEvent::schedule(PacketPtr _pkt, Tick t) 832948Ssaidi@eecs.umich.edu{ 842948Ssaidi@eecs.umich.edu pkt = _pkt; 855606Snate@binkert.org cpu->schedule(this, t); 862948Ssaidi@eecs.umich.edu} 872948Ssaidi@eecs.umich.edu 885529Snate@binkert.orgTimingSimpleCPU::TimingSimpleCPU(TimingSimpleCPUParams *p) 898707Sandreas.hansson@arm.com : BaseSimpleCPU(p), fetchTranslation(this), icachePort(this), 909179Sandreas.hansson@arm.com dcachePort(this), ifetch_pkt(NULL), dcache_pkt(NULL), previousCycle(0), 919442SAndreas.Sandberg@ARM.com fetchEvent(this), drainManager(NULL) 922623SN/A{ 932623SN/A _status = Idle; 943647Srdreslin@umich.edu 957897Shestness@cs.utexas.edu system->totalNumInsts = 0; 962623SN/A} 972623SN/A 982623SN/A 992623SN/ATimingSimpleCPU::~TimingSimpleCPU() 1002623SN/A{ 1012623SN/A} 1022623SN/A 1032901Ssaidi@eecs.umich.eduunsigned int 1049342SAndreas.Sandberg@arm.comTimingSimpleCPU::drain(DrainManager *drain_manager) 1052798Sktlim@umich.edu{ 1069448SAndreas.Sandberg@ARM.com assert(!drainManager); 1079448SAndreas.Sandberg@ARM.com if (switchedOut()) 1089448SAndreas.Sandberg@ARM.com return 0; 1099448SAndreas.Sandberg@ARM.com 1109342SAndreas.Sandberg@arm.com if (_status == Idle || 1119448SAndreas.Sandberg@ARM.com (_status == BaseSimpleCPU::Running && isDrained())) { 1129442SAndreas.Sandberg@ARM.com DPRINTF(Drain, "No need to drain.\n"); 1132901Ssaidi@eecs.umich.edu return 0; 1142798Sktlim@umich.edu } else { 1159342SAndreas.Sandberg@arm.com drainManager = drain_manager; 1169442SAndreas.Sandberg@ARM.com DPRINTF(Drain, "Requesting drain: %s\n", pcState()); 1179442SAndreas.Sandberg@ARM.com 1189442SAndreas.Sandberg@ARM.com // The fetch event can become descheduled if a drain didn't 1199442SAndreas.Sandberg@ARM.com // succeed on the first attempt. We need to reschedule it if 1209442SAndreas.Sandberg@ARM.com // the CPU is waiting for a microcode routine to complete. 1219448SAndreas.Sandberg@ARM.com if (_status == BaseSimpleCPU::Running && !fetchEvent.scheduled()) 1229648Sdam.sunwoo@arm.com schedule(fetchEvent, clockEdge()); 1239442SAndreas.Sandberg@ARM.com 1242901Ssaidi@eecs.umich.edu return 1; 1252798Sktlim@umich.edu } 1262623SN/A} 1272623SN/A 1282623SN/Avoid 1299342SAndreas.Sandberg@arm.comTimingSimpleCPU::drainResume() 1302623SN/A{ 1319442SAndreas.Sandberg@ARM.com assert(!fetchEvent.scheduled()); 1329448SAndreas.Sandberg@ARM.com assert(!drainManager); 1339448SAndreas.Sandberg@ARM.com if (switchedOut()) 1349448SAndreas.Sandberg@ARM.com return; 1359442SAndreas.Sandberg@ARM.com 1365221Ssaidi@eecs.umich.edu DPRINTF(SimpleCPU, "Resume\n"); 1379523SAndreas.Sandberg@ARM.com verifyMemoryMode(); 1383201Shsul@eecs.umich.edu 1399448SAndreas.Sandberg@ARM.com assert(!threadContexts.empty()); 1409448SAndreas.Sandberg@ARM.com if (threadContexts.size() > 1) 1419448SAndreas.Sandberg@ARM.com fatal("The timing CPU only supports one thread.\n"); 1429448SAndreas.Sandberg@ARM.com 1439448SAndreas.Sandberg@ARM.com if (thread->status() == ThreadContext::Active) { 1445710Scws3k@cs.virginia.edu schedule(fetchEvent, nextCycle()); 1459448SAndreas.Sandberg@ARM.com _status = BaseSimpleCPU::Running; 1469837Slena@cs.wisc,edu notIdleFraction = 1; 1479448SAndreas.Sandberg@ARM.com } else { 1489448SAndreas.Sandberg@ARM.com _status = BaseSimpleCPU::Idle; 1499837Slena@cs.wisc,edu notIdleFraction = 0; 1502623SN/A } 1519442SAndreas.Sandberg@ARM.com} 1522798Sktlim@umich.edu 1539442SAndreas.Sandberg@ARM.combool 1549442SAndreas.Sandberg@ARM.comTimingSimpleCPU::tryCompleteDrain() 1559442SAndreas.Sandberg@ARM.com{ 1569442SAndreas.Sandberg@ARM.com if (!drainManager) 1579442SAndreas.Sandberg@ARM.com return false; 1589442SAndreas.Sandberg@ARM.com 1599442SAndreas.Sandberg@ARM.com DPRINTF(Drain, "tryCompleteDrain: %s\n", pcState()); 1609442SAndreas.Sandberg@ARM.com if (!isDrained()) 1619442SAndreas.Sandberg@ARM.com return false; 1629442SAndreas.Sandberg@ARM.com 1639442SAndreas.Sandberg@ARM.com DPRINTF(Drain, "CPU done draining, processing drain event\n"); 1649442SAndreas.Sandberg@ARM.com drainManager->signalDrainDone(); 1659442SAndreas.Sandberg@ARM.com drainManager = NULL; 1669442SAndreas.Sandberg@ARM.com 1679442SAndreas.Sandberg@ARM.com return true; 1682798Sktlim@umich.edu} 1692798Sktlim@umich.edu 1702798Sktlim@umich.eduvoid 1712798Sktlim@umich.eduTimingSimpleCPU::switchOut() 1722798Sktlim@umich.edu{ 1739429SAndreas.Sandberg@ARM.com BaseSimpleCPU::switchOut(); 1749429SAndreas.Sandberg@ARM.com 1759442SAndreas.Sandberg@ARM.com assert(!fetchEvent.scheduled()); 1769342SAndreas.Sandberg@arm.com assert(_status == BaseSimpleCPU::Running || _status == Idle); 1779442SAndreas.Sandberg@ARM.com assert(!stayAtPC); 1789442SAndreas.Sandberg@ARM.com assert(microPC() == 0); 1799442SAndreas.Sandberg@ARM.com 1809179Sandreas.hansson@arm.com numCycles += curCycle() - previousCycle; 1812623SN/A} 1822623SN/A 1832623SN/A 1842623SN/Avoid 1852623SN/ATimingSimpleCPU::takeOverFrom(BaseCPU *oldCPU) 1862623SN/A{ 1879429SAndreas.Sandberg@ARM.com BaseSimpleCPU::takeOverFrom(oldCPU); 1882623SN/A 1899179Sandreas.hansson@arm.com previousCycle = curCycle(); 1902623SN/A} 1912623SN/A 1929523SAndreas.Sandberg@ARM.comvoid 1939523SAndreas.Sandberg@ARM.comTimingSimpleCPU::verifyMemoryMode() const 1949523SAndreas.Sandberg@ARM.com{ 1959524SAndreas.Sandberg@ARM.com if (!system->isTimingMode()) { 1969523SAndreas.Sandberg@ARM.com fatal("The timing CPU requires the memory system to be in " 1979523SAndreas.Sandberg@ARM.com "'timing' mode.\n"); 1989523SAndreas.Sandberg@ARM.com } 1999523SAndreas.Sandberg@ARM.com} 2002623SN/A 2012623SN/Avoid 2029180Sandreas.hansson@arm.comTimingSimpleCPU::activateContext(ThreadID thread_num, Cycles delay) 2032623SN/A{ 2045221Ssaidi@eecs.umich.edu DPRINTF(SimpleCPU, "ActivateContext %d (%d cycles)\n", thread_num, delay); 2055221Ssaidi@eecs.umich.edu 2062623SN/A assert(thread_num == 0); 2072683Sktlim@umich.edu assert(thread); 2082623SN/A 2092623SN/A assert(_status == Idle); 2102623SN/A 2119837Slena@cs.wisc,edu notIdleFraction = 1; 2129342SAndreas.Sandberg@arm.com _status = BaseSimpleCPU::Running; 2133686Sktlim@umich.edu 2142623SN/A // kick things off by initiating the fetch of the next instruction 2159179Sandreas.hansson@arm.com schedule(fetchEvent, clockEdge(delay)); 2162623SN/A} 2172623SN/A 2182623SN/A 2192623SN/Avoid 2208737Skoansin.tan@gmail.comTimingSimpleCPU::suspendContext(ThreadID thread_num) 2212623SN/A{ 2225221Ssaidi@eecs.umich.edu DPRINTF(SimpleCPU, "SuspendContext %d\n", thread_num); 2235221Ssaidi@eecs.umich.edu 2242623SN/A assert(thread_num == 0); 2252683Sktlim@umich.edu assert(thread); 2262623SN/A 2276043Sgblack@eecs.umich.edu if (_status == Idle) 2286043Sgblack@eecs.umich.edu return; 2296043Sgblack@eecs.umich.edu 2309342SAndreas.Sandberg@arm.com assert(_status == BaseSimpleCPU::Running); 2312623SN/A 2322644Sstever@eecs.umich.edu // just change status to Idle... if status != Running, 2332644Sstever@eecs.umich.edu // completeInst() will not initiate fetch of next instruction. 2342623SN/A 2359837Slena@cs.wisc,edu notIdleFraction = 0; 2362623SN/A _status = Idle; 2372623SN/A} 2382623SN/A 2395728Sgblack@eecs.umich.edubool 2405728Sgblack@eecs.umich.eduTimingSimpleCPU::handleReadPacket(PacketPtr pkt) 2415728Sgblack@eecs.umich.edu{ 2425728Sgblack@eecs.umich.edu RequestPtr req = pkt->req; 2438105Sgblack@eecs.umich.edu if (req->isMmappedIpr()) { 2449180Sandreas.hansson@arm.com Cycles delay = TheISA::handleIprRead(thread->getTC(), pkt); 2459179Sandreas.hansson@arm.com new IprEvent(pkt, this, clockEdge(delay)); 2465728Sgblack@eecs.umich.edu _status = DcacheWaitResponse; 2475728Sgblack@eecs.umich.edu dcache_pkt = NULL; 2488975Sandreas.hansson@arm.com } else if (!dcachePort.sendTimingReq(pkt)) { 2495728Sgblack@eecs.umich.edu _status = DcacheRetry; 2505728Sgblack@eecs.umich.edu dcache_pkt = pkt; 2515728Sgblack@eecs.umich.edu } else { 2525728Sgblack@eecs.umich.edu _status = DcacheWaitResponse; 2535728Sgblack@eecs.umich.edu // memory system takes ownership of packet 2545728Sgblack@eecs.umich.edu dcache_pkt = NULL; 2555728Sgblack@eecs.umich.edu } 2565728Sgblack@eecs.umich.edu return dcache_pkt == NULL; 2575728Sgblack@eecs.umich.edu} 2582623SN/A 2595894Sgblack@eecs.umich.eduvoid 2606973Stjones1@inf.ed.ac.ukTimingSimpleCPU::sendData(RequestPtr req, uint8_t *data, uint64_t *res, 2616973Stjones1@inf.ed.ac.uk bool read) 2625744Sgblack@eecs.umich.edu{ 2635894Sgblack@eecs.umich.edu PacketPtr pkt; 2645894Sgblack@eecs.umich.edu buildPacket(pkt, req, read); 2657691SAli.Saidi@ARM.com pkt->dataDynamicArray<uint8_t>(data); 2665894Sgblack@eecs.umich.edu if (req->getFlags().isSet(Request::NO_ACCESS)) { 2675894Sgblack@eecs.umich.edu assert(!dcache_pkt); 2685894Sgblack@eecs.umich.edu pkt->makeResponse(); 2695894Sgblack@eecs.umich.edu completeDataAccess(pkt); 2705894Sgblack@eecs.umich.edu } else if (read) { 2715894Sgblack@eecs.umich.edu handleReadPacket(pkt); 2725894Sgblack@eecs.umich.edu } else { 2735894Sgblack@eecs.umich.edu bool do_access = true; // flag to suppress cache access 2745894Sgblack@eecs.umich.edu 2756102Sgblack@eecs.umich.edu if (req->isLLSC()) { 2765894Sgblack@eecs.umich.edu do_access = TheISA::handleLockedWrite(thread, req); 2775894Sgblack@eecs.umich.edu } else if (req->isCondSwap()) { 2785894Sgblack@eecs.umich.edu assert(res); 2795894Sgblack@eecs.umich.edu req->setExtraData(*res); 2805894Sgblack@eecs.umich.edu } 2815894Sgblack@eecs.umich.edu 2825894Sgblack@eecs.umich.edu if (do_access) { 2835894Sgblack@eecs.umich.edu dcache_pkt = pkt; 2845894Sgblack@eecs.umich.edu handleWritePacket(); 2855894Sgblack@eecs.umich.edu } else { 2865894Sgblack@eecs.umich.edu _status = DcacheWaitResponse; 2875894Sgblack@eecs.umich.edu completeDataAccess(pkt); 2885894Sgblack@eecs.umich.edu } 2895894Sgblack@eecs.umich.edu } 2905894Sgblack@eecs.umich.edu} 2915894Sgblack@eecs.umich.edu 2925894Sgblack@eecs.umich.eduvoid 2936973Stjones1@inf.ed.ac.ukTimingSimpleCPU::sendSplitData(RequestPtr req1, RequestPtr req2, 2946973Stjones1@inf.ed.ac.uk RequestPtr req, uint8_t *data, bool read) 2955894Sgblack@eecs.umich.edu{ 2965894Sgblack@eecs.umich.edu PacketPtr pkt1, pkt2; 2975894Sgblack@eecs.umich.edu buildSplitPacket(pkt1, pkt2, req1, req2, req, data, read); 2985894Sgblack@eecs.umich.edu if (req->getFlags().isSet(Request::NO_ACCESS)) { 2995894Sgblack@eecs.umich.edu assert(!dcache_pkt); 3005894Sgblack@eecs.umich.edu pkt1->makeResponse(); 3015894Sgblack@eecs.umich.edu completeDataAccess(pkt1); 3025894Sgblack@eecs.umich.edu } else if (read) { 3037911Shestness@cs.utexas.edu SplitFragmentSenderState * send_state = 3047911Shestness@cs.utexas.edu dynamic_cast<SplitFragmentSenderState *>(pkt1->senderState); 3055894Sgblack@eecs.umich.edu if (handleReadPacket(pkt1)) { 3065894Sgblack@eecs.umich.edu send_state->clearFromParent(); 3077911Shestness@cs.utexas.edu send_state = dynamic_cast<SplitFragmentSenderState *>( 3087911Shestness@cs.utexas.edu pkt2->senderState); 3095894Sgblack@eecs.umich.edu if (handleReadPacket(pkt2)) { 3105894Sgblack@eecs.umich.edu send_state->clearFromParent(); 3115894Sgblack@eecs.umich.edu } 3125894Sgblack@eecs.umich.edu } 3135894Sgblack@eecs.umich.edu } else { 3145894Sgblack@eecs.umich.edu dcache_pkt = pkt1; 3157911Shestness@cs.utexas.edu SplitFragmentSenderState * send_state = 3167911Shestness@cs.utexas.edu dynamic_cast<SplitFragmentSenderState *>(pkt1->senderState); 3175894Sgblack@eecs.umich.edu if (handleWritePacket()) { 3185894Sgblack@eecs.umich.edu send_state->clearFromParent(); 3195894Sgblack@eecs.umich.edu dcache_pkt = pkt2; 3207911Shestness@cs.utexas.edu send_state = dynamic_cast<SplitFragmentSenderState *>( 3217911Shestness@cs.utexas.edu pkt2->senderState); 3225894Sgblack@eecs.umich.edu if (handleWritePacket()) { 3235894Sgblack@eecs.umich.edu send_state->clearFromParent(); 3245894Sgblack@eecs.umich.edu } 3255894Sgblack@eecs.umich.edu } 3265894Sgblack@eecs.umich.edu } 3275894Sgblack@eecs.umich.edu} 3285894Sgblack@eecs.umich.edu 3295894Sgblack@eecs.umich.eduvoid 3305894Sgblack@eecs.umich.eduTimingSimpleCPU::translationFault(Fault fault) 3315894Sgblack@eecs.umich.edu{ 3326739Sgblack@eecs.umich.edu // fault may be NoFault in cases where a fault is suppressed, 3336739Sgblack@eecs.umich.edu // for instance prefetches. 3349179Sandreas.hansson@arm.com numCycles += curCycle() - previousCycle; 3359179Sandreas.hansson@arm.com previousCycle = curCycle(); 3365894Sgblack@eecs.umich.edu 3375894Sgblack@eecs.umich.edu if (traceData) { 3385894Sgblack@eecs.umich.edu // Since there was a fault, we shouldn't trace this instruction. 3395894Sgblack@eecs.umich.edu delete traceData; 3405894Sgblack@eecs.umich.edu traceData = NULL; 3415744Sgblack@eecs.umich.edu } 3425744Sgblack@eecs.umich.edu 3435894Sgblack@eecs.umich.edu postExecute(); 3445894Sgblack@eecs.umich.edu 3459442SAndreas.Sandberg@ARM.com advanceInst(fault); 3465894Sgblack@eecs.umich.edu} 3475894Sgblack@eecs.umich.edu 3485894Sgblack@eecs.umich.eduvoid 3495894Sgblack@eecs.umich.eduTimingSimpleCPU::buildPacket(PacketPtr &pkt, RequestPtr req, bool read) 3505894Sgblack@eecs.umich.edu{ 3515894Sgblack@eecs.umich.edu MemCmd cmd; 3525894Sgblack@eecs.umich.edu if (read) { 3535894Sgblack@eecs.umich.edu cmd = MemCmd::ReadReq; 3546102Sgblack@eecs.umich.edu if (req->isLLSC()) 3555894Sgblack@eecs.umich.edu cmd = MemCmd::LoadLockedReq; 3565894Sgblack@eecs.umich.edu } else { 3575894Sgblack@eecs.umich.edu cmd = MemCmd::WriteReq; 3586102Sgblack@eecs.umich.edu if (req->isLLSC()) { 3595894Sgblack@eecs.umich.edu cmd = MemCmd::StoreCondReq; 3605894Sgblack@eecs.umich.edu } else if (req->isSwap()) { 3615894Sgblack@eecs.umich.edu cmd = MemCmd::SwapReq; 3625894Sgblack@eecs.umich.edu } 3635894Sgblack@eecs.umich.edu } 3648949Sandreas.hansson@arm.com pkt = new Packet(req, cmd); 3655894Sgblack@eecs.umich.edu} 3665894Sgblack@eecs.umich.edu 3675894Sgblack@eecs.umich.eduvoid 3685894Sgblack@eecs.umich.eduTimingSimpleCPU::buildSplitPacket(PacketPtr &pkt1, PacketPtr &pkt2, 3695894Sgblack@eecs.umich.edu RequestPtr req1, RequestPtr req2, RequestPtr req, 3705894Sgblack@eecs.umich.edu uint8_t *data, bool read) 3715894Sgblack@eecs.umich.edu{ 3725894Sgblack@eecs.umich.edu pkt1 = pkt2 = NULL; 3735894Sgblack@eecs.umich.edu 3748105Sgblack@eecs.umich.edu assert(!req1->isMmappedIpr() && !req2->isMmappedIpr()); 3755744Sgblack@eecs.umich.edu 3765894Sgblack@eecs.umich.edu if (req->getFlags().isSet(Request::NO_ACCESS)) { 3775894Sgblack@eecs.umich.edu buildPacket(pkt1, req, read); 3785894Sgblack@eecs.umich.edu return; 3795894Sgblack@eecs.umich.edu } 3805894Sgblack@eecs.umich.edu 3815894Sgblack@eecs.umich.edu buildPacket(pkt1, req1, read); 3825894Sgblack@eecs.umich.edu buildPacket(pkt2, req2, read); 3835894Sgblack@eecs.umich.edu 3848832SAli.Saidi@ARM.com req->setPhys(req1->getPaddr(), req->getSize(), req1->getFlags(), dataMasterId()); 3858949Sandreas.hansson@arm.com PacketPtr pkt = new Packet(req, pkt1->cmd.responseCommand()); 3865744Sgblack@eecs.umich.edu 3877691SAli.Saidi@ARM.com pkt->dataDynamicArray<uint8_t>(data); 3885744Sgblack@eecs.umich.edu pkt1->dataStatic<uint8_t>(data); 3895744Sgblack@eecs.umich.edu pkt2->dataStatic<uint8_t>(data + req1->getSize()); 3905744Sgblack@eecs.umich.edu 3915744Sgblack@eecs.umich.edu SplitMainSenderState * main_send_state = new SplitMainSenderState; 3925744Sgblack@eecs.umich.edu pkt->senderState = main_send_state; 3935744Sgblack@eecs.umich.edu main_send_state->fragments[0] = pkt1; 3945744Sgblack@eecs.umich.edu main_send_state->fragments[1] = pkt2; 3955744Sgblack@eecs.umich.edu main_send_state->outstanding = 2; 3965744Sgblack@eecs.umich.edu pkt1->senderState = new SplitFragmentSenderState(pkt, 0); 3975744Sgblack@eecs.umich.edu pkt2->senderState = new SplitFragmentSenderState(pkt, 1); 3985744Sgblack@eecs.umich.edu} 3995744Sgblack@eecs.umich.edu 4002623SN/AFault 4018444Sgblack@eecs.umich.eduTimingSimpleCPU::readMem(Addr addr, uint8_t *data, 4028444Sgblack@eecs.umich.edu unsigned size, unsigned flags) 4032623SN/A{ 4045728Sgblack@eecs.umich.edu Fault fault; 4055728Sgblack@eecs.umich.edu const int asid = 0; 4066221Snate@binkert.org const ThreadID tid = 0; 4077720Sgblack@eecs.umich.edu const Addr pc = thread->instAddr(); 4089814Sandreas.hansson@arm.com unsigned block_size = cacheLineSize(); 4096973Stjones1@inf.ed.ac.uk BaseTLB::Mode mode = BaseTLB::Read; 4102623SN/A 4117045Ssteve.reinhardt@amd.com if (traceData) { 4127045Ssteve.reinhardt@amd.com traceData->setAddr(addr); 4137045Ssteve.reinhardt@amd.com } 4147045Ssteve.reinhardt@amd.com 4157520Sgblack@eecs.umich.edu RequestPtr req = new Request(asid, addr, size, 4168832SAli.Saidi@ARM.com flags, dataMasterId(), pc, _cpuId, tid); 4175728Sgblack@eecs.umich.edu 4187520Sgblack@eecs.umich.edu Addr split_addr = roundDown(addr + size - 1, block_size); 4195744Sgblack@eecs.umich.edu assert(split_addr <= addr || split_addr - addr < block_size); 4205728Sgblack@eecs.umich.edu 4215894Sgblack@eecs.umich.edu _status = DTBWaitResponse; 4225744Sgblack@eecs.umich.edu if (split_addr > addr) { 4235894Sgblack@eecs.umich.edu RequestPtr req1, req2; 4246102Sgblack@eecs.umich.edu assert(!req->isLLSC() && !req->isSwap()); 4255894Sgblack@eecs.umich.edu req->splitOnVaddr(split_addr, req1, req2); 4265894Sgblack@eecs.umich.edu 4276973Stjones1@inf.ed.ac.uk WholeTranslationState *state = 4287520Sgblack@eecs.umich.edu new WholeTranslationState(req, req1, req2, new uint8_t[size], 4296973Stjones1@inf.ed.ac.uk NULL, mode); 4308486Sgblack@eecs.umich.edu DataTranslation<TimingSimpleCPU *> *trans1 = 4318486Sgblack@eecs.umich.edu new DataTranslation<TimingSimpleCPU *>(this, state, 0); 4328486Sgblack@eecs.umich.edu DataTranslation<TimingSimpleCPU *> *trans2 = 4338486Sgblack@eecs.umich.edu new DataTranslation<TimingSimpleCPU *>(this, state, 1); 4346973Stjones1@inf.ed.ac.uk 4356973Stjones1@inf.ed.ac.uk thread->dtb->translateTiming(req1, tc, trans1, mode); 4366973Stjones1@inf.ed.ac.uk thread->dtb->translateTiming(req2, tc, trans2, mode); 4375744Sgblack@eecs.umich.edu } else { 4386973Stjones1@inf.ed.ac.uk WholeTranslationState *state = 4397520Sgblack@eecs.umich.edu new WholeTranslationState(req, new uint8_t[size], NULL, mode); 4408486Sgblack@eecs.umich.edu DataTranslation<TimingSimpleCPU *> *translation 4418486Sgblack@eecs.umich.edu = new DataTranslation<TimingSimpleCPU *>(this, state); 4426973Stjones1@inf.ed.ac.uk thread->dtb->translateTiming(req, tc, translation, mode); 4432623SN/A } 4442623SN/A 4455728Sgblack@eecs.umich.edu return NoFault; 4462623SN/A} 4472623SN/A 4485728Sgblack@eecs.umich.edubool 4495728Sgblack@eecs.umich.eduTimingSimpleCPU::handleWritePacket() 4505728Sgblack@eecs.umich.edu{ 4515728Sgblack@eecs.umich.edu RequestPtr req = dcache_pkt->req; 4528105Sgblack@eecs.umich.edu if (req->isMmappedIpr()) { 4539180Sandreas.hansson@arm.com Cycles delay = TheISA::handleIprWrite(thread->getTC(), dcache_pkt); 4549179Sandreas.hansson@arm.com new IprEvent(dcache_pkt, this, clockEdge(delay)); 4555728Sgblack@eecs.umich.edu _status = DcacheWaitResponse; 4565728Sgblack@eecs.umich.edu dcache_pkt = NULL; 4578975Sandreas.hansson@arm.com } else if (!dcachePort.sendTimingReq(dcache_pkt)) { 4585728Sgblack@eecs.umich.edu _status = DcacheRetry; 4595728Sgblack@eecs.umich.edu } else { 4605728Sgblack@eecs.umich.edu _status = DcacheWaitResponse; 4615728Sgblack@eecs.umich.edu // memory system takes ownership of packet 4625728Sgblack@eecs.umich.edu dcache_pkt = NULL; 4635728Sgblack@eecs.umich.edu } 4645728Sgblack@eecs.umich.edu return dcache_pkt == NULL; 4655728Sgblack@eecs.umich.edu} 4662623SN/A 4672623SN/AFault 4688444Sgblack@eecs.umich.eduTimingSimpleCPU::writeMem(uint8_t *data, unsigned size, 4698444Sgblack@eecs.umich.edu Addr addr, unsigned flags, uint64_t *res) 4702623SN/A{ 4718443Sgblack@eecs.umich.edu uint8_t *newData = new uint8_t[size]; 4728443Sgblack@eecs.umich.edu memcpy(newData, data, size); 4738443Sgblack@eecs.umich.edu 4745728Sgblack@eecs.umich.edu const int asid = 0; 4756221Snate@binkert.org const ThreadID tid = 0; 4767720Sgblack@eecs.umich.edu const Addr pc = thread->instAddr(); 4779814Sandreas.hansson@arm.com unsigned block_size = cacheLineSize(); 4786973Stjones1@inf.ed.ac.uk BaseTLB::Mode mode = BaseTLB::Write; 4793169Sstever@eecs.umich.edu 4807045Ssteve.reinhardt@amd.com if (traceData) { 4817045Ssteve.reinhardt@amd.com traceData->setAddr(addr); 4827045Ssteve.reinhardt@amd.com } 4837045Ssteve.reinhardt@amd.com 4847520Sgblack@eecs.umich.edu RequestPtr req = new Request(asid, addr, size, 4858832SAli.Saidi@ARM.com flags, dataMasterId(), pc, _cpuId, tid); 4865728Sgblack@eecs.umich.edu 4877520Sgblack@eecs.umich.edu Addr split_addr = roundDown(addr + size - 1, block_size); 4885744Sgblack@eecs.umich.edu assert(split_addr <= addr || split_addr - addr < block_size); 4895728Sgblack@eecs.umich.edu 4905894Sgblack@eecs.umich.edu _status = DTBWaitResponse; 4915744Sgblack@eecs.umich.edu if (split_addr > addr) { 4925894Sgblack@eecs.umich.edu RequestPtr req1, req2; 4936102Sgblack@eecs.umich.edu assert(!req->isLLSC() && !req->isSwap()); 4945894Sgblack@eecs.umich.edu req->splitOnVaddr(split_addr, req1, req2); 4955894Sgblack@eecs.umich.edu 4966973Stjones1@inf.ed.ac.uk WholeTranslationState *state = 4978443Sgblack@eecs.umich.edu new WholeTranslationState(req, req1, req2, newData, res, mode); 4988486Sgblack@eecs.umich.edu DataTranslation<TimingSimpleCPU *> *trans1 = 4998486Sgblack@eecs.umich.edu new DataTranslation<TimingSimpleCPU *>(this, state, 0); 5008486Sgblack@eecs.umich.edu DataTranslation<TimingSimpleCPU *> *trans2 = 5018486Sgblack@eecs.umich.edu new DataTranslation<TimingSimpleCPU *>(this, state, 1); 5026973Stjones1@inf.ed.ac.uk 5036973Stjones1@inf.ed.ac.uk thread->dtb->translateTiming(req1, tc, trans1, mode); 5046973Stjones1@inf.ed.ac.uk thread->dtb->translateTiming(req2, tc, trans2, mode); 5055744Sgblack@eecs.umich.edu } else { 5066973Stjones1@inf.ed.ac.uk WholeTranslationState *state = 5078443Sgblack@eecs.umich.edu new WholeTranslationState(req, newData, res, mode); 5088486Sgblack@eecs.umich.edu DataTranslation<TimingSimpleCPU *> *translation = 5098486Sgblack@eecs.umich.edu new DataTranslation<TimingSimpleCPU *>(this, state); 5106973Stjones1@inf.ed.ac.uk thread->dtb->translateTiming(req, tc, translation, mode); 5112623SN/A } 5122623SN/A 5137045Ssteve.reinhardt@amd.com // Translation faults will be returned via finishTranslation() 5145728Sgblack@eecs.umich.edu return NoFault; 5152623SN/A} 5162623SN/A 5172623SN/A 5182623SN/Avoid 5196973Stjones1@inf.ed.ac.ukTimingSimpleCPU::finishTranslation(WholeTranslationState *state) 5206973Stjones1@inf.ed.ac.uk{ 5219342SAndreas.Sandberg@arm.com _status = BaseSimpleCPU::Running; 5226973Stjones1@inf.ed.ac.uk 5236973Stjones1@inf.ed.ac.uk if (state->getFault() != NoFault) { 5246973Stjones1@inf.ed.ac.uk if (state->isPrefetch()) { 5256973Stjones1@inf.ed.ac.uk state->setNoFault(); 5266973Stjones1@inf.ed.ac.uk } 5277691SAli.Saidi@ARM.com delete [] state->data; 5286973Stjones1@inf.ed.ac.uk state->deleteReqs(); 5296973Stjones1@inf.ed.ac.uk translationFault(state->getFault()); 5306973Stjones1@inf.ed.ac.uk } else { 5316973Stjones1@inf.ed.ac.uk if (!state->isSplit) { 5326973Stjones1@inf.ed.ac.uk sendData(state->mainReq, state->data, state->res, 5336973Stjones1@inf.ed.ac.uk state->mode == BaseTLB::Read); 5346973Stjones1@inf.ed.ac.uk } else { 5356973Stjones1@inf.ed.ac.uk sendSplitData(state->sreqLow, state->sreqHigh, state->mainReq, 5366973Stjones1@inf.ed.ac.uk state->data, state->mode == BaseTLB::Read); 5376973Stjones1@inf.ed.ac.uk } 5386973Stjones1@inf.ed.ac.uk } 5396973Stjones1@inf.ed.ac.uk 5406973Stjones1@inf.ed.ac.uk delete state; 5416973Stjones1@inf.ed.ac.uk} 5426973Stjones1@inf.ed.ac.uk 5436973Stjones1@inf.ed.ac.uk 5446973Stjones1@inf.ed.ac.ukvoid 5452623SN/ATimingSimpleCPU::fetch() 5462623SN/A{ 5475221Ssaidi@eecs.umich.edu DPRINTF(SimpleCPU, "Fetch\n"); 5485221Ssaidi@eecs.umich.edu 5493387Sgblack@eecs.umich.edu if (!curStaticInst || !curStaticInst->isDelayedCommit()) 5503387Sgblack@eecs.umich.edu checkForInterrupts(); 5512631SN/A 5525348Ssaidi@eecs.umich.edu checkPcEventQueue(); 5535348Ssaidi@eecs.umich.edu 5548143SAli.Saidi@ARM.com // We must have just got suspended by a PC event 5558143SAli.Saidi@ARM.com if (_status == Idle) 5568143SAli.Saidi@ARM.com return; 5578143SAli.Saidi@ARM.com 5587720Sgblack@eecs.umich.edu TheISA::PCState pcState = thread->pcState(); 5597720Sgblack@eecs.umich.edu bool needToFetch = !isRomMicroPC(pcState.microPC()) && !curMacroStaticInst; 5602623SN/A 5617720Sgblack@eecs.umich.edu if (needToFetch) { 5629342SAndreas.Sandberg@arm.com _status = BaseSimpleCPU::Running; 5635669Sgblack@eecs.umich.edu Request *ifetch_req = new Request(); 5645712Shsul@eecs.umich.edu ifetch_req->setThreadContext(_cpuId, /* thread ID */ 0); 5655894Sgblack@eecs.umich.edu setupFetchRequest(ifetch_req); 5668277SAli.Saidi@ARM.com DPRINTF(SimpleCPU, "Translating address %#x\n", ifetch_req->getVaddr()); 5676023Snate@binkert.org thread->itb->translateTiming(ifetch_req, tc, &fetchTranslation, 5686023Snate@binkert.org BaseTLB::Execute); 5692623SN/A } else { 5705669Sgblack@eecs.umich.edu _status = IcacheWaitResponse; 5715669Sgblack@eecs.umich.edu completeIfetch(NULL); 5725894Sgblack@eecs.umich.edu 5739179Sandreas.hansson@arm.com numCycles += curCycle() - previousCycle; 5749179Sandreas.hansson@arm.com previousCycle = curCycle(); 5755894Sgblack@eecs.umich.edu } 5765894Sgblack@eecs.umich.edu} 5775894Sgblack@eecs.umich.edu 5785894Sgblack@eecs.umich.edu 5795894Sgblack@eecs.umich.eduvoid 5805894Sgblack@eecs.umich.eduTimingSimpleCPU::sendFetch(Fault fault, RequestPtr req, ThreadContext *tc) 5815894Sgblack@eecs.umich.edu{ 5825894Sgblack@eecs.umich.edu if (fault == NoFault) { 5838277SAli.Saidi@ARM.com DPRINTF(SimpleCPU, "Sending fetch for addr %#x(pa: %#x)\n", 5848277SAli.Saidi@ARM.com req->getVaddr(), req->getPaddr()); 5858949Sandreas.hansson@arm.com ifetch_pkt = new Packet(req, MemCmd::ReadReq); 5865894Sgblack@eecs.umich.edu ifetch_pkt->dataStatic(&inst); 5878277SAli.Saidi@ARM.com DPRINTF(SimpleCPU, " -- pkt addr: %#x\n", ifetch_pkt->getAddr()); 5885894Sgblack@eecs.umich.edu 5898975Sandreas.hansson@arm.com if (!icachePort.sendTimingReq(ifetch_pkt)) { 5905894Sgblack@eecs.umich.edu // Need to wait for retry 5915894Sgblack@eecs.umich.edu _status = IcacheRetry; 5925894Sgblack@eecs.umich.edu } else { 5935894Sgblack@eecs.umich.edu // Need to wait for cache to respond 5945894Sgblack@eecs.umich.edu _status = IcacheWaitResponse; 5955894Sgblack@eecs.umich.edu // ownership of packet transferred to memory system 5965894Sgblack@eecs.umich.edu ifetch_pkt = NULL; 5975894Sgblack@eecs.umich.edu } 5985894Sgblack@eecs.umich.edu } else { 5998277SAli.Saidi@ARM.com DPRINTF(SimpleCPU, "Translation of addr %#x faulted\n", req->getVaddr()); 6005894Sgblack@eecs.umich.edu delete req; 6015894Sgblack@eecs.umich.edu // fetch fault: advance directly to next instruction (fault handler) 6029342SAndreas.Sandberg@arm.com _status = BaseSimpleCPU::Running; 6035894Sgblack@eecs.umich.edu advanceInst(fault); 6042623SN/A } 6053222Sktlim@umich.edu 6069179Sandreas.hansson@arm.com numCycles += curCycle() - previousCycle; 6079179Sandreas.hansson@arm.com previousCycle = curCycle(); 6082623SN/A} 6092623SN/A 6102623SN/A 6112623SN/Avoid 6122644Sstever@eecs.umich.eduTimingSimpleCPU::advanceInst(Fault fault) 6132623SN/A{ 6148276SAli.Saidi@ARM.com if (_status == Faulting) 6158276SAli.Saidi@ARM.com return; 6168276SAli.Saidi@ARM.com 6178276SAli.Saidi@ARM.com if (fault != NoFault) { 6188276SAli.Saidi@ARM.com advancePC(fault); 6198276SAli.Saidi@ARM.com DPRINTF(SimpleCPU, "Fault occured, scheduling fetch event\n"); 6209648Sdam.sunwoo@arm.com reschedule(fetchEvent, clockEdge(), true); 6218276SAli.Saidi@ARM.com _status = Faulting; 6228276SAli.Saidi@ARM.com return; 6238276SAli.Saidi@ARM.com } 6248276SAli.Saidi@ARM.com 6258276SAli.Saidi@ARM.com 6268276SAli.Saidi@ARM.com if (!stayAtPC) 6275726Sgblack@eecs.umich.edu advancePC(fault); 6282623SN/A 6299442SAndreas.Sandberg@ARM.com if (tryCompleteDrain()) 6309442SAndreas.Sandberg@ARM.com return; 6319442SAndreas.Sandberg@ARM.com 6329342SAndreas.Sandberg@arm.com if (_status == BaseSimpleCPU::Running) { 6332631SN/A // kick off fetch of next instruction... callback from icache 6342631SN/A // response will cause that instruction to be executed, 6352631SN/A // keeping the CPU running. 6362631SN/A fetch(); 6372631SN/A } 6382623SN/A} 6392623SN/A 6402623SN/A 6412623SN/Avoid 6423349Sbinkertn@umich.eduTimingSimpleCPU::completeIfetch(PacketPtr pkt) 6432623SN/A{ 6448277SAli.Saidi@ARM.com DPRINTF(SimpleCPU, "Complete ICache Fetch for addr %#x\n", pkt ? 6458277SAli.Saidi@ARM.com pkt->getAddr() : 0); 6468277SAli.Saidi@ARM.com 6472623SN/A // received a response from the icache: execute the received 6482623SN/A // instruction 6495669Sgblack@eecs.umich.edu assert(!pkt || !pkt->isError()); 6502623SN/A assert(_status == IcacheWaitResponse); 6512798Sktlim@umich.edu 6529342SAndreas.Sandberg@arm.com _status = BaseSimpleCPU::Running; 6532644Sstever@eecs.umich.edu 6549179Sandreas.hansson@arm.com numCycles += curCycle() - previousCycle; 6559179Sandreas.hansson@arm.com previousCycle = curCycle(); 6563222Sktlim@umich.edu 65710020Smatt.horsnell@ARM.com if (pkt) 65810020Smatt.horsnell@ARM.com pkt->req->setAccessLatency(); 65910020Smatt.horsnell@ARM.com 66010020Smatt.horsnell@ARM.com 6612623SN/A preExecute(); 6627725SAli.Saidi@ARM.com if (curStaticInst && curStaticInst->isMemRef()) { 6632623SN/A // load or store: just send to dcache 6642623SN/A Fault fault = curStaticInst->initiateAcc(this, traceData); 6657945SAli.Saidi@ARM.com 6667945SAli.Saidi@ARM.com // If we're not running now the instruction will complete in a dcache 6677945SAli.Saidi@ARM.com // response callback or the instruction faulted and has started an 6687945SAli.Saidi@ARM.com // ifetch 6699342SAndreas.Sandberg@arm.com if (_status == BaseSimpleCPU::Running) { 6705894Sgblack@eecs.umich.edu if (fault != NoFault && traceData) { 6715001Sgblack@eecs.umich.edu // If there was a fault, we shouldn't trace this instruction. 6725001Sgblack@eecs.umich.edu delete traceData; 6735001Sgblack@eecs.umich.edu traceData = NULL; 6743170Sstever@eecs.umich.edu } 6754998Sgblack@eecs.umich.edu 6762644Sstever@eecs.umich.edu postExecute(); 6775103Ssaidi@eecs.umich.edu // @todo remove me after debugging with legion done 6785103Ssaidi@eecs.umich.edu if (curStaticInst && (!curStaticInst->isMicroop() || 6795103Ssaidi@eecs.umich.edu curStaticInst->isFirstMicroop())) 6805103Ssaidi@eecs.umich.edu instCnt++; 6812644Sstever@eecs.umich.edu advanceInst(fault); 6822644Sstever@eecs.umich.edu } 6835726Sgblack@eecs.umich.edu } else if (curStaticInst) { 6842623SN/A // non-memory instruction: execute completely now 6852623SN/A Fault fault = curStaticInst->execute(this, traceData); 6864998Sgblack@eecs.umich.edu 6874998Sgblack@eecs.umich.edu // keep an instruction count 6884998Sgblack@eecs.umich.edu if (fault == NoFault) 6894998Sgblack@eecs.umich.edu countInst(); 6907655Sali.saidi@arm.com else if (traceData && !DTRACE(ExecFaulting)) { 6915001Sgblack@eecs.umich.edu delete traceData; 6925001Sgblack@eecs.umich.edu traceData = NULL; 6935001Sgblack@eecs.umich.edu } 6944998Sgblack@eecs.umich.edu 6952644Sstever@eecs.umich.edu postExecute(); 6965103Ssaidi@eecs.umich.edu // @todo remove me after debugging with legion done 6975103Ssaidi@eecs.umich.edu if (curStaticInst && (!curStaticInst->isMicroop() || 6985103Ssaidi@eecs.umich.edu curStaticInst->isFirstMicroop())) 6995103Ssaidi@eecs.umich.edu instCnt++; 7002644Sstever@eecs.umich.edu advanceInst(fault); 7015726Sgblack@eecs.umich.edu } else { 7025726Sgblack@eecs.umich.edu advanceInst(NoFault); 7032623SN/A } 7043658Sktlim@umich.edu 7055669Sgblack@eecs.umich.edu if (pkt) { 7065669Sgblack@eecs.umich.edu delete pkt->req; 7075669Sgblack@eecs.umich.edu delete pkt; 7085669Sgblack@eecs.umich.edu } 7092623SN/A} 7102623SN/A 7112948Ssaidi@eecs.umich.eduvoid 7122948Ssaidi@eecs.umich.eduTimingSimpleCPU::IcachePort::ITickEvent::process() 7132948Ssaidi@eecs.umich.edu{ 7142948Ssaidi@eecs.umich.edu cpu->completeIfetch(pkt); 7152948Ssaidi@eecs.umich.edu} 7162623SN/A 7172623SN/Abool 7188975Sandreas.hansson@arm.comTimingSimpleCPU::IcachePort::recvTimingResp(PacketPtr pkt) 7192623SN/A{ 7209165Sandreas.hansson@arm.com DPRINTF(SimpleCPU, "Received timing response %#x\n", pkt->getAddr()); 7219165Sandreas.hansson@arm.com // delay processing of returned data until next CPU clock edge 7229648Sdam.sunwoo@arm.com Tick next_tick = cpu->clockEdge(); 7232948Ssaidi@eecs.umich.edu 7249165Sandreas.hansson@arm.com if (next_tick == curTick()) 7259165Sandreas.hansson@arm.com cpu->completeIfetch(pkt); 7269165Sandreas.hansson@arm.com else 7279165Sandreas.hansson@arm.com tickEvent.schedule(pkt, next_tick); 7288948Sandreas.hansson@arm.com 7294433Ssaidi@eecs.umich.edu return true; 7302623SN/A} 7312623SN/A 7322657Ssaidi@eecs.umich.eduvoid 7332623SN/ATimingSimpleCPU::IcachePort::recvRetry() 7342623SN/A{ 7352623SN/A // we shouldn't get a retry unless we have a packet that we're 7362623SN/A // waiting to transmit 7372623SN/A assert(cpu->ifetch_pkt != NULL); 7382623SN/A assert(cpu->_status == IcacheRetry); 7393349Sbinkertn@umich.edu PacketPtr tmp = cpu->ifetch_pkt; 7408975Sandreas.hansson@arm.com if (sendTimingReq(tmp)) { 7412657Ssaidi@eecs.umich.edu cpu->_status = IcacheWaitResponse; 7422657Ssaidi@eecs.umich.edu cpu->ifetch_pkt = NULL; 7432657Ssaidi@eecs.umich.edu } 7442623SN/A} 7452623SN/A 7462623SN/Avoid 7473349Sbinkertn@umich.eduTimingSimpleCPU::completeDataAccess(PacketPtr pkt) 7482623SN/A{ 7492623SN/A // received a response from the dcache: complete the load or store 7502623SN/A // instruction 7514870Sstever@eecs.umich.edu assert(!pkt->isError()); 7527516Shestness@cs.utexas.edu assert(_status == DcacheWaitResponse || _status == DTBWaitResponse || 7537516Shestness@cs.utexas.edu pkt->req->getFlags().isSet(Request::NO_ACCESS)); 7542623SN/A 75510020Smatt.horsnell@ARM.com pkt->req->setAccessLatency(); 7569179Sandreas.hansson@arm.com numCycles += curCycle() - previousCycle; 7579179Sandreas.hansson@arm.com previousCycle = curCycle(); 7583184Srdreslin@umich.edu 7595728Sgblack@eecs.umich.edu if (pkt->senderState) { 7605728Sgblack@eecs.umich.edu SplitFragmentSenderState * send_state = 7615728Sgblack@eecs.umich.edu dynamic_cast<SplitFragmentSenderState *>(pkt->senderState); 7625728Sgblack@eecs.umich.edu assert(send_state); 7635728Sgblack@eecs.umich.edu delete pkt->req; 7645728Sgblack@eecs.umich.edu delete pkt; 7655728Sgblack@eecs.umich.edu PacketPtr big_pkt = send_state->bigPkt; 7665728Sgblack@eecs.umich.edu delete send_state; 7675728Sgblack@eecs.umich.edu 7685728Sgblack@eecs.umich.edu SplitMainSenderState * main_send_state = 7695728Sgblack@eecs.umich.edu dynamic_cast<SplitMainSenderState *>(big_pkt->senderState); 7705728Sgblack@eecs.umich.edu assert(main_send_state); 7715728Sgblack@eecs.umich.edu // Record the fact that this packet is no longer outstanding. 7725728Sgblack@eecs.umich.edu assert(main_send_state->outstanding != 0); 7735728Sgblack@eecs.umich.edu main_send_state->outstanding--; 7745728Sgblack@eecs.umich.edu 7755728Sgblack@eecs.umich.edu if (main_send_state->outstanding) { 7765728Sgblack@eecs.umich.edu return; 7775728Sgblack@eecs.umich.edu } else { 7785728Sgblack@eecs.umich.edu delete main_send_state; 7795728Sgblack@eecs.umich.edu big_pkt->senderState = NULL; 7805728Sgblack@eecs.umich.edu pkt = big_pkt; 7815728Sgblack@eecs.umich.edu } 7825728Sgblack@eecs.umich.edu } 7835728Sgblack@eecs.umich.edu 7849342SAndreas.Sandberg@arm.com _status = BaseSimpleCPU::Running; 7855728Sgblack@eecs.umich.edu 7862623SN/A Fault fault = curStaticInst->completeAcc(pkt, this, traceData); 7872623SN/A 7884998Sgblack@eecs.umich.edu // keep an instruction count 7894998Sgblack@eecs.umich.edu if (fault == NoFault) 7904998Sgblack@eecs.umich.edu countInst(); 7915001Sgblack@eecs.umich.edu else if (traceData) { 7925001Sgblack@eecs.umich.edu // If there was a fault, we shouldn't trace this instruction. 7935001Sgblack@eecs.umich.edu delete traceData; 7945001Sgblack@eecs.umich.edu traceData = NULL; 7955001Sgblack@eecs.umich.edu } 7964998Sgblack@eecs.umich.edu 7975507Sstever@gmail.com // the locked flag may be cleared on the response packet, so check 7985507Sstever@gmail.com // pkt->req and not pkt to see if it was a load-locked 7996102Sgblack@eecs.umich.edu if (pkt->isRead() && pkt->req->isLLSC()) { 8003170Sstever@eecs.umich.edu TheISA::handleLockedRead(thread, pkt->req); 8013170Sstever@eecs.umich.edu } 8023170Sstever@eecs.umich.edu 8032644Sstever@eecs.umich.edu delete pkt->req; 8042644Sstever@eecs.umich.edu delete pkt; 8052644Sstever@eecs.umich.edu 8063184Srdreslin@umich.edu postExecute(); 8073227Sktlim@umich.edu 8082644Sstever@eecs.umich.edu advanceInst(fault); 8092623SN/A} 8102623SN/A 8112623SN/Abool 8128975Sandreas.hansson@arm.comTimingSimpleCPU::DcachePort::recvTimingResp(PacketPtr pkt) 8132623SN/A{ 8149165Sandreas.hansson@arm.com // delay processing of returned data until next CPU clock edge 8159648Sdam.sunwoo@arm.com Tick next_tick = cpu->clockEdge(); 8162948Ssaidi@eecs.umich.edu 8179165Sandreas.hansson@arm.com if (next_tick == curTick()) { 8189165Sandreas.hansson@arm.com cpu->completeDataAccess(pkt); 8199165Sandreas.hansson@arm.com } else { 8209165Sandreas.hansson@arm.com if (!tickEvent.scheduled()) { 8219165Sandreas.hansson@arm.com tickEvent.schedule(pkt, next_tick); 8225728Sgblack@eecs.umich.edu } else { 8239165Sandreas.hansson@arm.com // In the case of a split transaction and a cache that is 8249165Sandreas.hansson@arm.com // faster than a CPU we could get two responses before 8259165Sandreas.hansson@arm.com // next_tick expires 8269165Sandreas.hansson@arm.com if (!retryEvent.scheduled()) 8279165Sandreas.hansson@arm.com cpu->schedule(retryEvent, next_tick); 8289165Sandreas.hansson@arm.com return false; 8294433Ssaidi@eecs.umich.edu } 8303310Srdreslin@umich.edu } 8318948Sandreas.hansson@arm.com 8324433Ssaidi@eecs.umich.edu return true; 8332948Ssaidi@eecs.umich.edu} 8342948Ssaidi@eecs.umich.edu 8352948Ssaidi@eecs.umich.eduvoid 8362948Ssaidi@eecs.umich.eduTimingSimpleCPU::DcachePort::DTickEvent::process() 8372948Ssaidi@eecs.umich.edu{ 8382630SN/A cpu->completeDataAccess(pkt); 8392623SN/A} 8402623SN/A 8412657Ssaidi@eecs.umich.eduvoid 8422623SN/ATimingSimpleCPU::DcachePort::recvRetry() 8432623SN/A{ 8442623SN/A // we shouldn't get a retry unless we have a packet that we're 8452623SN/A // waiting to transmit 8462623SN/A assert(cpu->dcache_pkt != NULL); 8472623SN/A assert(cpu->_status == DcacheRetry); 8483349Sbinkertn@umich.edu PacketPtr tmp = cpu->dcache_pkt; 8495728Sgblack@eecs.umich.edu if (tmp->senderState) { 8505728Sgblack@eecs.umich.edu // This is a packet from a split access. 8515728Sgblack@eecs.umich.edu SplitFragmentSenderState * send_state = 8525728Sgblack@eecs.umich.edu dynamic_cast<SplitFragmentSenderState *>(tmp->senderState); 8535728Sgblack@eecs.umich.edu assert(send_state); 8545728Sgblack@eecs.umich.edu PacketPtr big_pkt = send_state->bigPkt; 8555728Sgblack@eecs.umich.edu 8565728Sgblack@eecs.umich.edu SplitMainSenderState * main_send_state = 8575728Sgblack@eecs.umich.edu dynamic_cast<SplitMainSenderState *>(big_pkt->senderState); 8585728Sgblack@eecs.umich.edu assert(main_send_state); 8595728Sgblack@eecs.umich.edu 8608975Sandreas.hansson@arm.com if (sendTimingReq(tmp)) { 8615728Sgblack@eecs.umich.edu // If we were able to send without retrying, record that fact 8625728Sgblack@eecs.umich.edu // and try sending the other fragment. 8635728Sgblack@eecs.umich.edu send_state->clearFromParent(); 8645728Sgblack@eecs.umich.edu int other_index = main_send_state->getPendingFragment(); 8655728Sgblack@eecs.umich.edu if (other_index > 0) { 8665728Sgblack@eecs.umich.edu tmp = main_send_state->fragments[other_index]; 8675728Sgblack@eecs.umich.edu cpu->dcache_pkt = tmp; 8685728Sgblack@eecs.umich.edu if ((big_pkt->isRead() && cpu->handleReadPacket(tmp)) || 8695728Sgblack@eecs.umich.edu (big_pkt->isWrite() && cpu->handleWritePacket())) { 8705728Sgblack@eecs.umich.edu main_send_state->fragments[other_index] = NULL; 8715728Sgblack@eecs.umich.edu } 8725728Sgblack@eecs.umich.edu } else { 8735728Sgblack@eecs.umich.edu cpu->_status = DcacheWaitResponse; 8745728Sgblack@eecs.umich.edu // memory system takes ownership of packet 8755728Sgblack@eecs.umich.edu cpu->dcache_pkt = NULL; 8765728Sgblack@eecs.umich.edu } 8775728Sgblack@eecs.umich.edu } 8788975Sandreas.hansson@arm.com } else if (sendTimingReq(tmp)) { 8792657Ssaidi@eecs.umich.edu cpu->_status = DcacheWaitResponse; 8803170Sstever@eecs.umich.edu // memory system takes ownership of packet 8812657Ssaidi@eecs.umich.edu cpu->dcache_pkt = NULL; 8822657Ssaidi@eecs.umich.edu } 8832623SN/A} 8842623SN/A 8855606Snate@binkert.orgTimingSimpleCPU::IprEvent::IprEvent(Packet *_pkt, TimingSimpleCPU *_cpu, 8865606Snate@binkert.org Tick t) 8875606Snate@binkert.org : pkt(_pkt), cpu(_cpu) 8885103Ssaidi@eecs.umich.edu{ 8895606Snate@binkert.org cpu->schedule(this, t); 8905103Ssaidi@eecs.umich.edu} 8915103Ssaidi@eecs.umich.edu 8925103Ssaidi@eecs.umich.eduvoid 8935103Ssaidi@eecs.umich.eduTimingSimpleCPU::IprEvent::process() 8945103Ssaidi@eecs.umich.edu{ 8955103Ssaidi@eecs.umich.edu cpu->completeDataAccess(pkt); 8965103Ssaidi@eecs.umich.edu} 8975103Ssaidi@eecs.umich.edu 8985103Ssaidi@eecs.umich.educonst char * 8995336Shines@cs.fsu.eduTimingSimpleCPU::IprEvent::description() const 9005103Ssaidi@eecs.umich.edu{ 9015103Ssaidi@eecs.umich.edu return "Timing Simple CPU Delay IPR event"; 9025103Ssaidi@eecs.umich.edu} 9035103Ssaidi@eecs.umich.edu 9042623SN/A 9055315Sstever@gmail.comvoid 9065315Sstever@gmail.comTimingSimpleCPU::printAddr(Addr a) 9075315Sstever@gmail.com{ 9085315Sstever@gmail.com dcachePort.printAddr(a); 9095315Sstever@gmail.com} 9105315Sstever@gmail.com 9115315Sstever@gmail.com 9122623SN/A//////////////////////////////////////////////////////////////////////// 9132623SN/A// 9142623SN/A// TimingSimpleCPU Simulation Object 9152623SN/A// 9164762Snate@binkert.orgTimingSimpleCPU * 9174762Snate@binkert.orgTimingSimpleCPUParams::create() 9182623SN/A{ 9195529Snate@binkert.org numThreads = 1; 9208779Sgblack@eecs.umich.edu if (!FullSystem && workload.size() != 1) 9214762Snate@binkert.org panic("only one workload allowed"); 9225529Snate@binkert.org return new TimingSimpleCPU(this); 9232623SN/A} 924