simpoint.hh revision 10381:ab8b8601b6ff 
1/*
2 * Copyright (c) 2012-2014 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Dam Sunwoo
38 *          Curtis Dunham
39 */
40
41#ifndef __CPU_SIMPLE_PROBES_SIMPOINT_HH__
42#define __CPU_SIMPLE_PROBES_SIMPOINT_HH__
43
44#include "base/hashmap.hh"
45#include "cpu/simple_thread.hh"
46#include "params/SimPoint.hh"
47#include "sim/probe/probe.hh"
48
49/**
50 * Probe for SimPoints BBV generation
51 */
52
53/**
54 *  Start and end address of basic block for SimPoint profiling.
55 *  This structure is used to look up the hash table of BBVs.
56 *  - first: PC of first inst in basic block
57 *  - second: PC of last inst in basic block
58 */
59typedef std::pair<Addr, Addr> BasicBlockRange;
60
61/** Overload hash function for BasicBlockRange type */
62__hash_namespace_begin
63template <>
64struct hash<BasicBlockRange>
65{
66  public:
67    size_t operator()(const BasicBlockRange &bb) const {
68        return hash<Addr>()(bb.first + bb.second);
69    }
70};
71__hash_namespace_end
72
73class SimPoint : public ProbeListenerObject
74{
75  public:
76    SimPoint(const SimPointParams *params);
77    virtual ~SimPoint();
78
79    virtual void init();
80
81    virtual void regProbeListeners();
82
83    /**
84     * Profile basic blocks for SimPoints.
85     * Called at every macro inst to increment basic block inst counts and
86     * to profile block if end of block.
87     */
88    void profile(const std::pair<SimpleThread*, StaticInstPtr>&);
89
90  private:
91    /** SimPoint profiling interval size in instructions */
92    const uint64_t intervalSize;
93
94    /** Inst count in current basic block */
95    uint64_t intervalCount;
96    /** Excess inst count from previous interval*/
97    uint64_t intervalDrift;
98    /** Pointer to SimPoint BBV output stream */
99    std::ostream *simpointStream;
100
101    /** Basic Block information */
102    struct BBInfo {
103        /** Unique ID */
104        uint64_t id;
105        /** Num of static insts in BB */
106        uint64_t insts;
107        /** Accumulated dynamic inst count executed by BB */
108        uint64_t count;
109    };
110
111    /** Hash table containing all previously seen basic blocks */
112    m5::hash_map<BasicBlockRange, BBInfo> bbMap;
113    /** Currently executing basic block */
114    BasicBlockRange currentBBV;
115    /** inst count in current basic block */
116    uint64_t currentBBVInstCount;
117};
118
119#endif // __CPU_SIMPLE_PROBES_SIMPOINT_HH__
120