exec_context.hh revision 13622
110259SAndrew.Bardsley@arm.com/* 210259SAndrew.Bardsley@arm.com * Copyright (c) 2014-2017 ARM Limited 310259SAndrew.Bardsley@arm.com * All rights reserved 410259SAndrew.Bardsley@arm.com * 510259SAndrew.Bardsley@arm.com * The license below extends only to copyright in the software and shall 610259SAndrew.Bardsley@arm.com * not be construed as granting a license to any other intellectual 710259SAndrew.Bardsley@arm.com * property including but not limited to intellectual property relating 810259SAndrew.Bardsley@arm.com * to a hardware implementation of the functionality of the software 910259SAndrew.Bardsley@arm.com * licensed hereunder. You may use the software subject to the license 1010259SAndrew.Bardsley@arm.com * terms below provided that you ensure that this notice is replicated 1110259SAndrew.Bardsley@arm.com * unmodified and in its entirety in all distributions of the software, 1210259SAndrew.Bardsley@arm.com * modified or unmodified, in source code or in binary form. 1310259SAndrew.Bardsley@arm.com * 1410259SAndrew.Bardsley@arm.com * Copyright (c) 2002-2005 The Regents of The University of Michigan 1510259SAndrew.Bardsley@arm.com * All rights reserved. 1610259SAndrew.Bardsley@arm.com * 1710259SAndrew.Bardsley@arm.com * Redistribution and use in source and binary forms, with or without 1810259SAndrew.Bardsley@arm.com * modification, are permitted provided that the following conditions are 1910259SAndrew.Bardsley@arm.com * met: redistributions of source code must retain the above copyright 2010259SAndrew.Bardsley@arm.com * notice, this list of conditions and the following disclaimer; 2110259SAndrew.Bardsley@arm.com * redistributions in binary form must reproduce the above copyright 2210259SAndrew.Bardsley@arm.com * notice, this list of conditions and the following disclaimer in the 2310259SAndrew.Bardsley@arm.com * documentation and/or other materials provided with the distribution; 2410259SAndrew.Bardsley@arm.com * neither the name of the copyright holders nor the names of its 2510259SAndrew.Bardsley@arm.com * contributors may be used to endorse or promote products derived from 2610259SAndrew.Bardsley@arm.com * this software without specific prior written permission. 2710259SAndrew.Bardsley@arm.com * 2810259SAndrew.Bardsley@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2910259SAndrew.Bardsley@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 3010259SAndrew.Bardsley@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 3110259SAndrew.Bardsley@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 3210259SAndrew.Bardsley@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3310259SAndrew.Bardsley@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3410259SAndrew.Bardsley@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3510259SAndrew.Bardsley@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3610259SAndrew.Bardsley@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3710259SAndrew.Bardsley@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3810259SAndrew.Bardsley@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3910259SAndrew.Bardsley@arm.com * 4010259SAndrew.Bardsley@arm.com * Authors: Kevin Lim 4110259SAndrew.Bardsley@arm.com * Andreas Sandberg 4210259SAndrew.Bardsley@arm.com * Mitch Hayenga 4310259SAndrew.Bardsley@arm.com */ 4410259SAndrew.Bardsley@arm.com 4510259SAndrew.Bardsley@arm.com#ifndef __CPU_SIMPLE_EXEC_CONTEXT_HH__ 4610259SAndrew.Bardsley@arm.com#define __CPU_SIMPLE_EXEC_CONTEXT_HH__ 4710259SAndrew.Bardsley@arm.com 4810259SAndrew.Bardsley@arm.com#include "arch/registers.hh" 4910259SAndrew.Bardsley@arm.com#include "base/types.hh" 5010259SAndrew.Bardsley@arm.com#include "config/the_isa.hh" 5110259SAndrew.Bardsley@arm.com#include "cpu/base.hh" 5210259SAndrew.Bardsley@arm.com#include "cpu/exec_context.hh" 5310259SAndrew.Bardsley@arm.com#include "cpu/reg_class.hh" 5410259SAndrew.Bardsley@arm.com#include "cpu/simple/base.hh" 5510259SAndrew.Bardsley@arm.com#include "cpu/static_inst_fwd.hh" 5610259SAndrew.Bardsley@arm.com#include "cpu/translation.hh" 5710259SAndrew.Bardsley@arm.com#include "mem/request.hh" 5810259SAndrew.Bardsley@arm.com 5910259SAndrew.Bardsley@arm.comclass BaseSimpleCPU; 6010259SAndrew.Bardsley@arm.com 6110259SAndrew.Bardsley@arm.comclass SimpleExecContext : public ExecContext { 6210259SAndrew.Bardsley@arm.com protected: 6310259SAndrew.Bardsley@arm.com using VecRegContainer = TheISA::VecRegContainer; 6410259SAndrew.Bardsley@arm.com using VecElem = TheISA::VecElem; 6510259SAndrew.Bardsley@arm.com 6610259SAndrew.Bardsley@arm.com public: 6710259SAndrew.Bardsley@arm.com BaseSimpleCPU *cpu; 6810259SAndrew.Bardsley@arm.com SimpleThread* thread; 6910259SAndrew.Bardsley@arm.com 7010259SAndrew.Bardsley@arm.com // This is the offset from the current pc that fetch should be performed 7110259SAndrew.Bardsley@arm.com Addr fetchOffset; 7210259SAndrew.Bardsley@arm.com // This flag says to stay at the current pc. This is useful for 7310259SAndrew.Bardsley@arm.com // instructions which go beyond MachInst boundaries. 7410259SAndrew.Bardsley@arm.com bool stayAtPC; 7510259SAndrew.Bardsley@arm.com 7610259SAndrew.Bardsley@arm.com // Branch prediction 7710259SAndrew.Bardsley@arm.com TheISA::PCState predPC; 7810259SAndrew.Bardsley@arm.com 7910259SAndrew.Bardsley@arm.com /** PER-THREAD STATS */ 8010259SAndrew.Bardsley@arm.com 8110259SAndrew.Bardsley@arm.com // Number of simulated instructions 8210259SAndrew.Bardsley@arm.com Counter numInst; 8310259SAndrew.Bardsley@arm.com Stats::Scalar numInsts; 8410259SAndrew.Bardsley@arm.com Counter numOp; 8510259SAndrew.Bardsley@arm.com Stats::Scalar numOps; 8610259SAndrew.Bardsley@arm.com 8710259SAndrew.Bardsley@arm.com // Number of integer alu accesses 8810259SAndrew.Bardsley@arm.com Stats::Scalar numIntAluAccesses; 8910259SAndrew.Bardsley@arm.com 9010259SAndrew.Bardsley@arm.com // Number of float alu accesses 9110259SAndrew.Bardsley@arm.com Stats::Scalar numFpAluAccesses; 9210259SAndrew.Bardsley@arm.com 9310259SAndrew.Bardsley@arm.com // Number of vector alu accesses 9410259SAndrew.Bardsley@arm.com Stats::Scalar numVecAluAccesses; 9510259SAndrew.Bardsley@arm.com 9610259SAndrew.Bardsley@arm.com // Number of function calls/returns 9710259SAndrew.Bardsley@arm.com Stats::Scalar numCallsReturns; 9810259SAndrew.Bardsley@arm.com 9910259SAndrew.Bardsley@arm.com // Conditional control instructions; 10010259SAndrew.Bardsley@arm.com Stats::Scalar numCondCtrlInsts; 10110259SAndrew.Bardsley@arm.com 10210259SAndrew.Bardsley@arm.com // Number of int instructions 10310259SAndrew.Bardsley@arm.com Stats::Scalar numIntInsts; 10410259SAndrew.Bardsley@arm.com 10510259SAndrew.Bardsley@arm.com // Number of float instructions 10610259SAndrew.Bardsley@arm.com Stats::Scalar numFpInsts; 10710259SAndrew.Bardsley@arm.com 10810259SAndrew.Bardsley@arm.com // Number of vector instructions 10910259SAndrew.Bardsley@arm.com Stats::Scalar numVecInsts; 11010259SAndrew.Bardsley@arm.com 11110259SAndrew.Bardsley@arm.com // Number of integer register file accesses 11210259SAndrew.Bardsley@arm.com Stats::Scalar numIntRegReads; 11310259SAndrew.Bardsley@arm.com Stats::Scalar numIntRegWrites; 11410259SAndrew.Bardsley@arm.com 11510259SAndrew.Bardsley@arm.com // Number of float register file accesses 11610259SAndrew.Bardsley@arm.com Stats::Scalar numFpRegReads; 11710259SAndrew.Bardsley@arm.com Stats::Scalar numFpRegWrites; 11810259SAndrew.Bardsley@arm.com 11910259SAndrew.Bardsley@arm.com // Number of vector register file accesses 12010259SAndrew.Bardsley@arm.com mutable Stats::Scalar numVecRegReads; 12110259SAndrew.Bardsley@arm.com Stats::Scalar numVecRegWrites; 12210259SAndrew.Bardsley@arm.com 12310259SAndrew.Bardsley@arm.com // Number of predicate register file accesses 12410259SAndrew.Bardsley@arm.com mutable Stats::Scalar numVecPredRegReads; 12510259SAndrew.Bardsley@arm.com Stats::Scalar numVecPredRegWrites; 12610259SAndrew.Bardsley@arm.com 12710259SAndrew.Bardsley@arm.com // Number of condition code register file accesses 12810259SAndrew.Bardsley@arm.com Stats::Scalar numCCRegReads; 12910259SAndrew.Bardsley@arm.com Stats::Scalar numCCRegWrites; 13010259SAndrew.Bardsley@arm.com 13110259SAndrew.Bardsley@arm.com // Number of simulated memory references 13210259SAndrew.Bardsley@arm.com Stats::Scalar numMemRefs; 13310259SAndrew.Bardsley@arm.com Stats::Scalar numLoadInsts; 13410259SAndrew.Bardsley@arm.com Stats::Scalar numStoreInsts; 13510259SAndrew.Bardsley@arm.com 13610259SAndrew.Bardsley@arm.com // Number of idle cycles 13710259SAndrew.Bardsley@arm.com Stats::Formula numIdleCycles; 13810259SAndrew.Bardsley@arm.com 13910259SAndrew.Bardsley@arm.com // Number of busy cycles 14010259SAndrew.Bardsley@arm.com Stats::Formula numBusyCycles; 14110259SAndrew.Bardsley@arm.com 14210259SAndrew.Bardsley@arm.com // Number of simulated loads 14310259SAndrew.Bardsley@arm.com Counter numLoad; 14410259SAndrew.Bardsley@arm.com 14510259SAndrew.Bardsley@arm.com // Number of idle cycles 14610259SAndrew.Bardsley@arm.com Stats::Average notIdleFraction; 14710259SAndrew.Bardsley@arm.com Stats::Formula idleFraction; 14810259SAndrew.Bardsley@arm.com 14910259SAndrew.Bardsley@arm.com // Number of cycles stalled for I-cache responses 15010259SAndrew.Bardsley@arm.com Stats::Scalar icacheStallCycles; 15110259SAndrew.Bardsley@arm.com Counter lastIcacheStall; 15210259SAndrew.Bardsley@arm.com 15310259SAndrew.Bardsley@arm.com // Number of cycles stalled for D-cache responses 15410259SAndrew.Bardsley@arm.com Stats::Scalar dcacheStallCycles; 15510259SAndrew.Bardsley@arm.com Counter lastDcacheStall; 15610259SAndrew.Bardsley@arm.com 15710259SAndrew.Bardsley@arm.com /// @{ 15810259SAndrew.Bardsley@arm.com /// Total number of branches fetched 15910259SAndrew.Bardsley@arm.com Stats::Scalar numBranches; 16010259SAndrew.Bardsley@arm.com /// Number of branches predicted as taken 16110259SAndrew.Bardsley@arm.com Stats::Scalar numPredictedBranches; 16210259SAndrew.Bardsley@arm.com /// Number of misprediced branches 16310259SAndrew.Bardsley@arm.com Stats::Scalar numBranchMispred; 16410259SAndrew.Bardsley@arm.com /// @} 16510259SAndrew.Bardsley@arm.com 16610259SAndrew.Bardsley@arm.com // Instruction mix histogram by OpClass 16710259SAndrew.Bardsley@arm.com Stats::Vector statExecutedInstType; 16810259SAndrew.Bardsley@arm.com 16910259SAndrew.Bardsley@arm.com public: 17010259SAndrew.Bardsley@arm.com /** Constructor */ 17110259SAndrew.Bardsley@arm.com SimpleExecContext(BaseSimpleCPU* _cpu, SimpleThread* _thread) 17210259SAndrew.Bardsley@arm.com : cpu(_cpu), thread(_thread), fetchOffset(0), stayAtPC(false), 17310259SAndrew.Bardsley@arm.com numInst(0), numOp(0), numLoad(0), lastIcacheStall(0), lastDcacheStall(0) 17410259SAndrew.Bardsley@arm.com { } 17510259SAndrew.Bardsley@arm.com 17610259SAndrew.Bardsley@arm.com /** Reads an integer register. */ 17710259SAndrew.Bardsley@arm.com RegVal 17810259SAndrew.Bardsley@arm.com readIntRegOperand(const StaticInst *si, int idx) override 17910259SAndrew.Bardsley@arm.com { 18010259SAndrew.Bardsley@arm.com numIntRegReads++; 18110259SAndrew.Bardsley@arm.com const RegId& reg = si->srcRegIdx(idx); 18210259SAndrew.Bardsley@arm.com assert(reg.isIntReg()); 18310259SAndrew.Bardsley@arm.com return thread->readIntReg(reg.index()); 18410259SAndrew.Bardsley@arm.com } 18510259SAndrew.Bardsley@arm.com 18610259SAndrew.Bardsley@arm.com /** Sets an integer register to a value. */ 18710259SAndrew.Bardsley@arm.com void 18810259SAndrew.Bardsley@arm.com setIntRegOperand(const StaticInst *si, int idx, RegVal val) override 18910259SAndrew.Bardsley@arm.com { 19010259SAndrew.Bardsley@arm.com numIntRegWrites++; 19110259SAndrew.Bardsley@arm.com const RegId& reg = si->destRegIdx(idx); 19210259SAndrew.Bardsley@arm.com assert(reg.isIntReg()); 19310259SAndrew.Bardsley@arm.com thread->setIntReg(reg.index(), val); 19410259SAndrew.Bardsley@arm.com } 19510259SAndrew.Bardsley@arm.com 19610259SAndrew.Bardsley@arm.com /** Reads a floating point register in its binary format, instead 19710259SAndrew.Bardsley@arm.com * of by value. */ 19810259SAndrew.Bardsley@arm.com RegVal 19910259SAndrew.Bardsley@arm.com readFloatRegOperandBits(const StaticInst *si, int idx) override 20010259SAndrew.Bardsley@arm.com { 20110259SAndrew.Bardsley@arm.com numFpRegReads++; 20210259SAndrew.Bardsley@arm.com const RegId& reg = si->srcRegIdx(idx); 20310259SAndrew.Bardsley@arm.com assert(reg.isFloatReg()); 20410259SAndrew.Bardsley@arm.com return thread->readFloatReg(reg.index()); 20510259SAndrew.Bardsley@arm.com } 20610259SAndrew.Bardsley@arm.com 20710259SAndrew.Bardsley@arm.com /** Sets the bits of a floating point register of single width 20810259SAndrew.Bardsley@arm.com * to a binary value. */ 20910259SAndrew.Bardsley@arm.com void 21010259SAndrew.Bardsley@arm.com setFloatRegOperandBits(const StaticInst *si, int idx, RegVal val) override 21110259SAndrew.Bardsley@arm.com { 21210259SAndrew.Bardsley@arm.com numFpRegWrites++; 21310259SAndrew.Bardsley@arm.com const RegId& reg = si->destRegIdx(idx); 21410259SAndrew.Bardsley@arm.com assert(reg.isFloatReg()); 21510259SAndrew.Bardsley@arm.com thread->setFloatReg(reg.index(), val); 21610259SAndrew.Bardsley@arm.com } 21710259SAndrew.Bardsley@arm.com 21810259SAndrew.Bardsley@arm.com /** Reads a vector register. */ 21910259SAndrew.Bardsley@arm.com const VecRegContainer & 22010259SAndrew.Bardsley@arm.com readVecRegOperand(const StaticInst *si, int idx) const override 22110259SAndrew.Bardsley@arm.com { 22210259SAndrew.Bardsley@arm.com numVecRegReads++; 22310259SAndrew.Bardsley@arm.com const RegId& reg = si->srcRegIdx(idx); 22410259SAndrew.Bardsley@arm.com assert(reg.isVecReg()); 22510259SAndrew.Bardsley@arm.com return thread->readVecReg(reg); 22610259SAndrew.Bardsley@arm.com } 22710259SAndrew.Bardsley@arm.com 22810259SAndrew.Bardsley@arm.com /** Reads a vector register for modification. */ 22910379Sandreas.hansson@arm.com VecRegContainer & 23010379Sandreas.hansson@arm.com getWritableVecRegOperand(const StaticInst *si, int idx) override 23110259SAndrew.Bardsley@arm.com { 23210259SAndrew.Bardsley@arm.com numVecRegWrites++; 23310259SAndrew.Bardsley@arm.com const RegId& reg = si->destRegIdx(idx); 23410259SAndrew.Bardsley@arm.com assert(reg.isVecReg()); 23510259SAndrew.Bardsley@arm.com return thread->getWritableVecReg(reg); 23610259SAndrew.Bardsley@arm.com } 23710259SAndrew.Bardsley@arm.com 23810259SAndrew.Bardsley@arm.com /** Sets a vector register to a value. */ 23910259SAndrew.Bardsley@arm.com void 24010259SAndrew.Bardsley@arm.com setVecRegOperand(const StaticInst *si, int idx, 24110259SAndrew.Bardsley@arm.com const VecRegContainer& val) override 24210259SAndrew.Bardsley@arm.com { 24310259SAndrew.Bardsley@arm.com numVecRegWrites++; 24410259SAndrew.Bardsley@arm.com const RegId& reg = si->destRegIdx(idx); 24510259SAndrew.Bardsley@arm.com assert(reg.isVecReg()); 24610259SAndrew.Bardsley@arm.com thread->setVecReg(reg, val); 24710259SAndrew.Bardsley@arm.com } 24810259SAndrew.Bardsley@arm.com 24910259SAndrew.Bardsley@arm.com /** Vector Register Lane Interfaces. */ 25010259SAndrew.Bardsley@arm.com /** @{ */ 25110259SAndrew.Bardsley@arm.com /** Reads source vector lane. */ 25210259SAndrew.Bardsley@arm.com template <typename VecElem> 25310259SAndrew.Bardsley@arm.com VecLaneT<VecElem, true> 25410259SAndrew.Bardsley@arm.com readVecLaneOperand(const StaticInst *si, int idx) const 25510259SAndrew.Bardsley@arm.com { 25610259SAndrew.Bardsley@arm.com numVecRegReads++; 25710259SAndrew.Bardsley@arm.com const RegId& reg = si->srcRegIdx(idx); 25810259SAndrew.Bardsley@arm.com assert(reg.isVecReg()); 25910259SAndrew.Bardsley@arm.com return thread->readVecLane<VecElem>(reg); 26010259SAndrew.Bardsley@arm.com } 26110259SAndrew.Bardsley@arm.com /** Reads source vector 8bit operand. */ 26210259SAndrew.Bardsley@arm.com virtual ConstVecLane8 26310259SAndrew.Bardsley@arm.com readVec8BitLaneOperand(const StaticInst *si, int idx) const 26410259SAndrew.Bardsley@arm.com override 26510259SAndrew.Bardsley@arm.com { return readVecLaneOperand<uint8_t>(si, idx); } 26610259SAndrew.Bardsley@arm.com 26710259SAndrew.Bardsley@arm.com /** Reads source vector 16bit operand. */ 26810259SAndrew.Bardsley@arm.com virtual ConstVecLane16 26910259SAndrew.Bardsley@arm.com readVec16BitLaneOperand(const StaticInst *si, int idx) const 27010259SAndrew.Bardsley@arm.com override 27110259SAndrew.Bardsley@arm.com { return readVecLaneOperand<uint16_t>(si, idx); } 27210259SAndrew.Bardsley@arm.com 27310259SAndrew.Bardsley@arm.com /** Reads source vector 32bit operand. */ 27410259SAndrew.Bardsley@arm.com virtual ConstVecLane32 27510259SAndrew.Bardsley@arm.com readVec32BitLaneOperand(const StaticInst *si, int idx) const 27610379Sandreas.hansson@arm.com override 27710379Sandreas.hansson@arm.com { return readVecLaneOperand<uint32_t>(si, idx); } 27810259SAndrew.Bardsley@arm.com 27910259SAndrew.Bardsley@arm.com /** Reads source vector 64bit operand. */ 28010259SAndrew.Bardsley@arm.com virtual ConstVecLane64 28110259SAndrew.Bardsley@arm.com readVec64BitLaneOperand(const StaticInst *si, int idx) const 28210259SAndrew.Bardsley@arm.com override 28310259SAndrew.Bardsley@arm.com { return readVecLaneOperand<uint64_t>(si, idx); } 28410259SAndrew.Bardsley@arm.com 28510259SAndrew.Bardsley@arm.com /** Write a lane of the destination vector operand. */ 28610259SAndrew.Bardsley@arm.com template <typename LD> 28710259SAndrew.Bardsley@arm.com void 28810259SAndrew.Bardsley@arm.com setVecLaneOperandT(const StaticInst *si, int idx, 28910259SAndrew.Bardsley@arm.com const LD& val) 29010259SAndrew.Bardsley@arm.com { 29110259SAndrew.Bardsley@arm.com numVecRegWrites++; 29210259SAndrew.Bardsley@arm.com const RegId& reg = si->destRegIdx(idx); 29310259SAndrew.Bardsley@arm.com assert(reg.isVecReg()); 29410259SAndrew.Bardsley@arm.com return thread->setVecLane(reg, val); 29510259SAndrew.Bardsley@arm.com } 29610259SAndrew.Bardsley@arm.com /** Write a lane of the destination vector operand. */ 29710259SAndrew.Bardsley@arm.com virtual void 29810259SAndrew.Bardsley@arm.com setVecLaneOperand(const StaticInst *si, int idx, 29910259SAndrew.Bardsley@arm.com const LaneData<LaneSize::Byte>& val) override 30010259SAndrew.Bardsley@arm.com { return setVecLaneOperandT(si, idx, val); } 30110259SAndrew.Bardsley@arm.com /** Write a lane of the destination vector operand. */ 30210259SAndrew.Bardsley@arm.com virtual void 30310259SAndrew.Bardsley@arm.com setVecLaneOperand(const StaticInst *si, int idx, 30410259SAndrew.Bardsley@arm.com const LaneData<LaneSize::TwoByte>& val) override 30510259SAndrew.Bardsley@arm.com { return setVecLaneOperandT(si, idx, val); } 30610259SAndrew.Bardsley@arm.com /** Write a lane of the destination vector operand. */ 30710259SAndrew.Bardsley@arm.com virtual void 30810259SAndrew.Bardsley@arm.com setVecLaneOperand(const StaticInst *si, int idx, 30910259SAndrew.Bardsley@arm.com const LaneData<LaneSize::FourByte>& val) override 31010259SAndrew.Bardsley@arm.com { return setVecLaneOperandT(si, idx, val); } 31110259SAndrew.Bardsley@arm.com /** Write a lane of the destination vector operand. */ 31210259SAndrew.Bardsley@arm.com virtual void 31310259SAndrew.Bardsley@arm.com setVecLaneOperand(const StaticInst *si, int idx, 31410259SAndrew.Bardsley@arm.com const LaneData<LaneSize::EightByte>& val) override 31510259SAndrew.Bardsley@arm.com { return setVecLaneOperandT(si, idx, val); } 31610259SAndrew.Bardsley@arm.com /** @} */ 31710259SAndrew.Bardsley@arm.com 31810259SAndrew.Bardsley@arm.com /** Reads an element of a vector register. */ 31910259SAndrew.Bardsley@arm.com VecElem 32010259SAndrew.Bardsley@arm.com readVecElemOperand(const StaticInst *si, int idx) const override 32110259SAndrew.Bardsley@arm.com { 32210259SAndrew.Bardsley@arm.com numVecRegReads++; 32310259SAndrew.Bardsley@arm.com const RegId& reg = si->srcRegIdx(idx); 32410259SAndrew.Bardsley@arm.com assert(reg.isVecElem()); 32510259SAndrew.Bardsley@arm.com return thread->readVecElem(reg); 32610259SAndrew.Bardsley@arm.com } 32710259SAndrew.Bardsley@arm.com 32810259SAndrew.Bardsley@arm.com /** Sets an element of a vector register to a value. */ 32910259SAndrew.Bardsley@arm.com void 33010259SAndrew.Bardsley@arm.com setVecElemOperand(const StaticInst *si, int idx, 33110259SAndrew.Bardsley@arm.com const VecElem val) override 33210259SAndrew.Bardsley@arm.com { 33310259SAndrew.Bardsley@arm.com numVecRegWrites++; 33410259SAndrew.Bardsley@arm.com const RegId& reg = si->destRegIdx(idx); 33510259SAndrew.Bardsley@arm.com assert(reg.isVecElem()); 33610259SAndrew.Bardsley@arm.com thread->setVecElem(reg, val); 33710259SAndrew.Bardsley@arm.com } 33810259SAndrew.Bardsley@arm.com 33910259SAndrew.Bardsley@arm.com const VecPredRegContainer& 34010259SAndrew.Bardsley@arm.com readVecPredRegOperand(const StaticInst *si, int idx) const override 34110259SAndrew.Bardsley@arm.com { 34210259SAndrew.Bardsley@arm.com numVecPredRegReads++; 34310259SAndrew.Bardsley@arm.com const RegId& reg = si->srcRegIdx(idx); 34410259SAndrew.Bardsley@arm.com assert(reg.isVecPredReg()); 34510259SAndrew.Bardsley@arm.com return thread->readVecPredReg(reg); 34610259SAndrew.Bardsley@arm.com } 34710259SAndrew.Bardsley@arm.com 34810259SAndrew.Bardsley@arm.com VecPredRegContainer& 34910259SAndrew.Bardsley@arm.com getWritableVecPredRegOperand(const StaticInst *si, int idx) override 35010259SAndrew.Bardsley@arm.com { 35110259SAndrew.Bardsley@arm.com numVecPredRegWrites++; 35210259SAndrew.Bardsley@arm.com const RegId& reg = si->destRegIdx(idx); 35310259SAndrew.Bardsley@arm.com assert(reg.isVecPredReg()); 35410259SAndrew.Bardsley@arm.com return thread->getWritableVecPredReg(reg); 35510259SAndrew.Bardsley@arm.com } 35610259SAndrew.Bardsley@arm.com 35710259SAndrew.Bardsley@arm.com void 35810259SAndrew.Bardsley@arm.com setVecPredRegOperand(const StaticInst *si, int idx, 35910259SAndrew.Bardsley@arm.com const VecPredRegContainer& val) override 36010259SAndrew.Bardsley@arm.com { 36110259SAndrew.Bardsley@arm.com numVecPredRegWrites++; 36210259SAndrew.Bardsley@arm.com const RegId& reg = si->destRegIdx(idx); 36310259SAndrew.Bardsley@arm.com assert(reg.isVecPredReg()); 36410259SAndrew.Bardsley@arm.com thread->setVecPredReg(reg, val); 36510259SAndrew.Bardsley@arm.com } 36610259SAndrew.Bardsley@arm.com 36710259SAndrew.Bardsley@arm.com RegVal 36810259SAndrew.Bardsley@arm.com readCCRegOperand(const StaticInst *si, int idx) override 36910259SAndrew.Bardsley@arm.com { 37010259SAndrew.Bardsley@arm.com numCCRegReads++; 37110259SAndrew.Bardsley@arm.com const RegId& reg = si->srcRegIdx(idx); 37210259SAndrew.Bardsley@arm.com assert(reg.isCCReg()); 37310259SAndrew.Bardsley@arm.com return thread->readCCReg(reg.index()); 37410259SAndrew.Bardsley@arm.com } 37510259SAndrew.Bardsley@arm.com 37610259SAndrew.Bardsley@arm.com void 37710259SAndrew.Bardsley@arm.com setCCRegOperand(const StaticInst *si, int idx, RegVal val) override 37810259SAndrew.Bardsley@arm.com { 37910259SAndrew.Bardsley@arm.com numCCRegWrites++; 38010259SAndrew.Bardsley@arm.com const RegId& reg = si->destRegIdx(idx); 38110259SAndrew.Bardsley@arm.com assert(reg.isCCReg()); 38210259SAndrew.Bardsley@arm.com thread->setCCReg(reg.index(), val); 38310259SAndrew.Bardsley@arm.com } 38410259SAndrew.Bardsley@arm.com 38510259SAndrew.Bardsley@arm.com RegVal 38610259SAndrew.Bardsley@arm.com readMiscRegOperand(const StaticInst *si, int idx) override 38710259SAndrew.Bardsley@arm.com { 38810259SAndrew.Bardsley@arm.com numIntRegReads++; 38910259SAndrew.Bardsley@arm.com const RegId& reg = si->srcRegIdx(idx); 39010259SAndrew.Bardsley@arm.com assert(reg.isMiscReg()); 39110259SAndrew.Bardsley@arm.com return thread->readMiscReg(reg.index()); 39210259SAndrew.Bardsley@arm.com } 39310259SAndrew.Bardsley@arm.com 39410259SAndrew.Bardsley@arm.com void 39510259SAndrew.Bardsley@arm.com setMiscRegOperand(const StaticInst *si, int idx, RegVal val) override 39610259SAndrew.Bardsley@arm.com { 39710259SAndrew.Bardsley@arm.com numIntRegWrites++; 39810259SAndrew.Bardsley@arm.com const RegId& reg = si->destRegIdx(idx); 39910259SAndrew.Bardsley@arm.com assert(reg.isMiscReg()); 40010259SAndrew.Bardsley@arm.com thread->setMiscReg(reg.index(), val); 40110259SAndrew.Bardsley@arm.com } 40210259SAndrew.Bardsley@arm.com 40310259SAndrew.Bardsley@arm.com /** 40410259SAndrew.Bardsley@arm.com * Reads a miscellaneous register, handling any architectural 40510259SAndrew.Bardsley@arm.com * side effects due to reading that register. 40610259SAndrew.Bardsley@arm.com */ 40710259SAndrew.Bardsley@arm.com RegVal 40810259SAndrew.Bardsley@arm.com readMiscReg(int misc_reg) override 40910259SAndrew.Bardsley@arm.com { 41010259SAndrew.Bardsley@arm.com numIntRegReads++; 41110259SAndrew.Bardsley@arm.com return thread->readMiscReg(misc_reg); 41210259SAndrew.Bardsley@arm.com } 41310259SAndrew.Bardsley@arm.com 41410259SAndrew.Bardsley@arm.com /** 41510259SAndrew.Bardsley@arm.com * Sets a miscellaneous register, handling any architectural 41610259SAndrew.Bardsley@arm.com * side effects due to writing that register. 41710259SAndrew.Bardsley@arm.com */ 41810259SAndrew.Bardsley@arm.com void 41910259SAndrew.Bardsley@arm.com setMiscReg(int misc_reg, RegVal val) override 42010259SAndrew.Bardsley@arm.com { 42110259SAndrew.Bardsley@arm.com numIntRegWrites++; 42210259SAndrew.Bardsley@arm.com thread->setMiscReg(misc_reg, val); 42310259SAndrew.Bardsley@arm.com } 42410259SAndrew.Bardsley@arm.com 42510259SAndrew.Bardsley@arm.com PCState 42610259SAndrew.Bardsley@arm.com pcState() const override 42710259SAndrew.Bardsley@arm.com { 42810259SAndrew.Bardsley@arm.com return thread->pcState(); 42910259SAndrew.Bardsley@arm.com } 43010259SAndrew.Bardsley@arm.com 43110259SAndrew.Bardsley@arm.com void 43210259SAndrew.Bardsley@arm.com pcState(const PCState &val) override 43310259SAndrew.Bardsley@arm.com { 43410259SAndrew.Bardsley@arm.com thread->pcState(val); 43510259SAndrew.Bardsley@arm.com } 43610259SAndrew.Bardsley@arm.com 43710259SAndrew.Bardsley@arm.com 43810259SAndrew.Bardsley@arm.com Fault 43910259SAndrew.Bardsley@arm.com readMem(Addr addr, uint8_t *data, unsigned int size, 44010259SAndrew.Bardsley@arm.com Request::Flags flags) override 44110259SAndrew.Bardsley@arm.com { 44210259SAndrew.Bardsley@arm.com return cpu->readMem(addr, data, size, flags); 44310259SAndrew.Bardsley@arm.com } 44410259SAndrew.Bardsley@arm.com 44510259SAndrew.Bardsley@arm.com Fault 44610259SAndrew.Bardsley@arm.com initiateMemRead(Addr addr, unsigned int size, 44710259SAndrew.Bardsley@arm.com Request::Flags flags) override 44810259SAndrew.Bardsley@arm.com { 44910259SAndrew.Bardsley@arm.com return cpu->initiateMemRead(addr, size, flags); 45010259SAndrew.Bardsley@arm.com } 45110259SAndrew.Bardsley@arm.com 45210259SAndrew.Bardsley@arm.com Fault 45310259SAndrew.Bardsley@arm.com writeMem(uint8_t *data, unsigned int size, Addr addr, 45410259SAndrew.Bardsley@arm.com Request::Flags flags, uint64_t *res) override 45510259SAndrew.Bardsley@arm.com { 45610259SAndrew.Bardsley@arm.com return cpu->writeMem(data, size, addr, flags, res); 45710259SAndrew.Bardsley@arm.com } 45810259SAndrew.Bardsley@arm.com 45910259SAndrew.Bardsley@arm.com /** 46010259SAndrew.Bardsley@arm.com * Sets the number of consecutive store conditional failures. 46110259SAndrew.Bardsley@arm.com */ 46210259SAndrew.Bardsley@arm.com void 46310259SAndrew.Bardsley@arm.com setStCondFailures(unsigned int sc_failures) override 46410259SAndrew.Bardsley@arm.com { 46510259SAndrew.Bardsley@arm.com thread->setStCondFailures(sc_failures); 46610259SAndrew.Bardsley@arm.com } 46710259SAndrew.Bardsley@arm.com 46810259SAndrew.Bardsley@arm.com /** 46910259SAndrew.Bardsley@arm.com * Returns the number of consecutive store conditional failures. 47010259SAndrew.Bardsley@arm.com */ 47110259SAndrew.Bardsley@arm.com unsigned int 47210259SAndrew.Bardsley@arm.com readStCondFailures() const override 47310259SAndrew.Bardsley@arm.com { 47410259SAndrew.Bardsley@arm.com return thread->readStCondFailures(); 47510259SAndrew.Bardsley@arm.com } 47610259SAndrew.Bardsley@arm.com 47710259SAndrew.Bardsley@arm.com /** 47810259SAndrew.Bardsley@arm.com * Executes a syscall specified by the callnum. 47910368SAndrew.Bardsley@arm.com */ 48010368SAndrew.Bardsley@arm.com void 48110259SAndrew.Bardsley@arm.com syscall(int64_t callnum, Fault *fault) override 48210259SAndrew.Bardsley@arm.com { 48310259SAndrew.Bardsley@arm.com if (FullSystem) 48410259SAndrew.Bardsley@arm.com panic("Syscall emulation isn't available in FS mode."); 48510259SAndrew.Bardsley@arm.com 48610259SAndrew.Bardsley@arm.com thread->syscall(callnum, fault); 48710259SAndrew.Bardsley@arm.com } 48810259SAndrew.Bardsley@arm.com 48910259SAndrew.Bardsley@arm.com /** Returns a pointer to the ThreadContext. */ 49010259SAndrew.Bardsley@arm.com ThreadContext *tcBase() override { return thread->getTC(); } 49110259SAndrew.Bardsley@arm.com 49210259SAndrew.Bardsley@arm.com /** 49310259SAndrew.Bardsley@arm.com * Somewhat Alpha-specific function that handles returning from an 49410259SAndrew.Bardsley@arm.com * error or interrupt. 49510259SAndrew.Bardsley@arm.com */ 49610259SAndrew.Bardsley@arm.com Fault hwrei() override { return thread->hwrei(); } 49710259SAndrew.Bardsley@arm.com 49810259SAndrew.Bardsley@arm.com /** 49910259SAndrew.Bardsley@arm.com * Check for special simulator handling of specific PAL calls. If 50010259SAndrew.Bardsley@arm.com * return value is false, actual PAL call will be suppressed. 50110259SAndrew.Bardsley@arm.com */ 50210259SAndrew.Bardsley@arm.com bool 50310259SAndrew.Bardsley@arm.com simPalCheck(int palFunc) override 50410259SAndrew.Bardsley@arm.com { 50510259SAndrew.Bardsley@arm.com return thread->simPalCheck(palFunc); 50610259SAndrew.Bardsley@arm.com } 50710259SAndrew.Bardsley@arm.com 50810259SAndrew.Bardsley@arm.com bool 50910259SAndrew.Bardsley@arm.com readPredicate() const override 51010259SAndrew.Bardsley@arm.com { 51110259SAndrew.Bardsley@arm.com return thread->readPredicate(); 51210259SAndrew.Bardsley@arm.com } 51310259SAndrew.Bardsley@arm.com 51410259SAndrew.Bardsley@arm.com void 51510259SAndrew.Bardsley@arm.com setPredicate(bool val) override 51610259SAndrew.Bardsley@arm.com { 51710259SAndrew.Bardsley@arm.com thread->setPredicate(val); 51810259SAndrew.Bardsley@arm.com 51910259SAndrew.Bardsley@arm.com if (cpu->traceData) { 52010259SAndrew.Bardsley@arm.com cpu->traceData->setPredicate(val); 52110259SAndrew.Bardsley@arm.com } 52210259SAndrew.Bardsley@arm.com } 52310259SAndrew.Bardsley@arm.com 52410259SAndrew.Bardsley@arm.com /** 52510259SAndrew.Bardsley@arm.com * Invalidate a page in the DTLB <i>and</i> ITLB. 52610259SAndrew.Bardsley@arm.com */ 52710259SAndrew.Bardsley@arm.com void 52810259SAndrew.Bardsley@arm.com demapPage(Addr vaddr, uint64_t asn) override 52910259SAndrew.Bardsley@arm.com { 53010259SAndrew.Bardsley@arm.com thread->demapPage(vaddr, asn); 53110259SAndrew.Bardsley@arm.com } 53210259SAndrew.Bardsley@arm.com 53310259SAndrew.Bardsley@arm.com void 53410259SAndrew.Bardsley@arm.com armMonitor(Addr address) override 53510259SAndrew.Bardsley@arm.com { 53610259SAndrew.Bardsley@arm.com cpu->armMonitor(thread->threadId(), address); 53710259SAndrew.Bardsley@arm.com } 53810259SAndrew.Bardsley@arm.com 53910259SAndrew.Bardsley@arm.com bool 54010259SAndrew.Bardsley@arm.com mwait(PacketPtr pkt) override 54110259SAndrew.Bardsley@arm.com { 54210259SAndrew.Bardsley@arm.com return cpu->mwait(thread->threadId(), pkt); 54310259SAndrew.Bardsley@arm.com } 54410259SAndrew.Bardsley@arm.com 54510259SAndrew.Bardsley@arm.com void 54610259SAndrew.Bardsley@arm.com mwaitAtomic(ThreadContext *tc) override 54710259SAndrew.Bardsley@arm.com { 54810259SAndrew.Bardsley@arm.com cpu->mwaitAtomic(thread->threadId(), tc, thread->dtb); 54910259SAndrew.Bardsley@arm.com } 55010259SAndrew.Bardsley@arm.com 55110259SAndrew.Bardsley@arm.com AddressMonitor * 55210259SAndrew.Bardsley@arm.com getAddrMonitor() override 55310259SAndrew.Bardsley@arm.com { 55410259SAndrew.Bardsley@arm.com return cpu->getCpuAddrMonitor(thread->threadId()); 55510259SAndrew.Bardsley@arm.com } 55610259SAndrew.Bardsley@arm.com 55710259SAndrew.Bardsley@arm.com#if THE_ISA == MIPS_ISA 55810259SAndrew.Bardsley@arm.com RegVal 55910259SAndrew.Bardsley@arm.com readRegOtherThread(const RegId& reg, ThreadID tid=InvalidThreadID) 56010259SAndrew.Bardsley@arm.com override 56110259SAndrew.Bardsley@arm.com { 56210259SAndrew.Bardsley@arm.com panic("Simple CPU models do not support multithreaded " 56310259SAndrew.Bardsley@arm.com "register access."); 56410259SAndrew.Bardsley@arm.com } 56510259SAndrew.Bardsley@arm.com 56610259SAndrew.Bardsley@arm.com void 56710259SAndrew.Bardsley@arm.com setRegOtherThread(const RegId& reg, RegVal val, 56810259SAndrew.Bardsley@arm.com ThreadID tid=InvalidThreadID) override 56910259SAndrew.Bardsley@arm.com { 57010259SAndrew.Bardsley@arm.com panic("Simple CPU models do not support multithreaded " 57110259SAndrew.Bardsley@arm.com "register access."); 57210259SAndrew.Bardsley@arm.com } 57310259SAndrew.Bardsley@arm.com#endif 57410259SAndrew.Bardsley@arm.com 57510259SAndrew.Bardsley@arm.com}; 57610259SAndrew.Bardsley@arm.com 57710259SAndrew.Bardsley@arm.com#endif // __CPU_EXEC_CONTEXT_HH__ 57810259SAndrew.Bardsley@arm.com