exec_context.hh revision 13611
110259SAndrew.Bardsley@arm.com/* 213954Sgiacomo.gabrielli@arm.com * Copyright (c) 2014-2017 ARM Limited 310259SAndrew.Bardsley@arm.com * All rights reserved 410259SAndrew.Bardsley@arm.com * 510259SAndrew.Bardsley@arm.com * The license below extends only to copyright in the software and shall 610259SAndrew.Bardsley@arm.com * not be construed as granting a license to any other intellectual 710259SAndrew.Bardsley@arm.com * property including but not limited to intellectual property relating 810259SAndrew.Bardsley@arm.com * to a hardware implementation of the functionality of the software 910259SAndrew.Bardsley@arm.com * licensed hereunder. You may use the software subject to the license 1010259SAndrew.Bardsley@arm.com * terms below provided that you ensure that this notice is replicated 1110259SAndrew.Bardsley@arm.com * unmodified and in its entirety in all distributions of the software, 1210259SAndrew.Bardsley@arm.com * modified or unmodified, in source code or in binary form. 1310259SAndrew.Bardsley@arm.com * 1410259SAndrew.Bardsley@arm.com * Copyright (c) 2002-2005 The Regents of The University of Michigan 1510259SAndrew.Bardsley@arm.com * All rights reserved. 1610259SAndrew.Bardsley@arm.com * 1710259SAndrew.Bardsley@arm.com * Redistribution and use in source and binary forms, with or without 1810259SAndrew.Bardsley@arm.com * modification, are permitted provided that the following conditions are 1910259SAndrew.Bardsley@arm.com * met: redistributions of source code must retain the above copyright 2010259SAndrew.Bardsley@arm.com * notice, this list of conditions and the following disclaimer; 2110259SAndrew.Bardsley@arm.com * redistributions in binary form must reproduce the above copyright 2210259SAndrew.Bardsley@arm.com * notice, this list of conditions and the following disclaimer in the 2310259SAndrew.Bardsley@arm.com * documentation and/or other materials provided with the distribution; 2410259SAndrew.Bardsley@arm.com * neither the name of the copyright holders nor the names of its 2510259SAndrew.Bardsley@arm.com * contributors may be used to endorse or promote products derived from 2610259SAndrew.Bardsley@arm.com * this software without specific prior written permission. 2710259SAndrew.Bardsley@arm.com * 2810259SAndrew.Bardsley@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2910259SAndrew.Bardsley@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 3010259SAndrew.Bardsley@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 3110259SAndrew.Bardsley@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 3210259SAndrew.Bardsley@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3310259SAndrew.Bardsley@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3410259SAndrew.Bardsley@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3510259SAndrew.Bardsley@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3610259SAndrew.Bardsley@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3710259SAndrew.Bardsley@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3810259SAndrew.Bardsley@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3910259SAndrew.Bardsley@arm.com * 4011793Sbrandon.potter@amd.com * Authors: Kevin Lim 4111793Sbrandon.potter@amd.com * Andreas Sandberg 4210259SAndrew.Bardsley@arm.com * Mitch Hayenga 4310259SAndrew.Bardsley@arm.com */ 4410259SAndrew.Bardsley@arm.com 4510259SAndrew.Bardsley@arm.com#ifndef __CPU_SIMPLE_EXEC_CONTEXT_HH__ 4610259SAndrew.Bardsley@arm.com#define __CPU_SIMPLE_EXEC_CONTEXT_HH__ 4713449Sgabeblack@google.com 4810259SAndrew.Bardsley@arm.com#include "arch/registers.hh" 4910259SAndrew.Bardsley@arm.com#include "base/types.hh" 5010259SAndrew.Bardsley@arm.com#include "config/the_isa.hh" 5110259SAndrew.Bardsley@arm.com#include "cpu/base.hh" 5213954Sgiacomo.gabrielli@arm.com#include "cpu/exec_context.hh" 5310259SAndrew.Bardsley@arm.com#include "cpu/reg_class.hh" 5410259SAndrew.Bardsley@arm.com#include "cpu/simple/base.hh" 5510259SAndrew.Bardsley@arm.com#include "cpu/static_inst_fwd.hh" 5610259SAndrew.Bardsley@arm.com#include "cpu/translation.hh" 5710259SAndrew.Bardsley@arm.com#include "mem/request.hh" 5810259SAndrew.Bardsley@arm.com 5910259SAndrew.Bardsley@arm.comclass BaseSimpleCPU; 6010259SAndrew.Bardsley@arm.com 6110259SAndrew.Bardsley@arm.comclass SimpleExecContext : public ExecContext { 6210259SAndrew.Bardsley@arm.com protected: 6310259SAndrew.Bardsley@arm.com typedef TheISA::CCReg CCReg; 6410259SAndrew.Bardsley@arm.com using VecRegContainer = TheISA::VecRegContainer; 6510259SAndrew.Bardsley@arm.com using VecElem = TheISA::VecElem; 6610259SAndrew.Bardsley@arm.com 6710259SAndrew.Bardsley@arm.com public: 6810259SAndrew.Bardsley@arm.com BaseSimpleCPU *cpu; 6910259SAndrew.Bardsley@arm.com SimpleThread* thread; 7010259SAndrew.Bardsley@arm.com 7114105Sgabor.dozsa@arm.com // This is the offset from the current pc that fetch should be performed 7210259SAndrew.Bardsley@arm.com Addr fetchOffset; 7312749Sgiacomo.travaglini@arm.com // This flag says to stay at the current pc. This is useful for 7412749Sgiacomo.travaglini@arm.com // instructions which go beyond MachInst boundaries. 7512749Sgiacomo.travaglini@arm.com bool stayAtPC; 7610259SAndrew.Bardsley@arm.com 7713954Sgiacomo.gabrielli@arm.com // Branch prediction 7814105Sgabor.dozsa@arm.com TheISA::PCState predPC; 7914105Sgabor.dozsa@arm.com 8014105Sgabor.dozsa@arm.com /** PER-THREAD STATS */ 8114105Sgabor.dozsa@arm.com 8214105Sgabor.dozsa@arm.com // Number of simulated instructions 8314105Sgabor.dozsa@arm.com Counter numInst; 8414105Sgabor.dozsa@arm.com Stats::Scalar numInsts; 8514105Sgabor.dozsa@arm.com Counter numOp; 8614105Sgabor.dozsa@arm.com Stats::Scalar numOps; 8714105Sgabor.dozsa@arm.com 8814105Sgabor.dozsa@arm.com // Number of integer alu accesses 8914105Sgabor.dozsa@arm.com Stats::Scalar numIntAluAccesses; 9014105Sgabor.dozsa@arm.com 9114105Sgabor.dozsa@arm.com // Number of float alu accesses 9214105Sgabor.dozsa@arm.com Stats::Scalar numFpAluAccesses; 9314105Sgabor.dozsa@arm.com 9414105Sgabor.dozsa@arm.com // Number of vector alu accesses 9514105Sgabor.dozsa@arm.com Stats::Scalar numVecAluAccesses; 9614105Sgabor.dozsa@arm.com 9714105Sgabor.dozsa@arm.com // Number of function calls/returns 9814105Sgabor.dozsa@arm.com Stats::Scalar numCallsReturns; 9914105Sgabor.dozsa@arm.com 10014105Sgabor.dozsa@arm.com // Conditional control instructions; 10114105Sgabor.dozsa@arm.com Stats::Scalar numCondCtrlInsts; 10214105Sgabor.dozsa@arm.com 10314105Sgabor.dozsa@arm.com // Number of int instructions 10414105Sgabor.dozsa@arm.com Stats::Scalar numIntInsts; 10514105Sgabor.dozsa@arm.com 10614105Sgabor.dozsa@arm.com // Number of float instructions 10714105Sgabor.dozsa@arm.com Stats::Scalar numFpInsts; 10814105Sgabor.dozsa@arm.com 10914105Sgabor.dozsa@arm.com // Number of vector instructions 11014105Sgabor.dozsa@arm.com Stats::Scalar numVecInsts; 11114105Sgabor.dozsa@arm.com 11214105Sgabor.dozsa@arm.com // Number of integer register file accesses 11314105Sgabor.dozsa@arm.com Stats::Scalar numIntRegReads; 11413954Sgiacomo.gabrielli@arm.com Stats::Scalar numIntRegWrites; 11513954Sgiacomo.gabrielli@arm.com 11613954Sgiacomo.gabrielli@arm.com // Number of float register file accesses 11713954Sgiacomo.gabrielli@arm.com Stats::Scalar numFpRegReads; 11813954Sgiacomo.gabrielli@arm.com Stats::Scalar numFpRegWrites; 11913954Sgiacomo.gabrielli@arm.com 12010259SAndrew.Bardsley@arm.com // Number of vector register file accesses 12110259SAndrew.Bardsley@arm.com mutable Stats::Scalar numVecRegReads; 12210259SAndrew.Bardsley@arm.com Stats::Scalar numVecRegWrites; 12310259SAndrew.Bardsley@arm.com 12410259SAndrew.Bardsley@arm.com // Number of predicate register file accesses 12510259SAndrew.Bardsley@arm.com mutable Stats::Scalar numVecPredRegReads; 12610259SAndrew.Bardsley@arm.com Stats::Scalar numVecPredRegWrites; 12710259SAndrew.Bardsley@arm.com 12810259SAndrew.Bardsley@arm.com // Number of condition code register file accesses 12910259SAndrew.Bardsley@arm.com Stats::Scalar numCCRegReads; 13010259SAndrew.Bardsley@arm.com Stats::Scalar numCCRegWrites; 13110259SAndrew.Bardsley@arm.com 13212179Spau.cabre@metempsy.com // Number of simulated memory references 13310259SAndrew.Bardsley@arm.com Stats::Scalar numMemRefs; 13410259SAndrew.Bardsley@arm.com Stats::Scalar numLoadInsts; 13510259SAndrew.Bardsley@arm.com Stats::Scalar numStoreInsts; 13610259SAndrew.Bardsley@arm.com 13710259SAndrew.Bardsley@arm.com // Number of idle cycles 13810259SAndrew.Bardsley@arm.com Stats::Formula numIdleCycles; 13910259SAndrew.Bardsley@arm.com 14010259SAndrew.Bardsley@arm.com // Number of busy cycles 14110259SAndrew.Bardsley@arm.com Stats::Formula numBusyCycles; 14210259SAndrew.Bardsley@arm.com 14310259SAndrew.Bardsley@arm.com // Number of simulated loads 14410259SAndrew.Bardsley@arm.com Counter numLoad; 14512749Sgiacomo.travaglini@arm.com 14612749Sgiacomo.travaglini@arm.com // Number of idle cycles 14710259SAndrew.Bardsley@arm.com Stats::Average notIdleFraction; 14810259SAndrew.Bardsley@arm.com Stats::Formula idleFraction; 14910259SAndrew.Bardsley@arm.com 15010259SAndrew.Bardsley@arm.com // Number of cycles stalled for I-cache responses 15110259SAndrew.Bardsley@arm.com Stats::Scalar icacheStallCycles; 15210259SAndrew.Bardsley@arm.com Counter lastIcacheStall; 15310259SAndrew.Bardsley@arm.com 15410259SAndrew.Bardsley@arm.com // Number of cycles stalled for D-cache responses 15510259SAndrew.Bardsley@arm.com Stats::Scalar dcacheStallCycles; 15610259SAndrew.Bardsley@arm.com Counter lastDcacheStall; 15710259SAndrew.Bardsley@arm.com 15810259SAndrew.Bardsley@arm.com /// @{ 15910259SAndrew.Bardsley@arm.com /// Total number of branches fetched 16010259SAndrew.Bardsley@arm.com Stats::Scalar numBranches; 16110259SAndrew.Bardsley@arm.com /// Number of branches predicted as taken 16210259SAndrew.Bardsley@arm.com Stats::Scalar numPredictedBranches; 16310259SAndrew.Bardsley@arm.com /// Number of misprediced branches 16410259SAndrew.Bardsley@arm.com Stats::Scalar numBranchMispred; 16510259SAndrew.Bardsley@arm.com /// @} 16610259SAndrew.Bardsley@arm.com 16710259SAndrew.Bardsley@arm.com // Instruction mix histogram by OpClass 16810259SAndrew.Bardsley@arm.com Stats::Vector statExecutedInstType; 16910259SAndrew.Bardsley@arm.com 17010259SAndrew.Bardsley@arm.com public: 17110259SAndrew.Bardsley@arm.com /** Constructor */ 17210259SAndrew.Bardsley@arm.com SimpleExecContext(BaseSimpleCPU* _cpu, SimpleThread* _thread) 17310259SAndrew.Bardsley@arm.com : cpu(_cpu), thread(_thread), fetchOffset(0), stayAtPC(false), 17410259SAndrew.Bardsley@arm.com numInst(0), numOp(0), numLoad(0), lastIcacheStall(0), lastDcacheStall(0) 17510259SAndrew.Bardsley@arm.com { } 17610259SAndrew.Bardsley@arm.com 17710259SAndrew.Bardsley@arm.com /** Reads an integer register. */ 17810259SAndrew.Bardsley@arm.com RegVal 17910259SAndrew.Bardsley@arm.com readIntRegOperand(const StaticInst *si, int idx) override 18010259SAndrew.Bardsley@arm.com { 18110259SAndrew.Bardsley@arm.com numIntRegReads++; 18210259SAndrew.Bardsley@arm.com const RegId& reg = si->srcRegIdx(idx); 18310259SAndrew.Bardsley@arm.com assert(reg.isIntReg()); 18410259SAndrew.Bardsley@arm.com return thread->readIntReg(reg.index()); 18510259SAndrew.Bardsley@arm.com } 18610259SAndrew.Bardsley@arm.com 18710259SAndrew.Bardsley@arm.com /** Sets an integer register to a value. */ 18810259SAndrew.Bardsley@arm.com void 18910259SAndrew.Bardsley@arm.com setIntRegOperand(const StaticInst *si, int idx, RegVal val) override 19010259SAndrew.Bardsley@arm.com { 19110259SAndrew.Bardsley@arm.com numIntRegWrites++; 19210259SAndrew.Bardsley@arm.com const RegId& reg = si->destRegIdx(idx); 19310259SAndrew.Bardsley@arm.com assert(reg.isIntReg()); 19410259SAndrew.Bardsley@arm.com thread->setIntReg(reg.index(), val); 19510259SAndrew.Bardsley@arm.com } 19610259SAndrew.Bardsley@arm.com 19710259SAndrew.Bardsley@arm.com /** Reads a floating point register in its binary format, instead 19810259SAndrew.Bardsley@arm.com * of by value. */ 19910259SAndrew.Bardsley@arm.com RegVal 20010259SAndrew.Bardsley@arm.com readFloatRegOperandBits(const StaticInst *si, int idx) override 20110259SAndrew.Bardsley@arm.com { 20210259SAndrew.Bardsley@arm.com numFpRegReads++; 20310259SAndrew.Bardsley@arm.com const RegId& reg = si->srcRegIdx(idx); 20410259SAndrew.Bardsley@arm.com assert(reg.isFloatReg()); 20510259SAndrew.Bardsley@arm.com return thread->readFloatReg(reg.index()); 20610259SAndrew.Bardsley@arm.com } 20710259SAndrew.Bardsley@arm.com 20810259SAndrew.Bardsley@arm.com /** Sets the bits of a floating point register of single width 20910259SAndrew.Bardsley@arm.com * to a binary value. */ 21010259SAndrew.Bardsley@arm.com void 21110259SAndrew.Bardsley@arm.com setFloatRegOperandBits(const StaticInst *si, int idx, RegVal val) override 21210259SAndrew.Bardsley@arm.com { 21310259SAndrew.Bardsley@arm.com numFpRegWrites++; 21410259SAndrew.Bardsley@arm.com const RegId& reg = si->destRegIdx(idx); 21510259SAndrew.Bardsley@arm.com assert(reg.isFloatReg()); 21610259SAndrew.Bardsley@arm.com thread->setFloatReg(reg.index(), val); 21710259SAndrew.Bardsley@arm.com } 21810259SAndrew.Bardsley@arm.com 21910259SAndrew.Bardsley@arm.com /** Reads a vector register. */ 22010259SAndrew.Bardsley@arm.com const VecRegContainer & 22110259SAndrew.Bardsley@arm.com readVecRegOperand(const StaticInst *si, int idx) const override 22210259SAndrew.Bardsley@arm.com { 22310259SAndrew.Bardsley@arm.com numVecRegReads++; 22410259SAndrew.Bardsley@arm.com const RegId& reg = si->srcRegIdx(idx); 22510259SAndrew.Bardsley@arm.com assert(reg.isVecReg()); 22610259SAndrew.Bardsley@arm.com return thread->readVecReg(reg); 22710259SAndrew.Bardsley@arm.com } 22810259SAndrew.Bardsley@arm.com 22910259SAndrew.Bardsley@arm.com /** Reads a vector register for modification. */ 23010259SAndrew.Bardsley@arm.com VecRegContainer & 23110259SAndrew.Bardsley@arm.com getWritableVecRegOperand(const StaticInst *si, int idx) override 23210259SAndrew.Bardsley@arm.com { 23310259SAndrew.Bardsley@arm.com numVecRegWrites++; 23410259SAndrew.Bardsley@arm.com const RegId& reg = si->destRegIdx(idx); 23510259SAndrew.Bardsley@arm.com assert(reg.isVecReg()); 23610259SAndrew.Bardsley@arm.com return thread->getWritableVecReg(reg); 23710259SAndrew.Bardsley@arm.com } 23810259SAndrew.Bardsley@arm.com 23910259SAndrew.Bardsley@arm.com /** Sets a vector register to a value. */ 24010259SAndrew.Bardsley@arm.com void 24110259SAndrew.Bardsley@arm.com setVecRegOperand(const StaticInst *si, int idx, 24210259SAndrew.Bardsley@arm.com const VecRegContainer& val) override 24310259SAndrew.Bardsley@arm.com { 24410259SAndrew.Bardsley@arm.com numVecRegWrites++; 24510259SAndrew.Bardsley@arm.com const RegId& reg = si->destRegIdx(idx); 24610259SAndrew.Bardsley@arm.com assert(reg.isVecReg()); 24710259SAndrew.Bardsley@arm.com thread->setVecReg(reg, val); 24810259SAndrew.Bardsley@arm.com } 24910259SAndrew.Bardsley@arm.com 25010259SAndrew.Bardsley@arm.com /** Vector Register Lane Interfaces. */ 25110259SAndrew.Bardsley@arm.com /** @{ */ 25211567Smitch.hayenga@arm.com /** Reads source vector lane. */ 25311567Smitch.hayenga@arm.com template <typename VecElem> 25410259SAndrew.Bardsley@arm.com VecLaneT<VecElem, true> 25510259SAndrew.Bardsley@arm.com readVecLaneOperand(const StaticInst *si, int idx) const 25610259SAndrew.Bardsley@arm.com { 25710259SAndrew.Bardsley@arm.com numVecRegReads++; 25810259SAndrew.Bardsley@arm.com const RegId& reg = si->srcRegIdx(idx); 25911567Smitch.hayenga@arm.com assert(reg.isVecReg()); 26010259SAndrew.Bardsley@arm.com return thread->readVecLane<VecElem>(reg); 26110259SAndrew.Bardsley@arm.com } 26210259SAndrew.Bardsley@arm.com /** Reads source vector 8bit operand. */ 26312749Sgiacomo.travaglini@arm.com virtual ConstVecLane8 26410379Sandreas.hansson@arm.com readVec8BitLaneOperand(const StaticInst *si, int idx) const 26510259SAndrew.Bardsley@arm.com override 26610259SAndrew.Bardsley@arm.com { return readVecLaneOperand<uint8_t>(si, idx); } 26710259SAndrew.Bardsley@arm.com 26810259SAndrew.Bardsley@arm.com /** Reads source vector 16bit operand. */ 26914105Sgabor.dozsa@arm.com virtual ConstVecLane16 27014105Sgabor.dozsa@arm.com readVec16BitLaneOperand(const StaticInst *si, int idx) const 27110259SAndrew.Bardsley@arm.com override 27214105Sgabor.dozsa@arm.com { return readVecLaneOperand<uint16_t>(si, idx); } 27314105Sgabor.dozsa@arm.com 27414105Sgabor.dozsa@arm.com /** Reads source vector 32bit operand. */ 27514105Sgabor.dozsa@arm.com virtual ConstVecLane32 27614105Sgabor.dozsa@arm.com readVec32BitLaneOperand(const StaticInst *si, int idx) const 27714105Sgabor.dozsa@arm.com override 27814105Sgabor.dozsa@arm.com { return readVecLaneOperand<uint32_t>(si, idx); } 27914105Sgabor.dozsa@arm.com 28014105Sgabor.dozsa@arm.com /** Reads source vector 64bit operand. */ 28114105Sgabor.dozsa@arm.com virtual ConstVecLane64 28214105Sgabor.dozsa@arm.com readVec64BitLaneOperand(const StaticInst *si, int idx) const 28314105Sgabor.dozsa@arm.com override 28414105Sgabor.dozsa@arm.com { return readVecLaneOperand<uint64_t>(si, idx); } 28514105Sgabor.dozsa@arm.com 28610259SAndrew.Bardsley@arm.com /** Write a lane of the destination vector operand. */ 28710259SAndrew.Bardsley@arm.com template <typename LD> 28810259SAndrew.Bardsley@arm.com void 28910259SAndrew.Bardsley@arm.com setVecLaneOperandT(const StaticInst *si, int idx, 29010259SAndrew.Bardsley@arm.com const LD& val) 29110259SAndrew.Bardsley@arm.com { 29210259SAndrew.Bardsley@arm.com numVecRegWrites++; 29310259SAndrew.Bardsley@arm.com const RegId& reg = si->destRegIdx(idx); 29410259SAndrew.Bardsley@arm.com assert(reg.isVecReg()); 29510259SAndrew.Bardsley@arm.com return thread->setVecLane(reg, val); 29610259SAndrew.Bardsley@arm.com } 29710259SAndrew.Bardsley@arm.com /** Write a lane of the destination vector operand. */ 29813954Sgiacomo.gabrielli@arm.com virtual void 29913954Sgiacomo.gabrielli@arm.com setVecLaneOperand(const StaticInst *si, int idx, 30013954Sgiacomo.gabrielli@arm.com const LaneData<LaneSize::Byte>& val) override 30113954Sgiacomo.gabrielli@arm.com { return setVecLaneOperandT(si, idx, val); } 30210259SAndrew.Bardsley@arm.com /** Write a lane of the destination vector operand. */ 30313954Sgiacomo.gabrielli@arm.com virtual void 30410259SAndrew.Bardsley@arm.com setVecLaneOperand(const StaticInst *si, int idx, 30513954Sgiacomo.gabrielli@arm.com const LaneData<LaneSize::TwoByte>& val) override 30613954Sgiacomo.gabrielli@arm.com { return setVecLaneOperandT(si, idx, val); } 30713954Sgiacomo.gabrielli@arm.com /** Write a lane of the destination vector operand. */ 30813954Sgiacomo.gabrielli@arm.com virtual void 30913954Sgiacomo.gabrielli@arm.com setVecLaneOperand(const StaticInst *si, int idx, 31013954Sgiacomo.gabrielli@arm.com const LaneData<LaneSize::FourByte>& val) override 31113954Sgiacomo.gabrielli@arm.com { return setVecLaneOperandT(si, idx, val); } 31213954Sgiacomo.gabrielli@arm.com /** Write a lane of the destination vector operand. */ 31313954Sgiacomo.gabrielli@arm.com virtual void 31413954Sgiacomo.gabrielli@arm.com setVecLaneOperand(const StaticInst *si, int idx, 31510259SAndrew.Bardsley@arm.com const LaneData<LaneSize::EightByte>& val) override 31610259SAndrew.Bardsley@arm.com { return setVecLaneOperandT(si, idx, val); } 31710259SAndrew.Bardsley@arm.com /** @} */ 31810259SAndrew.Bardsley@arm.com 31910259SAndrew.Bardsley@arm.com /** Reads an element of a vector register. */ 32010259SAndrew.Bardsley@arm.com VecElem 32110259SAndrew.Bardsley@arm.com readVecElemOperand(const StaticInst *si, int idx) const override 32210259SAndrew.Bardsley@arm.com { 32310259SAndrew.Bardsley@arm.com numVecRegReads++; 32410259SAndrew.Bardsley@arm.com const RegId& reg = si->srcRegIdx(idx); 32510259SAndrew.Bardsley@arm.com assert(reg.isVecElem()); 32610259SAndrew.Bardsley@arm.com return thread->readVecElem(reg); 32712749Sgiacomo.travaglini@arm.com } 32810379Sandreas.hansson@arm.com 32910259SAndrew.Bardsley@arm.com /** Sets an element of a vector register to a value. */ 33010259SAndrew.Bardsley@arm.com void 33110259SAndrew.Bardsley@arm.com setVecElemOperand(const StaticInst *si, int idx, 33210259SAndrew.Bardsley@arm.com const VecElem val) override 33310259SAndrew.Bardsley@arm.com { 33410259SAndrew.Bardsley@arm.com numVecRegWrites++; 33510259SAndrew.Bardsley@arm.com const RegId& reg = si->destRegIdx(idx); 33610259SAndrew.Bardsley@arm.com assert(reg.isVecElem()); 33710259SAndrew.Bardsley@arm.com thread->setVecElem(reg, val); 33810259SAndrew.Bardsley@arm.com } 33914105Sgabor.dozsa@arm.com 34014105Sgabor.dozsa@arm.com const VecPredRegContainer& 34114105Sgabor.dozsa@arm.com readVecPredRegOperand(const StaticInst *si, int idx) const override 34210259SAndrew.Bardsley@arm.com { 34310259SAndrew.Bardsley@arm.com numVecPredRegReads++; 34410259SAndrew.Bardsley@arm.com const RegId& reg = si->srcRegIdx(idx); 34510259SAndrew.Bardsley@arm.com assert(reg.isVecPredReg()); 34610259SAndrew.Bardsley@arm.com return thread->readVecPredReg(reg); 34710259SAndrew.Bardsley@arm.com } 34810259SAndrew.Bardsley@arm.com 34914105Sgabor.dozsa@arm.com VecPredRegContainer& 35010259SAndrew.Bardsley@arm.com getWritableVecPredRegOperand(const StaticInst *si, int idx) override 35114105Sgabor.dozsa@arm.com { 35210259SAndrew.Bardsley@arm.com numVecPredRegWrites++; 35310259SAndrew.Bardsley@arm.com const RegId& reg = si->destRegIdx(idx); 35410259SAndrew.Bardsley@arm.com assert(reg.isVecPredReg()); 35510259SAndrew.Bardsley@arm.com return thread->getWritableVecPredReg(reg); 35610259SAndrew.Bardsley@arm.com } 35714105Sgabor.dozsa@arm.com 35814105Sgabor.dozsa@arm.com void 35914105Sgabor.dozsa@arm.com setVecPredRegOperand(const StaticInst *si, int idx, 36014105Sgabor.dozsa@arm.com const VecPredRegContainer& val) override 36114105Sgabor.dozsa@arm.com { 36214105Sgabor.dozsa@arm.com numVecPredRegWrites++; 36314105Sgabor.dozsa@arm.com const RegId& reg = si->destRegIdx(idx); 36414105Sgabor.dozsa@arm.com assert(reg.isVecPredReg()); 36514105Sgabor.dozsa@arm.com thread->setVecPredReg(reg, val); 36614105Sgabor.dozsa@arm.com } 36714105Sgabor.dozsa@arm.com 36814105Sgabor.dozsa@arm.com CCReg 36914105Sgabor.dozsa@arm.com readCCRegOperand(const StaticInst *si, int idx) override 37014105Sgabor.dozsa@arm.com { 37114105Sgabor.dozsa@arm.com numCCRegReads++; 37214105Sgabor.dozsa@arm.com const RegId& reg = si->srcRegIdx(idx); 37310259SAndrew.Bardsley@arm.com assert(reg.isCCReg()); 37410259SAndrew.Bardsley@arm.com return thread->readCCReg(reg.index()); 37510259SAndrew.Bardsley@arm.com } 37610259SAndrew.Bardsley@arm.com 37710259SAndrew.Bardsley@arm.com void 37810259SAndrew.Bardsley@arm.com setCCRegOperand(const StaticInst *si, int idx, CCReg val) override 37910259SAndrew.Bardsley@arm.com { 38010259SAndrew.Bardsley@arm.com numCCRegWrites++; 38110259SAndrew.Bardsley@arm.com const RegId& reg = si->destRegIdx(idx); 38210259SAndrew.Bardsley@arm.com assert(reg.isCCReg()); 38310259SAndrew.Bardsley@arm.com thread->setCCReg(reg.index(), val); 38410259SAndrew.Bardsley@arm.com } 38510259SAndrew.Bardsley@arm.com 38610259SAndrew.Bardsley@arm.com RegVal 38710259SAndrew.Bardsley@arm.com readMiscRegOperand(const StaticInst *si, int idx) override 38812127Sspwilson2@wisc.edu { 38912127Sspwilson2@wisc.edu numIntRegReads++; 39010259SAndrew.Bardsley@arm.com const RegId& reg = si->srcRegIdx(idx); 39110259SAndrew.Bardsley@arm.com assert(reg.isMiscReg()); 39210259SAndrew.Bardsley@arm.com return thread->readMiscReg(reg.index()); 39310259SAndrew.Bardsley@arm.com } 39410259SAndrew.Bardsley@arm.com 39510259SAndrew.Bardsley@arm.com void 39610259SAndrew.Bardsley@arm.com setMiscRegOperand(const StaticInst *si, int idx, RegVal val) override 39710259SAndrew.Bardsley@arm.com { 39810259SAndrew.Bardsley@arm.com numIntRegWrites++; 39910259SAndrew.Bardsley@arm.com const RegId& reg = si->destRegIdx(idx); 40010259SAndrew.Bardsley@arm.com assert(reg.isMiscReg()); 40110259SAndrew.Bardsley@arm.com thread->setMiscReg(reg.index(), val); 40210259SAndrew.Bardsley@arm.com } 40310259SAndrew.Bardsley@arm.com 40410259SAndrew.Bardsley@arm.com /** 40510259SAndrew.Bardsley@arm.com * Reads a miscellaneous register, handling any architectural 40610259SAndrew.Bardsley@arm.com * side effects due to reading that register. 40710259SAndrew.Bardsley@arm.com */ 40810259SAndrew.Bardsley@arm.com RegVal 40910259SAndrew.Bardsley@arm.com readMiscReg(int misc_reg) override 41010259SAndrew.Bardsley@arm.com { 41110259SAndrew.Bardsley@arm.com numIntRegReads++; 41210259SAndrew.Bardsley@arm.com return thread->readMiscReg(misc_reg); 41310259SAndrew.Bardsley@arm.com } 41412749Sgiacomo.travaglini@arm.com 41512749Sgiacomo.travaglini@arm.com /** 41610259SAndrew.Bardsley@arm.com * Sets a miscellaneous register, handling any architectural 41710259SAndrew.Bardsley@arm.com * side effects due to writing that register. 41810259SAndrew.Bardsley@arm.com */ 41910259SAndrew.Bardsley@arm.com void 42010259SAndrew.Bardsley@arm.com setMiscReg(int misc_reg, RegVal val) override 42113954Sgiacomo.gabrielli@arm.com { 42213954Sgiacomo.gabrielli@arm.com numIntRegWrites++; 42310259SAndrew.Bardsley@arm.com thread->setMiscReg(misc_reg, val); 42410259SAndrew.Bardsley@arm.com } 42510259SAndrew.Bardsley@arm.com 42610259SAndrew.Bardsley@arm.com PCState 42710259SAndrew.Bardsley@arm.com pcState() const override 42810259SAndrew.Bardsley@arm.com { 42910259SAndrew.Bardsley@arm.com return thread->pcState(); 43010259SAndrew.Bardsley@arm.com } 43110259SAndrew.Bardsley@arm.com 43210259SAndrew.Bardsley@arm.com void 43310259SAndrew.Bardsley@arm.com pcState(const PCState &val) override 43410259SAndrew.Bardsley@arm.com { 43510259SAndrew.Bardsley@arm.com thread->pcState(val); 43610259SAndrew.Bardsley@arm.com } 43710259SAndrew.Bardsley@arm.com 43810259SAndrew.Bardsley@arm.com 43910259SAndrew.Bardsley@arm.com Fault 44010259SAndrew.Bardsley@arm.com readMem(Addr addr, uint8_t *data, unsigned int size, 44110259SAndrew.Bardsley@arm.com Request::Flags flags) override 44210259SAndrew.Bardsley@arm.com { 44310259SAndrew.Bardsley@arm.com return cpu->readMem(addr, data, size, flags); 44410259SAndrew.Bardsley@arm.com } 44510259SAndrew.Bardsley@arm.com 44610259SAndrew.Bardsley@arm.com Fault 44710259SAndrew.Bardsley@arm.com initiateMemRead(Addr addr, unsigned int size, 44810259SAndrew.Bardsley@arm.com Request::Flags flags) override 44910259SAndrew.Bardsley@arm.com { 45010259SAndrew.Bardsley@arm.com return cpu->initiateMemRead(addr, size, flags); 45110259SAndrew.Bardsley@arm.com } 45210259SAndrew.Bardsley@arm.com 45310259SAndrew.Bardsley@arm.com Fault 45410259SAndrew.Bardsley@arm.com writeMem(uint8_t *data, unsigned int size, Addr addr, 45510259SAndrew.Bardsley@arm.com Request::Flags flags, uint64_t *res) override 45610259SAndrew.Bardsley@arm.com { 45710259SAndrew.Bardsley@arm.com return cpu->writeMem(data, size, addr, flags, res); 45810259SAndrew.Bardsley@arm.com } 45910259SAndrew.Bardsley@arm.com 46010259SAndrew.Bardsley@arm.com /** 46110259SAndrew.Bardsley@arm.com * Sets the number of consecutive store conditional failures. 46210259SAndrew.Bardsley@arm.com */ 46310259SAndrew.Bardsley@arm.com void 46410259SAndrew.Bardsley@arm.com setStCondFailures(unsigned int sc_failures) override 46510259SAndrew.Bardsley@arm.com { 46610259SAndrew.Bardsley@arm.com thread->setStCondFailures(sc_failures); 46713954Sgiacomo.gabrielli@arm.com } 46813954Sgiacomo.gabrielli@arm.com 46913954Sgiacomo.gabrielli@arm.com /** 47010259SAndrew.Bardsley@arm.com * Returns the number of consecutive store conditional failures. 47110259SAndrew.Bardsley@arm.com */ 47210259SAndrew.Bardsley@arm.com unsigned int 47310259SAndrew.Bardsley@arm.com readStCondFailures() const override 47410259SAndrew.Bardsley@arm.com { 47510259SAndrew.Bardsley@arm.com return thread->readStCondFailures(); 47610259SAndrew.Bardsley@arm.com } 47710259SAndrew.Bardsley@arm.com 47810259SAndrew.Bardsley@arm.com /** 47910259SAndrew.Bardsley@arm.com * Executes a syscall specified by the callnum. 48010259SAndrew.Bardsley@arm.com */ 48110259SAndrew.Bardsley@arm.com void 48210259SAndrew.Bardsley@arm.com syscall(int64_t callnum, Fault *fault) override 48310259SAndrew.Bardsley@arm.com { 48410259SAndrew.Bardsley@arm.com if (FullSystem) 48510259SAndrew.Bardsley@arm.com panic("Syscall emulation isn't available in FS mode."); 48610259SAndrew.Bardsley@arm.com 48710259SAndrew.Bardsley@arm.com thread->syscall(callnum, fault); 48810259SAndrew.Bardsley@arm.com } 48912749Sgiacomo.travaglini@arm.com 49013954Sgiacomo.gabrielli@arm.com /** Returns a pointer to the ThreadContext. */ 49110259SAndrew.Bardsley@arm.com ThreadContext *tcBase() override { return thread->getTC(); } 49212749Sgiacomo.travaglini@arm.com 49313954Sgiacomo.gabrielli@arm.com /** 49413954Sgiacomo.gabrielli@arm.com * Somewhat Alpha-specific function that handles returning from an 49513954Sgiacomo.gabrielli@arm.com * error or interrupt. 49613954Sgiacomo.gabrielli@arm.com */ 49713954Sgiacomo.gabrielli@arm.com Fault hwrei() override { return thread->hwrei(); } 49813954Sgiacomo.gabrielli@arm.com 49913954Sgiacomo.gabrielli@arm.com /** 50013954Sgiacomo.gabrielli@arm.com * Check for special simulator handling of specific PAL calls. If 50113954Sgiacomo.gabrielli@arm.com * return value is false, actual PAL call will be suppressed. 50213954Sgiacomo.gabrielli@arm.com */ 50313954Sgiacomo.gabrielli@arm.com bool 50413954Sgiacomo.gabrielli@arm.com simPalCheck(int palFunc) override 50513954Sgiacomo.gabrielli@arm.com { 50613954Sgiacomo.gabrielli@arm.com return thread->simPalCheck(palFunc); 50713954Sgiacomo.gabrielli@arm.com } 50813954Sgiacomo.gabrielli@arm.com 50913954Sgiacomo.gabrielli@arm.com bool 51013954Sgiacomo.gabrielli@arm.com readPredicate() const override 51113954Sgiacomo.gabrielli@arm.com { 51213954Sgiacomo.gabrielli@arm.com return thread->readPredicate(); 51313954Sgiacomo.gabrielli@arm.com } 51410259SAndrew.Bardsley@arm.com 51513954Sgiacomo.gabrielli@arm.com void 51613954Sgiacomo.gabrielli@arm.com setPredicate(bool val) override 51713954Sgiacomo.gabrielli@arm.com { 51813954Sgiacomo.gabrielli@arm.com thread->setPredicate(val); 51913954Sgiacomo.gabrielli@arm.com 52013954Sgiacomo.gabrielli@arm.com if (cpu->traceData) { 52113954Sgiacomo.gabrielli@arm.com cpu->traceData->setPredicate(val); 52213954Sgiacomo.gabrielli@arm.com } 52313954Sgiacomo.gabrielli@arm.com } 52413954Sgiacomo.gabrielli@arm.com 52510259SAndrew.Bardsley@arm.com /** 52610259SAndrew.Bardsley@arm.com * Invalidate a page in the DTLB <i>and</i> ITLB. 52710259SAndrew.Bardsley@arm.com */ 52813954Sgiacomo.gabrielli@arm.com void 52913954Sgiacomo.gabrielli@arm.com demapPage(Addr vaddr, uint64_t asn) override 53010259SAndrew.Bardsley@arm.com { 53110259SAndrew.Bardsley@arm.com thread->demapPage(vaddr, asn); 53210259SAndrew.Bardsley@arm.com } 53310259SAndrew.Bardsley@arm.com 53410259SAndrew.Bardsley@arm.com void 53513954Sgiacomo.gabrielli@arm.com armMonitor(Addr address) override 53612749Sgiacomo.travaglini@arm.com { 53710259SAndrew.Bardsley@arm.com cpu->armMonitor(thread->threadId(), address); 53810259SAndrew.Bardsley@arm.com } 53910259SAndrew.Bardsley@arm.com 54013954Sgiacomo.gabrielli@arm.com bool 54113954Sgiacomo.gabrielli@arm.com mwait(PacketPtr pkt) override 54210259SAndrew.Bardsley@arm.com { 54310259SAndrew.Bardsley@arm.com return cpu->mwait(thread->threadId(), pkt); 54412748Sgiacomo.travaglini@arm.com } 54510259SAndrew.Bardsley@arm.com 54610259SAndrew.Bardsley@arm.com void 54710259SAndrew.Bardsley@arm.com mwaitAtomic(ThreadContext *tc) override 54810259SAndrew.Bardsley@arm.com { 54910259SAndrew.Bardsley@arm.com cpu->mwaitAtomic(thread->threadId(), tc, thread->dtb); 55010259SAndrew.Bardsley@arm.com } 55110259SAndrew.Bardsley@arm.com 55210259SAndrew.Bardsley@arm.com AddressMonitor * 55310259SAndrew.Bardsley@arm.com getAddrMonitor() override 55410259SAndrew.Bardsley@arm.com { 55510259SAndrew.Bardsley@arm.com return cpu->getCpuAddrMonitor(thread->threadId()); 55610259SAndrew.Bardsley@arm.com } 55710259SAndrew.Bardsley@arm.com 55810259SAndrew.Bardsley@arm.com#if THE_ISA == MIPS_ISA 55910259SAndrew.Bardsley@arm.com RegVal 56010259SAndrew.Bardsley@arm.com readRegOtherThread(const RegId& reg, ThreadID tid=InvalidThreadID) 56110259SAndrew.Bardsley@arm.com override 56210259SAndrew.Bardsley@arm.com { 56310259SAndrew.Bardsley@arm.com panic("Simple CPU models do not support multithreaded " 56410259SAndrew.Bardsley@arm.com "register access."); 56510259SAndrew.Bardsley@arm.com } 56610259SAndrew.Bardsley@arm.com 56710259SAndrew.Bardsley@arm.com void 56812749Sgiacomo.travaglini@arm.com setRegOtherThread(const RegId& reg, RegVal val, 56910259SAndrew.Bardsley@arm.com ThreadID tid=InvalidThreadID) override 57010259SAndrew.Bardsley@arm.com { 57110368SAndrew.Bardsley@arm.com panic("Simple CPU models do not support multithreaded " 57212749Sgiacomo.travaglini@arm.com "register access."); 57310259SAndrew.Bardsley@arm.com } 57410259SAndrew.Bardsley@arm.com#endif 57510259SAndrew.Bardsley@arm.com 57610259SAndrew.Bardsley@arm.com}; 57710259SAndrew.Bardsley@arm.com 57812749Sgiacomo.travaglini@arm.com#endif // __CPU_EXEC_CONTEXT_HH__ 57910259SAndrew.Bardsley@arm.com