exec_context.hh revision 12110
111147Smitch.hayenga@arm.com/* 212109SRekai.GonzalezAlberquilla@arm.com * Copyright (c) 2014-2016 ARM Limited 311147Smitch.hayenga@arm.com * All rights reserved 411147Smitch.hayenga@arm.com * 511147Smitch.hayenga@arm.com * The license below extends only to copyright in the software and shall 611147Smitch.hayenga@arm.com * not be construed as granting a license to any other intellectual 711147Smitch.hayenga@arm.com * property including but not limited to intellectual property relating 811147Smitch.hayenga@arm.com * to a hardware implementation of the functionality of the software 911147Smitch.hayenga@arm.com * licensed hereunder. You may use the software subject to the license 1011147Smitch.hayenga@arm.com * terms below provided that you ensure that this notice is replicated 1111147Smitch.hayenga@arm.com * unmodified and in its entirety in all distributions of the software, 1211147Smitch.hayenga@arm.com * modified or unmodified, in source code or in binary form. 1311147Smitch.hayenga@arm.com * 1411147Smitch.hayenga@arm.com * Copyright (c) 2002-2005 The Regents of The University of Michigan 1511147Smitch.hayenga@arm.com * All rights reserved. 1611147Smitch.hayenga@arm.com * 1711147Smitch.hayenga@arm.com * Redistribution and use in source and binary forms, with or without 1811147Smitch.hayenga@arm.com * modification, are permitted provided that the following conditions are 1911147Smitch.hayenga@arm.com * met: redistributions of source code must retain the above copyright 2011147Smitch.hayenga@arm.com * notice, this list of conditions and the following disclaimer; 2111147Smitch.hayenga@arm.com * redistributions in binary form must reproduce the above copyright 2211147Smitch.hayenga@arm.com * notice, this list of conditions and the following disclaimer in the 2311147Smitch.hayenga@arm.com * documentation and/or other materials provided with the distribution; 2411147Smitch.hayenga@arm.com * neither the name of the copyright holders nor the names of its 2511147Smitch.hayenga@arm.com * contributors may be used to endorse or promote products derived from 2611147Smitch.hayenga@arm.com * this software without specific prior written permission. 2711147Smitch.hayenga@arm.com * 2811147Smitch.hayenga@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2911147Smitch.hayenga@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 3011147Smitch.hayenga@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 3111147Smitch.hayenga@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 3211147Smitch.hayenga@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3311147Smitch.hayenga@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3411147Smitch.hayenga@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3511147Smitch.hayenga@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3611147Smitch.hayenga@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3711147Smitch.hayenga@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3811147Smitch.hayenga@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3911147Smitch.hayenga@arm.com * 4011147Smitch.hayenga@arm.com * Authors: Kevin Lim 4111147Smitch.hayenga@arm.com * Andreas Sandberg 4211147Smitch.hayenga@arm.com * Mitch Hayenga 4311147Smitch.hayenga@arm.com */ 4411147Smitch.hayenga@arm.com 4511147Smitch.hayenga@arm.com#ifndef __CPU_SIMPLE_EXEC_CONTEXT_HH__ 4611147Smitch.hayenga@arm.com#define __CPU_SIMPLE_EXEC_CONTEXT_HH__ 4711147Smitch.hayenga@arm.com 4811147Smitch.hayenga@arm.com#include "arch/registers.hh" 4911147Smitch.hayenga@arm.com#include "base/types.hh" 5011147Smitch.hayenga@arm.com#include "config/the_isa.hh" 5111147Smitch.hayenga@arm.com#include "cpu/base.hh" 5211147Smitch.hayenga@arm.com#include "cpu/exec_context.hh" 5312104Snathanael.premillieu@arm.com#include "cpu/reg_class.hh" 5411147Smitch.hayenga@arm.com#include "cpu/simple/base.hh" 5511147Smitch.hayenga@arm.com#include "cpu/static_inst_fwd.hh" 5611147Smitch.hayenga@arm.com#include "cpu/translation.hh" 5711608Snikos.nikoleris@arm.com#include "mem/request.hh" 5811147Smitch.hayenga@arm.com 5911147Smitch.hayenga@arm.comclass BaseSimpleCPU; 6011147Smitch.hayenga@arm.com 6111147Smitch.hayenga@arm.comclass SimpleExecContext : public ExecContext { 6211147Smitch.hayenga@arm.com protected: 6311147Smitch.hayenga@arm.com typedef TheISA::MiscReg MiscReg; 6411147Smitch.hayenga@arm.com typedef TheISA::FloatReg FloatReg; 6511147Smitch.hayenga@arm.com typedef TheISA::FloatRegBits FloatRegBits; 6611147Smitch.hayenga@arm.com typedef TheISA::CCReg CCReg; 6712109SRekai.GonzalezAlberquilla@arm.com using VecRegContainer = TheISA::VecRegContainer; 6812109SRekai.GonzalezAlberquilla@arm.com using VecElem = TheISA::VecElem; 6911147Smitch.hayenga@arm.com 7011147Smitch.hayenga@arm.com public: 7111147Smitch.hayenga@arm.com BaseSimpleCPU *cpu; 7211147Smitch.hayenga@arm.com SimpleThread* thread; 7311147Smitch.hayenga@arm.com 7411147Smitch.hayenga@arm.com // This is the offset from the current pc that fetch should be performed 7511147Smitch.hayenga@arm.com Addr fetchOffset; 7611147Smitch.hayenga@arm.com // This flag says to stay at the current pc. This is useful for 7711147Smitch.hayenga@arm.com // instructions which go beyond MachInst boundaries. 7811147Smitch.hayenga@arm.com bool stayAtPC; 7911147Smitch.hayenga@arm.com 8011147Smitch.hayenga@arm.com // Branch prediction 8111147Smitch.hayenga@arm.com TheISA::PCState predPC; 8211147Smitch.hayenga@arm.com 8311147Smitch.hayenga@arm.com /** PER-THREAD STATS */ 8411147Smitch.hayenga@arm.com 8511147Smitch.hayenga@arm.com // Number of simulated instructions 8611147Smitch.hayenga@arm.com Counter numInst; 8711147Smitch.hayenga@arm.com Stats::Scalar numInsts; 8811147Smitch.hayenga@arm.com Counter numOp; 8911147Smitch.hayenga@arm.com Stats::Scalar numOps; 9011147Smitch.hayenga@arm.com 9111147Smitch.hayenga@arm.com // Number of integer alu accesses 9211147Smitch.hayenga@arm.com Stats::Scalar numIntAluAccesses; 9311147Smitch.hayenga@arm.com 9411147Smitch.hayenga@arm.com // Number of float alu accesses 9511147Smitch.hayenga@arm.com Stats::Scalar numFpAluAccesses; 9611147Smitch.hayenga@arm.com 9712110SRekai.GonzalezAlberquilla@arm.com // Number of vector alu accesses 9812110SRekai.GonzalezAlberquilla@arm.com Stats::Scalar numVecAluAccesses; 9912110SRekai.GonzalezAlberquilla@arm.com 10011147Smitch.hayenga@arm.com // Number of function calls/returns 10111147Smitch.hayenga@arm.com Stats::Scalar numCallsReturns; 10211147Smitch.hayenga@arm.com 10311147Smitch.hayenga@arm.com // Conditional control instructions; 10411147Smitch.hayenga@arm.com Stats::Scalar numCondCtrlInsts; 10511147Smitch.hayenga@arm.com 10611147Smitch.hayenga@arm.com // Number of int instructions 10711147Smitch.hayenga@arm.com Stats::Scalar numIntInsts; 10811147Smitch.hayenga@arm.com 10911147Smitch.hayenga@arm.com // Number of float instructions 11011147Smitch.hayenga@arm.com Stats::Scalar numFpInsts; 11111147Smitch.hayenga@arm.com 11212110SRekai.GonzalezAlberquilla@arm.com // Number of vector instructions 11312110SRekai.GonzalezAlberquilla@arm.com Stats::Scalar numVecInsts; 11412110SRekai.GonzalezAlberquilla@arm.com 11511147Smitch.hayenga@arm.com // Number of integer register file accesses 11611147Smitch.hayenga@arm.com Stats::Scalar numIntRegReads; 11711147Smitch.hayenga@arm.com Stats::Scalar numIntRegWrites; 11811147Smitch.hayenga@arm.com 11911147Smitch.hayenga@arm.com // Number of float register file accesses 12011147Smitch.hayenga@arm.com Stats::Scalar numFpRegReads; 12111147Smitch.hayenga@arm.com Stats::Scalar numFpRegWrites; 12211147Smitch.hayenga@arm.com 12312109SRekai.GonzalezAlberquilla@arm.com // Number of vector register file accesses 12412109SRekai.GonzalezAlberquilla@arm.com mutable Stats::Scalar numVecRegReads; 12512109SRekai.GonzalezAlberquilla@arm.com Stats::Scalar numVecRegWrites; 12612109SRekai.GonzalezAlberquilla@arm.com 12711147Smitch.hayenga@arm.com // Number of condition code register file accesses 12811147Smitch.hayenga@arm.com Stats::Scalar numCCRegReads; 12911147Smitch.hayenga@arm.com Stats::Scalar numCCRegWrites; 13011147Smitch.hayenga@arm.com 13111147Smitch.hayenga@arm.com // Number of simulated memory references 13211147Smitch.hayenga@arm.com Stats::Scalar numMemRefs; 13311147Smitch.hayenga@arm.com Stats::Scalar numLoadInsts; 13411147Smitch.hayenga@arm.com Stats::Scalar numStoreInsts; 13511147Smitch.hayenga@arm.com 13611147Smitch.hayenga@arm.com // Number of idle cycles 13711147Smitch.hayenga@arm.com Stats::Formula numIdleCycles; 13811147Smitch.hayenga@arm.com 13911147Smitch.hayenga@arm.com // Number of busy cycles 14011147Smitch.hayenga@arm.com Stats::Formula numBusyCycles; 14111147Smitch.hayenga@arm.com 14211147Smitch.hayenga@arm.com // Number of simulated loads 14311147Smitch.hayenga@arm.com Counter numLoad; 14411147Smitch.hayenga@arm.com 14511147Smitch.hayenga@arm.com // Number of idle cycles 14611147Smitch.hayenga@arm.com Stats::Average notIdleFraction; 14711147Smitch.hayenga@arm.com Stats::Formula idleFraction; 14811147Smitch.hayenga@arm.com 14911147Smitch.hayenga@arm.com // Number of cycles stalled for I-cache responses 15011147Smitch.hayenga@arm.com Stats::Scalar icacheStallCycles; 15111147Smitch.hayenga@arm.com Counter lastIcacheStall; 15211147Smitch.hayenga@arm.com 15311147Smitch.hayenga@arm.com // Number of cycles stalled for D-cache responses 15411147Smitch.hayenga@arm.com Stats::Scalar dcacheStallCycles; 15511147Smitch.hayenga@arm.com Counter lastDcacheStall; 15611147Smitch.hayenga@arm.com 15711147Smitch.hayenga@arm.com /// @{ 15811147Smitch.hayenga@arm.com /// Total number of branches fetched 15911147Smitch.hayenga@arm.com Stats::Scalar numBranches; 16011147Smitch.hayenga@arm.com /// Number of branches predicted as taken 16111147Smitch.hayenga@arm.com Stats::Scalar numPredictedBranches; 16211147Smitch.hayenga@arm.com /// Number of misprediced branches 16311147Smitch.hayenga@arm.com Stats::Scalar numBranchMispred; 16411147Smitch.hayenga@arm.com /// @} 16511147Smitch.hayenga@arm.com 16611147Smitch.hayenga@arm.com // Instruction mix histogram by OpClass 16711147Smitch.hayenga@arm.com Stats::Vector statExecutedInstType; 16811147Smitch.hayenga@arm.com 16911147Smitch.hayenga@arm.com public: 17011147Smitch.hayenga@arm.com /** Constructor */ 17111147Smitch.hayenga@arm.com SimpleExecContext(BaseSimpleCPU* _cpu, SimpleThread* _thread) 17211147Smitch.hayenga@arm.com : cpu(_cpu), thread(_thread), fetchOffset(0), stayAtPC(false), 17311147Smitch.hayenga@arm.com numInst(0), numOp(0), numLoad(0), lastIcacheStall(0), lastDcacheStall(0) 17411147Smitch.hayenga@arm.com { } 17511147Smitch.hayenga@arm.com 17611147Smitch.hayenga@arm.com /** Reads an integer register. */ 17711168Sandreas.hansson@arm.com IntReg readIntRegOperand(const StaticInst *si, int idx) override 17811147Smitch.hayenga@arm.com { 17911147Smitch.hayenga@arm.com numIntRegReads++; 18012106SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->srcRegIdx(idx); 18112106SRekai.GonzalezAlberquilla@arm.com assert(reg.isIntReg()); 18212106SRekai.GonzalezAlberquilla@arm.com return thread->readIntReg(reg.index()); 18311147Smitch.hayenga@arm.com } 18411147Smitch.hayenga@arm.com 18511147Smitch.hayenga@arm.com /** Sets an integer register to a value. */ 18611168Sandreas.hansson@arm.com void setIntRegOperand(const StaticInst *si, int idx, IntReg val) override 18711147Smitch.hayenga@arm.com { 18811147Smitch.hayenga@arm.com numIntRegWrites++; 18912106SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->destRegIdx(idx); 19012106SRekai.GonzalezAlberquilla@arm.com assert(reg.isIntReg()); 19112106SRekai.GonzalezAlberquilla@arm.com thread->setIntReg(reg.index(), val); 19211147Smitch.hayenga@arm.com } 19311147Smitch.hayenga@arm.com 19411147Smitch.hayenga@arm.com /** Reads a floating point register of single register width. */ 19511168Sandreas.hansson@arm.com FloatReg readFloatRegOperand(const StaticInst *si, int idx) override 19611147Smitch.hayenga@arm.com { 19711147Smitch.hayenga@arm.com numFpRegReads++; 19812106SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->srcRegIdx(idx); 19912106SRekai.GonzalezAlberquilla@arm.com assert(reg.isFloatReg()); 20012106SRekai.GonzalezAlberquilla@arm.com return thread->readFloatReg(reg.index()); 20111147Smitch.hayenga@arm.com } 20211147Smitch.hayenga@arm.com 20311147Smitch.hayenga@arm.com /** Reads a floating point register in its binary format, instead 20411147Smitch.hayenga@arm.com * of by value. */ 20511168Sandreas.hansson@arm.com FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx) override 20611147Smitch.hayenga@arm.com { 20711147Smitch.hayenga@arm.com numFpRegReads++; 20812106SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->srcRegIdx(idx); 20912106SRekai.GonzalezAlberquilla@arm.com assert(reg.isFloatReg()); 21012106SRekai.GonzalezAlberquilla@arm.com return thread->readFloatRegBits(reg.index()); 21111147Smitch.hayenga@arm.com } 21211147Smitch.hayenga@arm.com 21311147Smitch.hayenga@arm.com /** Sets a floating point register of single width to a value. */ 21411168Sandreas.hansson@arm.com void setFloatRegOperand(const StaticInst *si, int idx, 21511168Sandreas.hansson@arm.com FloatReg val) override 21611147Smitch.hayenga@arm.com { 21711147Smitch.hayenga@arm.com numFpRegWrites++; 21812106SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->destRegIdx(idx); 21912106SRekai.GonzalezAlberquilla@arm.com assert(reg.isFloatReg()); 22012106SRekai.GonzalezAlberquilla@arm.com thread->setFloatReg(reg.index(), val); 22111147Smitch.hayenga@arm.com } 22211147Smitch.hayenga@arm.com 22311147Smitch.hayenga@arm.com /** Sets the bits of a floating point register of single width 22411147Smitch.hayenga@arm.com * to a binary value. */ 22511147Smitch.hayenga@arm.com void setFloatRegOperandBits(const StaticInst *si, int idx, 22611168Sandreas.hansson@arm.com FloatRegBits val) override 22711147Smitch.hayenga@arm.com { 22811147Smitch.hayenga@arm.com numFpRegWrites++; 22912106SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->destRegIdx(idx); 23012106SRekai.GonzalezAlberquilla@arm.com assert(reg.isFloatReg()); 23112106SRekai.GonzalezAlberquilla@arm.com thread->setFloatRegBits(reg.index(), val); 23211147Smitch.hayenga@arm.com } 23311147Smitch.hayenga@arm.com 23412109SRekai.GonzalezAlberquilla@arm.com /** Reads a vector register. */ 23512109SRekai.GonzalezAlberquilla@arm.com const VecRegContainer& 23612109SRekai.GonzalezAlberquilla@arm.com readVecRegOperand(const StaticInst *si, int idx) const override 23712109SRekai.GonzalezAlberquilla@arm.com { 23812109SRekai.GonzalezAlberquilla@arm.com numVecRegReads++; 23912109SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->srcRegIdx(idx); 24012109SRekai.GonzalezAlberquilla@arm.com assert(reg.isVecReg()); 24112109SRekai.GonzalezAlberquilla@arm.com return thread->readVecReg(reg); 24212109SRekai.GonzalezAlberquilla@arm.com } 24312109SRekai.GonzalezAlberquilla@arm.com 24412109SRekai.GonzalezAlberquilla@arm.com /** Reads a vector register for modification. */ 24512109SRekai.GonzalezAlberquilla@arm.com VecRegContainer& 24612109SRekai.GonzalezAlberquilla@arm.com getWritableVecRegOperand(const StaticInst *si, int idx) override 24712109SRekai.GonzalezAlberquilla@arm.com { 24812109SRekai.GonzalezAlberquilla@arm.com numVecRegWrites++; 24912109SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->destRegIdx(idx); 25012109SRekai.GonzalezAlberquilla@arm.com assert(reg.isVecReg()); 25112109SRekai.GonzalezAlberquilla@arm.com return thread->getWritableVecReg(reg); 25212109SRekai.GonzalezAlberquilla@arm.com } 25312109SRekai.GonzalezAlberquilla@arm.com 25412109SRekai.GonzalezAlberquilla@arm.com /** Sets a vector register to a value. */ 25512109SRekai.GonzalezAlberquilla@arm.com void setVecRegOperand(const StaticInst *si, int idx, 25612109SRekai.GonzalezAlberquilla@arm.com const VecRegContainer& val) override 25712109SRekai.GonzalezAlberquilla@arm.com { 25812109SRekai.GonzalezAlberquilla@arm.com numVecRegWrites++; 25912109SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->destRegIdx(idx); 26012109SRekai.GonzalezAlberquilla@arm.com assert(reg.isVecReg()); 26112109SRekai.GonzalezAlberquilla@arm.com thread->setVecReg(reg, val); 26212109SRekai.GonzalezAlberquilla@arm.com } 26312109SRekai.GonzalezAlberquilla@arm.com 26412109SRekai.GonzalezAlberquilla@arm.com /** Vector Register Lane Interfaces. */ 26512109SRekai.GonzalezAlberquilla@arm.com /** @{ */ 26612109SRekai.GonzalezAlberquilla@arm.com /** Reads source vector lane. */ 26712109SRekai.GonzalezAlberquilla@arm.com template <typename VecElem> 26812109SRekai.GonzalezAlberquilla@arm.com VecLaneT<VecElem, true> 26912109SRekai.GonzalezAlberquilla@arm.com readVecLaneOperand(const StaticInst *si, int idx) const 27012109SRekai.GonzalezAlberquilla@arm.com { 27112109SRekai.GonzalezAlberquilla@arm.com numVecRegReads++; 27212109SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->srcRegIdx(idx); 27312109SRekai.GonzalezAlberquilla@arm.com assert(reg.isVecReg()); 27412109SRekai.GonzalezAlberquilla@arm.com return thread->readVecLane<VecElem>(reg); 27512109SRekai.GonzalezAlberquilla@arm.com } 27612109SRekai.GonzalezAlberquilla@arm.com /** Reads source vector 8bit operand. */ 27712109SRekai.GonzalezAlberquilla@arm.com virtual ConstVecLane8 27812109SRekai.GonzalezAlberquilla@arm.com readVec8BitLaneOperand(const StaticInst *si, int idx) const 27912109SRekai.GonzalezAlberquilla@arm.com override 28012109SRekai.GonzalezAlberquilla@arm.com { return readVecLaneOperand<uint8_t>(si, idx); } 28112109SRekai.GonzalezAlberquilla@arm.com 28212109SRekai.GonzalezAlberquilla@arm.com /** Reads source vector 16bit operand. */ 28312109SRekai.GonzalezAlberquilla@arm.com virtual ConstVecLane16 28412109SRekai.GonzalezAlberquilla@arm.com readVec16BitLaneOperand(const StaticInst *si, int idx) const 28512109SRekai.GonzalezAlberquilla@arm.com override 28612109SRekai.GonzalezAlberquilla@arm.com { return readVecLaneOperand<uint16_t>(si, idx); } 28712109SRekai.GonzalezAlberquilla@arm.com 28812109SRekai.GonzalezAlberquilla@arm.com /** Reads source vector 32bit operand. */ 28912109SRekai.GonzalezAlberquilla@arm.com virtual ConstVecLane32 29012109SRekai.GonzalezAlberquilla@arm.com readVec32BitLaneOperand(const StaticInst *si, int idx) const 29112109SRekai.GonzalezAlberquilla@arm.com override 29212109SRekai.GonzalezAlberquilla@arm.com { return readVecLaneOperand<uint32_t>(si, idx); } 29312109SRekai.GonzalezAlberquilla@arm.com 29412109SRekai.GonzalezAlberquilla@arm.com /** Reads source vector 64bit operand. */ 29512109SRekai.GonzalezAlberquilla@arm.com virtual ConstVecLane64 29612109SRekai.GonzalezAlberquilla@arm.com readVec64BitLaneOperand(const StaticInst *si, int idx) const 29712109SRekai.GonzalezAlberquilla@arm.com override 29812109SRekai.GonzalezAlberquilla@arm.com { return readVecLaneOperand<uint64_t>(si, idx); } 29912109SRekai.GonzalezAlberquilla@arm.com 30012109SRekai.GonzalezAlberquilla@arm.com /** Write a lane of the destination vector operand. */ 30112109SRekai.GonzalezAlberquilla@arm.com template <typename LD> 30212109SRekai.GonzalezAlberquilla@arm.com void 30312109SRekai.GonzalezAlberquilla@arm.com setVecLaneOperandT(const StaticInst *si, int idx, 30412109SRekai.GonzalezAlberquilla@arm.com const LD& val) 30512109SRekai.GonzalezAlberquilla@arm.com { 30612109SRekai.GonzalezAlberquilla@arm.com numVecRegWrites++; 30712109SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->destRegIdx(idx); 30812109SRekai.GonzalezAlberquilla@arm.com assert(reg.isVecReg()); 30912109SRekai.GonzalezAlberquilla@arm.com return thread->setVecLane(reg, val); 31012109SRekai.GonzalezAlberquilla@arm.com } 31112109SRekai.GonzalezAlberquilla@arm.com /** Write a lane of the destination vector operand. */ 31212109SRekai.GonzalezAlberquilla@arm.com virtual void 31312109SRekai.GonzalezAlberquilla@arm.com setVecLaneOperand(const StaticInst *si, int idx, 31412109SRekai.GonzalezAlberquilla@arm.com const LaneData<LaneSize::Byte>& val) override 31512109SRekai.GonzalezAlberquilla@arm.com { return setVecLaneOperandT(si, idx, val); } 31612109SRekai.GonzalezAlberquilla@arm.com /** Write a lane of the destination vector operand. */ 31712109SRekai.GonzalezAlberquilla@arm.com virtual void 31812109SRekai.GonzalezAlberquilla@arm.com setVecLaneOperand(const StaticInst *si, int idx, 31912109SRekai.GonzalezAlberquilla@arm.com const LaneData<LaneSize::TwoByte>& val) override 32012109SRekai.GonzalezAlberquilla@arm.com { return setVecLaneOperandT(si, idx, val); } 32112109SRekai.GonzalezAlberquilla@arm.com /** Write a lane of the destination vector operand. */ 32212109SRekai.GonzalezAlberquilla@arm.com virtual void 32312109SRekai.GonzalezAlberquilla@arm.com setVecLaneOperand(const StaticInst *si, int idx, 32412109SRekai.GonzalezAlberquilla@arm.com const LaneData<LaneSize::FourByte>& val) override 32512109SRekai.GonzalezAlberquilla@arm.com { return setVecLaneOperandT(si, idx, val); } 32612109SRekai.GonzalezAlberquilla@arm.com /** Write a lane of the destination vector operand. */ 32712109SRekai.GonzalezAlberquilla@arm.com virtual void 32812109SRekai.GonzalezAlberquilla@arm.com setVecLaneOperand(const StaticInst *si, int idx, 32912109SRekai.GonzalezAlberquilla@arm.com const LaneData<LaneSize::EightByte>& val) override 33012109SRekai.GonzalezAlberquilla@arm.com { return setVecLaneOperandT(si, idx, val); } 33112109SRekai.GonzalezAlberquilla@arm.com /** @} */ 33212109SRekai.GonzalezAlberquilla@arm.com 33312109SRekai.GonzalezAlberquilla@arm.com /** Reads an element of a vector register. */ 33412109SRekai.GonzalezAlberquilla@arm.com VecElem readVecElemOperand(const StaticInst *si, int idx) const override 33512109SRekai.GonzalezAlberquilla@arm.com { 33612109SRekai.GonzalezAlberquilla@arm.com numVecRegReads++; 33712109SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->destRegIdx(idx); 33812109SRekai.GonzalezAlberquilla@arm.com assert(reg.isVecElem()); 33912109SRekai.GonzalezAlberquilla@arm.com return thread->readVecElem(reg); 34012109SRekai.GonzalezAlberquilla@arm.com } 34112109SRekai.GonzalezAlberquilla@arm.com 34212109SRekai.GonzalezAlberquilla@arm.com /** Sets an element of a vector register to a value. */ 34312109SRekai.GonzalezAlberquilla@arm.com void setVecElemOperand(const StaticInst *si, int idx, 34412109SRekai.GonzalezAlberquilla@arm.com const VecElem val) override 34512109SRekai.GonzalezAlberquilla@arm.com { 34612109SRekai.GonzalezAlberquilla@arm.com numVecRegWrites++; 34712109SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->destRegIdx(idx); 34812109SRekai.GonzalezAlberquilla@arm.com assert(reg.isVecElem()); 34912109SRekai.GonzalezAlberquilla@arm.com thread->setVecElem(reg, val); 35012109SRekai.GonzalezAlberquilla@arm.com } 35112109SRekai.GonzalezAlberquilla@arm.com 35211168Sandreas.hansson@arm.com CCReg readCCRegOperand(const StaticInst *si, int idx) override 35311147Smitch.hayenga@arm.com { 35411147Smitch.hayenga@arm.com numCCRegReads++; 35512106SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->srcRegIdx(idx); 35612106SRekai.GonzalezAlberquilla@arm.com assert(reg.isCCReg()); 35712106SRekai.GonzalezAlberquilla@arm.com return thread->readCCReg(reg.index()); 35811147Smitch.hayenga@arm.com } 35911147Smitch.hayenga@arm.com 36011168Sandreas.hansson@arm.com void setCCRegOperand(const StaticInst *si, int idx, CCReg val) override 36111147Smitch.hayenga@arm.com { 36211147Smitch.hayenga@arm.com numCCRegWrites++; 36312106SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->destRegIdx(idx); 36412106SRekai.GonzalezAlberquilla@arm.com assert(reg.isCCReg()); 36512106SRekai.GonzalezAlberquilla@arm.com thread->setCCReg(reg.index(), val); 36611147Smitch.hayenga@arm.com } 36711147Smitch.hayenga@arm.com 36811168Sandreas.hansson@arm.com MiscReg readMiscRegOperand(const StaticInst *si, int idx) override 36911147Smitch.hayenga@arm.com { 37011147Smitch.hayenga@arm.com numIntRegReads++; 37112106SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->srcRegIdx(idx); 37212106SRekai.GonzalezAlberquilla@arm.com assert(reg.isMiscReg()); 37312106SRekai.GonzalezAlberquilla@arm.com return thread->readMiscReg(reg.index()); 37411147Smitch.hayenga@arm.com } 37511147Smitch.hayenga@arm.com 37611168Sandreas.hansson@arm.com void setMiscRegOperand(const StaticInst *si, int idx, 37711168Sandreas.hansson@arm.com const MiscReg &val) override 37811147Smitch.hayenga@arm.com { 37911147Smitch.hayenga@arm.com numIntRegWrites++; 38012106SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->destRegIdx(idx); 38112106SRekai.GonzalezAlberquilla@arm.com assert(reg.isMiscReg()); 38212106SRekai.GonzalezAlberquilla@arm.com thread->setMiscReg(reg.index(), val); 38311147Smitch.hayenga@arm.com } 38411147Smitch.hayenga@arm.com 38511147Smitch.hayenga@arm.com /** 38611147Smitch.hayenga@arm.com * Reads a miscellaneous register, handling any architectural 38711147Smitch.hayenga@arm.com * side effects due to reading that register. 38811147Smitch.hayenga@arm.com */ 38911168Sandreas.hansson@arm.com MiscReg readMiscReg(int misc_reg) override 39011147Smitch.hayenga@arm.com { 39111147Smitch.hayenga@arm.com numIntRegReads++; 39211147Smitch.hayenga@arm.com return thread->readMiscReg(misc_reg); 39311147Smitch.hayenga@arm.com } 39411147Smitch.hayenga@arm.com 39511147Smitch.hayenga@arm.com /** 39611147Smitch.hayenga@arm.com * Sets a miscellaneous register, handling any architectural 39711147Smitch.hayenga@arm.com * side effects due to writing that register. 39811147Smitch.hayenga@arm.com */ 39911168Sandreas.hansson@arm.com void setMiscReg(int misc_reg, const MiscReg &val) override 40011147Smitch.hayenga@arm.com { 40111147Smitch.hayenga@arm.com numIntRegWrites++; 40211147Smitch.hayenga@arm.com thread->setMiscReg(misc_reg, val); 40311147Smitch.hayenga@arm.com } 40411147Smitch.hayenga@arm.com 40511168Sandreas.hansson@arm.com PCState pcState() const override 40611147Smitch.hayenga@arm.com { 40711147Smitch.hayenga@arm.com return thread->pcState(); 40811147Smitch.hayenga@arm.com } 40911147Smitch.hayenga@arm.com 41011168Sandreas.hansson@arm.com void pcState(const PCState &val) override 41111147Smitch.hayenga@arm.com { 41211147Smitch.hayenga@arm.com thread->pcState(val); 41311147Smitch.hayenga@arm.com } 41411147Smitch.hayenga@arm.com 41511147Smitch.hayenga@arm.com 41611147Smitch.hayenga@arm.com /** 41711147Smitch.hayenga@arm.com * Record the effective address of the instruction. 41811147Smitch.hayenga@arm.com * 41911147Smitch.hayenga@arm.com * @note Only valid for memory ops. 42011147Smitch.hayenga@arm.com */ 42111168Sandreas.hansson@arm.com void setEA(Addr EA) override 42211147Smitch.hayenga@arm.com { panic("BaseSimpleCPU::setEA() not implemented\n"); } 42311147Smitch.hayenga@arm.com 42411147Smitch.hayenga@arm.com /** 42511147Smitch.hayenga@arm.com * Get the effective address of the instruction. 42611147Smitch.hayenga@arm.com * 42711147Smitch.hayenga@arm.com * @note Only valid for memory ops. 42811147Smitch.hayenga@arm.com */ 42911168Sandreas.hansson@arm.com Addr getEA() const override 43011147Smitch.hayenga@arm.com { panic("BaseSimpleCPU::getEA() not implemented\n"); } 43111147Smitch.hayenga@arm.com 43211147Smitch.hayenga@arm.com Fault readMem(Addr addr, uint8_t *data, unsigned int size, 43311608Snikos.nikoleris@arm.com Request::Flags flags) override 43411147Smitch.hayenga@arm.com { 43511147Smitch.hayenga@arm.com return cpu->readMem(addr, data, size, flags); 43611147Smitch.hayenga@arm.com } 43711147Smitch.hayenga@arm.com 43811303Ssteve.reinhardt@amd.com Fault initiateMemRead(Addr addr, unsigned int size, 43911608Snikos.nikoleris@arm.com Request::Flags flags) override 44011303Ssteve.reinhardt@amd.com { 44111303Ssteve.reinhardt@amd.com return cpu->initiateMemRead(addr, size, flags); 44211303Ssteve.reinhardt@amd.com } 44311303Ssteve.reinhardt@amd.com 44411147Smitch.hayenga@arm.com Fault writeMem(uint8_t *data, unsigned int size, Addr addr, 44511608Snikos.nikoleris@arm.com Request::Flags flags, uint64_t *res) override 44611147Smitch.hayenga@arm.com { 44711147Smitch.hayenga@arm.com return cpu->writeMem(data, size, addr, flags, res); 44811147Smitch.hayenga@arm.com } 44911147Smitch.hayenga@arm.com 45011147Smitch.hayenga@arm.com /** 45111147Smitch.hayenga@arm.com * Sets the number of consecutive store conditional failures. 45211147Smitch.hayenga@arm.com */ 45311168Sandreas.hansson@arm.com void setStCondFailures(unsigned int sc_failures) override 45411147Smitch.hayenga@arm.com { 45511147Smitch.hayenga@arm.com thread->setStCondFailures(sc_failures); 45611147Smitch.hayenga@arm.com } 45711147Smitch.hayenga@arm.com 45811147Smitch.hayenga@arm.com /** 45911147Smitch.hayenga@arm.com * Returns the number of consecutive store conditional failures. 46011147Smitch.hayenga@arm.com */ 46111168Sandreas.hansson@arm.com unsigned int readStCondFailures() const override 46211147Smitch.hayenga@arm.com { 46311147Smitch.hayenga@arm.com return thread->readStCondFailures(); 46411147Smitch.hayenga@arm.com } 46511147Smitch.hayenga@arm.com 46611147Smitch.hayenga@arm.com /** 46711147Smitch.hayenga@arm.com * Executes a syscall specified by the callnum. 46811147Smitch.hayenga@arm.com */ 46911877Sbrandon.potter@amd.com void syscall(int64_t callnum, Fault *fault) override 47011147Smitch.hayenga@arm.com { 47111147Smitch.hayenga@arm.com if (FullSystem) 47211147Smitch.hayenga@arm.com panic("Syscall emulation isn't available in FS mode."); 47311147Smitch.hayenga@arm.com 47411877Sbrandon.potter@amd.com thread->syscall(callnum, fault); 47511147Smitch.hayenga@arm.com } 47611147Smitch.hayenga@arm.com 47711147Smitch.hayenga@arm.com /** Returns a pointer to the ThreadContext. */ 47811168Sandreas.hansson@arm.com ThreadContext *tcBase() override 47911147Smitch.hayenga@arm.com { 48011147Smitch.hayenga@arm.com return thread->getTC(); 48111147Smitch.hayenga@arm.com } 48211147Smitch.hayenga@arm.com 48311147Smitch.hayenga@arm.com /** 48411147Smitch.hayenga@arm.com * Somewhat Alpha-specific function that handles returning from an 48511147Smitch.hayenga@arm.com * error or interrupt. 48611147Smitch.hayenga@arm.com */ 48711168Sandreas.hansson@arm.com Fault hwrei() override 48811147Smitch.hayenga@arm.com { 48911147Smitch.hayenga@arm.com return thread->hwrei(); 49011147Smitch.hayenga@arm.com } 49111147Smitch.hayenga@arm.com 49211147Smitch.hayenga@arm.com /** 49311147Smitch.hayenga@arm.com * Check for special simulator handling of specific PAL calls. If 49411147Smitch.hayenga@arm.com * return value is false, actual PAL call will be suppressed. 49511147Smitch.hayenga@arm.com */ 49611168Sandreas.hansson@arm.com bool simPalCheck(int palFunc) override 49711147Smitch.hayenga@arm.com { 49811147Smitch.hayenga@arm.com return thread->simPalCheck(palFunc); 49911147Smitch.hayenga@arm.com } 50011147Smitch.hayenga@arm.com 50111168Sandreas.hansson@arm.com bool readPredicate() override 50211147Smitch.hayenga@arm.com { 50311147Smitch.hayenga@arm.com return thread->readPredicate(); 50411147Smitch.hayenga@arm.com } 50511147Smitch.hayenga@arm.com 50611168Sandreas.hansson@arm.com void setPredicate(bool val) override 50711147Smitch.hayenga@arm.com { 50811147Smitch.hayenga@arm.com thread->setPredicate(val); 50911147Smitch.hayenga@arm.com 51011147Smitch.hayenga@arm.com if (cpu->traceData) { 51111147Smitch.hayenga@arm.com cpu->traceData->setPredicate(val); 51211147Smitch.hayenga@arm.com } 51311147Smitch.hayenga@arm.com } 51411147Smitch.hayenga@arm.com 51511147Smitch.hayenga@arm.com /** 51611147Smitch.hayenga@arm.com * Invalidate a page in the DTLB <i>and</i> ITLB. 51711147Smitch.hayenga@arm.com */ 51811168Sandreas.hansson@arm.com void demapPage(Addr vaddr, uint64_t asn) override 51911147Smitch.hayenga@arm.com { 52011147Smitch.hayenga@arm.com thread->demapPage(vaddr, asn); 52111147Smitch.hayenga@arm.com } 52211147Smitch.hayenga@arm.com 52311168Sandreas.hansson@arm.com void armMonitor(Addr address) override 52411147Smitch.hayenga@arm.com { 52511148Smitch.hayenga@arm.com cpu->armMonitor(thread->threadId(), address); 52611147Smitch.hayenga@arm.com } 52711147Smitch.hayenga@arm.com 52811168Sandreas.hansson@arm.com bool mwait(PacketPtr pkt) override 52911147Smitch.hayenga@arm.com { 53011148Smitch.hayenga@arm.com return cpu->mwait(thread->threadId(), pkt); 53111147Smitch.hayenga@arm.com } 53211147Smitch.hayenga@arm.com 53311168Sandreas.hansson@arm.com void mwaitAtomic(ThreadContext *tc) override 53411147Smitch.hayenga@arm.com { 53511148Smitch.hayenga@arm.com cpu->mwaitAtomic(thread->threadId(), tc, thread->dtb); 53611147Smitch.hayenga@arm.com } 53711147Smitch.hayenga@arm.com 53811168Sandreas.hansson@arm.com AddressMonitor *getAddrMonitor() override 53911147Smitch.hayenga@arm.com { 54011148Smitch.hayenga@arm.com return cpu->getCpuAddrMonitor(thread->threadId()); 54111147Smitch.hayenga@arm.com } 54211147Smitch.hayenga@arm.com 54311147Smitch.hayenga@arm.com#if THE_ISA == MIPS_ISA 54412106SRekai.GonzalezAlberquilla@arm.com MiscReg readRegOtherThread(const RegId& reg, 54512106SRekai.GonzalezAlberquilla@arm.com ThreadID tid = InvalidThreadID) 54611168Sandreas.hansson@arm.com override 54711147Smitch.hayenga@arm.com { 54811147Smitch.hayenga@arm.com panic("Simple CPU models do not support multithreaded " 54911147Smitch.hayenga@arm.com "register access."); 55011147Smitch.hayenga@arm.com } 55111147Smitch.hayenga@arm.com 55212106SRekai.GonzalezAlberquilla@arm.com void setRegOtherThread(const RegId& reg, MiscReg val, 55311168Sandreas.hansson@arm.com ThreadID tid = InvalidThreadID) override 55411147Smitch.hayenga@arm.com { 55511147Smitch.hayenga@arm.com panic("Simple CPU models do not support multithreaded " 55611147Smitch.hayenga@arm.com "register access."); 55711147Smitch.hayenga@arm.com } 55811147Smitch.hayenga@arm.com 55911147Smitch.hayenga@arm.com#endif 56011147Smitch.hayenga@arm.com 56111147Smitch.hayenga@arm.com}; 56211147Smitch.hayenga@arm.com 56311147Smitch.hayenga@arm.com#endif // __CPU_EXEC_CONTEXT_HH__ 564