exec_context.hh revision 12106
111147Smitch.hayenga@arm.com/* 211147Smitch.hayenga@arm.com * Copyright (c) 2014-2015 ARM Limited 311147Smitch.hayenga@arm.com * All rights reserved 411147Smitch.hayenga@arm.com * 511147Smitch.hayenga@arm.com * The license below extends only to copyright in the software and shall 611147Smitch.hayenga@arm.com * not be construed as granting a license to any other intellectual 711147Smitch.hayenga@arm.com * property including but not limited to intellectual property relating 811147Smitch.hayenga@arm.com * to a hardware implementation of the functionality of the software 911147Smitch.hayenga@arm.com * licensed hereunder. You may use the software subject to the license 1011147Smitch.hayenga@arm.com * terms below provided that you ensure that this notice is replicated 1111147Smitch.hayenga@arm.com * unmodified and in its entirety in all distributions of the software, 1211147Smitch.hayenga@arm.com * modified or unmodified, in source code or in binary form. 1311147Smitch.hayenga@arm.com * 1411147Smitch.hayenga@arm.com * Copyright (c) 2002-2005 The Regents of The University of Michigan 1511147Smitch.hayenga@arm.com * All rights reserved. 1611147Smitch.hayenga@arm.com * 1711147Smitch.hayenga@arm.com * Redistribution and use in source and binary forms, with or without 1811147Smitch.hayenga@arm.com * modification, are permitted provided that the following conditions are 1911147Smitch.hayenga@arm.com * met: redistributions of source code must retain the above copyright 2011147Smitch.hayenga@arm.com * notice, this list of conditions and the following disclaimer; 2111147Smitch.hayenga@arm.com * redistributions in binary form must reproduce the above copyright 2211147Smitch.hayenga@arm.com * notice, this list of conditions and the following disclaimer in the 2311147Smitch.hayenga@arm.com * documentation and/or other materials provided with the distribution; 2411147Smitch.hayenga@arm.com * neither the name of the copyright holders nor the names of its 2511147Smitch.hayenga@arm.com * contributors may be used to endorse or promote products derived from 2611147Smitch.hayenga@arm.com * this software without specific prior written permission. 2711147Smitch.hayenga@arm.com * 2811147Smitch.hayenga@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2911147Smitch.hayenga@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 3011147Smitch.hayenga@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 3111147Smitch.hayenga@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 3211147Smitch.hayenga@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3311147Smitch.hayenga@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3411147Smitch.hayenga@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3511147Smitch.hayenga@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3611147Smitch.hayenga@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3711147Smitch.hayenga@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3811147Smitch.hayenga@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3911147Smitch.hayenga@arm.com * 4011147Smitch.hayenga@arm.com * Authors: Kevin Lim 4111147Smitch.hayenga@arm.com * Andreas Sandberg 4211147Smitch.hayenga@arm.com * Mitch Hayenga 4311147Smitch.hayenga@arm.com */ 4411147Smitch.hayenga@arm.com 4511147Smitch.hayenga@arm.com#ifndef __CPU_SIMPLE_EXEC_CONTEXT_HH__ 4611147Smitch.hayenga@arm.com#define __CPU_SIMPLE_EXEC_CONTEXT_HH__ 4711147Smitch.hayenga@arm.com 4811147Smitch.hayenga@arm.com#include "arch/registers.hh" 4911147Smitch.hayenga@arm.com#include "base/types.hh" 5011147Smitch.hayenga@arm.com#include "config/the_isa.hh" 5111147Smitch.hayenga@arm.com#include "cpu/base.hh" 5211147Smitch.hayenga@arm.com#include "cpu/exec_context.hh" 5312104Snathanael.premillieu@arm.com#include "cpu/reg_class.hh" 5411147Smitch.hayenga@arm.com#include "cpu/simple/base.hh" 5511147Smitch.hayenga@arm.com#include "cpu/static_inst_fwd.hh" 5611147Smitch.hayenga@arm.com#include "cpu/translation.hh" 5711608Snikos.nikoleris@arm.com#include "mem/request.hh" 5811147Smitch.hayenga@arm.com 5911147Smitch.hayenga@arm.comclass BaseSimpleCPU; 6011147Smitch.hayenga@arm.com 6111147Smitch.hayenga@arm.comclass SimpleExecContext : public ExecContext { 6211147Smitch.hayenga@arm.com protected: 6311147Smitch.hayenga@arm.com typedef TheISA::MiscReg MiscReg; 6411147Smitch.hayenga@arm.com typedef TheISA::FloatReg FloatReg; 6511147Smitch.hayenga@arm.com typedef TheISA::FloatRegBits FloatRegBits; 6611147Smitch.hayenga@arm.com typedef TheISA::CCReg CCReg; 6711147Smitch.hayenga@arm.com 6811147Smitch.hayenga@arm.com public: 6911147Smitch.hayenga@arm.com BaseSimpleCPU *cpu; 7011147Smitch.hayenga@arm.com SimpleThread* thread; 7111147Smitch.hayenga@arm.com 7211147Smitch.hayenga@arm.com // This is the offset from the current pc that fetch should be performed 7311147Smitch.hayenga@arm.com Addr fetchOffset; 7411147Smitch.hayenga@arm.com // This flag says to stay at the current pc. This is useful for 7511147Smitch.hayenga@arm.com // instructions which go beyond MachInst boundaries. 7611147Smitch.hayenga@arm.com bool stayAtPC; 7711147Smitch.hayenga@arm.com 7811147Smitch.hayenga@arm.com // Branch prediction 7911147Smitch.hayenga@arm.com TheISA::PCState predPC; 8011147Smitch.hayenga@arm.com 8111147Smitch.hayenga@arm.com /** PER-THREAD STATS */ 8211147Smitch.hayenga@arm.com 8311147Smitch.hayenga@arm.com // Number of simulated instructions 8411147Smitch.hayenga@arm.com Counter numInst; 8511147Smitch.hayenga@arm.com Stats::Scalar numInsts; 8611147Smitch.hayenga@arm.com Counter numOp; 8711147Smitch.hayenga@arm.com Stats::Scalar numOps; 8811147Smitch.hayenga@arm.com 8911147Smitch.hayenga@arm.com // Number of integer alu accesses 9011147Smitch.hayenga@arm.com Stats::Scalar numIntAluAccesses; 9111147Smitch.hayenga@arm.com 9211147Smitch.hayenga@arm.com // Number of float alu accesses 9311147Smitch.hayenga@arm.com Stats::Scalar numFpAluAccesses; 9411147Smitch.hayenga@arm.com 9511147Smitch.hayenga@arm.com // Number of function calls/returns 9611147Smitch.hayenga@arm.com Stats::Scalar numCallsReturns; 9711147Smitch.hayenga@arm.com 9811147Smitch.hayenga@arm.com // Conditional control instructions; 9911147Smitch.hayenga@arm.com Stats::Scalar numCondCtrlInsts; 10011147Smitch.hayenga@arm.com 10111147Smitch.hayenga@arm.com // Number of int instructions 10211147Smitch.hayenga@arm.com Stats::Scalar numIntInsts; 10311147Smitch.hayenga@arm.com 10411147Smitch.hayenga@arm.com // Number of float instructions 10511147Smitch.hayenga@arm.com Stats::Scalar numFpInsts; 10611147Smitch.hayenga@arm.com 10711147Smitch.hayenga@arm.com // Number of integer register file accesses 10811147Smitch.hayenga@arm.com Stats::Scalar numIntRegReads; 10911147Smitch.hayenga@arm.com Stats::Scalar numIntRegWrites; 11011147Smitch.hayenga@arm.com 11111147Smitch.hayenga@arm.com // Number of float register file accesses 11211147Smitch.hayenga@arm.com Stats::Scalar numFpRegReads; 11311147Smitch.hayenga@arm.com Stats::Scalar numFpRegWrites; 11411147Smitch.hayenga@arm.com 11511147Smitch.hayenga@arm.com // Number of condition code register file accesses 11611147Smitch.hayenga@arm.com Stats::Scalar numCCRegReads; 11711147Smitch.hayenga@arm.com Stats::Scalar numCCRegWrites; 11811147Smitch.hayenga@arm.com 11911147Smitch.hayenga@arm.com // Number of simulated memory references 12011147Smitch.hayenga@arm.com Stats::Scalar numMemRefs; 12111147Smitch.hayenga@arm.com Stats::Scalar numLoadInsts; 12211147Smitch.hayenga@arm.com Stats::Scalar numStoreInsts; 12311147Smitch.hayenga@arm.com 12411147Smitch.hayenga@arm.com // Number of idle cycles 12511147Smitch.hayenga@arm.com Stats::Formula numIdleCycles; 12611147Smitch.hayenga@arm.com 12711147Smitch.hayenga@arm.com // Number of busy cycles 12811147Smitch.hayenga@arm.com Stats::Formula numBusyCycles; 12911147Smitch.hayenga@arm.com 13011147Smitch.hayenga@arm.com // Number of simulated loads 13111147Smitch.hayenga@arm.com Counter numLoad; 13211147Smitch.hayenga@arm.com 13311147Smitch.hayenga@arm.com // Number of idle cycles 13411147Smitch.hayenga@arm.com Stats::Average notIdleFraction; 13511147Smitch.hayenga@arm.com Stats::Formula idleFraction; 13611147Smitch.hayenga@arm.com 13711147Smitch.hayenga@arm.com // Number of cycles stalled for I-cache responses 13811147Smitch.hayenga@arm.com Stats::Scalar icacheStallCycles; 13911147Smitch.hayenga@arm.com Counter lastIcacheStall; 14011147Smitch.hayenga@arm.com 14111147Smitch.hayenga@arm.com // Number of cycles stalled for D-cache responses 14211147Smitch.hayenga@arm.com Stats::Scalar dcacheStallCycles; 14311147Smitch.hayenga@arm.com Counter lastDcacheStall; 14411147Smitch.hayenga@arm.com 14511147Smitch.hayenga@arm.com /// @{ 14611147Smitch.hayenga@arm.com /// Total number of branches fetched 14711147Smitch.hayenga@arm.com Stats::Scalar numBranches; 14811147Smitch.hayenga@arm.com /// Number of branches predicted as taken 14911147Smitch.hayenga@arm.com Stats::Scalar numPredictedBranches; 15011147Smitch.hayenga@arm.com /// Number of misprediced branches 15111147Smitch.hayenga@arm.com Stats::Scalar numBranchMispred; 15211147Smitch.hayenga@arm.com /// @} 15311147Smitch.hayenga@arm.com 15411147Smitch.hayenga@arm.com // Instruction mix histogram by OpClass 15511147Smitch.hayenga@arm.com Stats::Vector statExecutedInstType; 15611147Smitch.hayenga@arm.com 15711147Smitch.hayenga@arm.com public: 15811147Smitch.hayenga@arm.com /** Constructor */ 15911147Smitch.hayenga@arm.com SimpleExecContext(BaseSimpleCPU* _cpu, SimpleThread* _thread) 16011147Smitch.hayenga@arm.com : cpu(_cpu), thread(_thread), fetchOffset(0), stayAtPC(false), 16111147Smitch.hayenga@arm.com numInst(0), numOp(0), numLoad(0), lastIcacheStall(0), lastDcacheStall(0) 16211147Smitch.hayenga@arm.com { } 16311147Smitch.hayenga@arm.com 16411147Smitch.hayenga@arm.com /** Reads an integer register. */ 16511168Sandreas.hansson@arm.com IntReg readIntRegOperand(const StaticInst *si, int idx) override 16611147Smitch.hayenga@arm.com { 16711147Smitch.hayenga@arm.com numIntRegReads++; 16812106SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->srcRegIdx(idx); 16912106SRekai.GonzalezAlberquilla@arm.com assert(reg.isIntReg()); 17012106SRekai.GonzalezAlberquilla@arm.com return thread->readIntReg(reg.index()); 17111147Smitch.hayenga@arm.com } 17211147Smitch.hayenga@arm.com 17311147Smitch.hayenga@arm.com /** Sets an integer register to a value. */ 17411168Sandreas.hansson@arm.com void setIntRegOperand(const StaticInst *si, int idx, IntReg val) override 17511147Smitch.hayenga@arm.com { 17611147Smitch.hayenga@arm.com numIntRegWrites++; 17712106SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->destRegIdx(idx); 17812106SRekai.GonzalezAlberquilla@arm.com assert(reg.isIntReg()); 17912106SRekai.GonzalezAlberquilla@arm.com thread->setIntReg(reg.index(), val); 18011147Smitch.hayenga@arm.com } 18111147Smitch.hayenga@arm.com 18211147Smitch.hayenga@arm.com /** Reads a floating point register of single register width. */ 18311168Sandreas.hansson@arm.com FloatReg readFloatRegOperand(const StaticInst *si, int idx) override 18411147Smitch.hayenga@arm.com { 18511147Smitch.hayenga@arm.com numFpRegReads++; 18612106SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->srcRegIdx(idx); 18712106SRekai.GonzalezAlberquilla@arm.com assert(reg.isFloatReg()); 18812106SRekai.GonzalezAlberquilla@arm.com return thread->readFloatReg(reg.index()); 18911147Smitch.hayenga@arm.com } 19011147Smitch.hayenga@arm.com 19111147Smitch.hayenga@arm.com /** Reads a floating point register in its binary format, instead 19211147Smitch.hayenga@arm.com * of by value. */ 19311168Sandreas.hansson@arm.com FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx) override 19411147Smitch.hayenga@arm.com { 19511147Smitch.hayenga@arm.com numFpRegReads++; 19612106SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->srcRegIdx(idx); 19712106SRekai.GonzalezAlberquilla@arm.com assert(reg.isFloatReg()); 19812106SRekai.GonzalezAlberquilla@arm.com return thread->readFloatRegBits(reg.index()); 19911147Smitch.hayenga@arm.com } 20011147Smitch.hayenga@arm.com 20111147Smitch.hayenga@arm.com /** Sets a floating point register of single width to a value. */ 20211168Sandreas.hansson@arm.com void setFloatRegOperand(const StaticInst *si, int idx, 20311168Sandreas.hansson@arm.com FloatReg val) override 20411147Smitch.hayenga@arm.com { 20511147Smitch.hayenga@arm.com numFpRegWrites++; 20612106SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->destRegIdx(idx); 20712106SRekai.GonzalezAlberquilla@arm.com assert(reg.isFloatReg()); 20812106SRekai.GonzalezAlberquilla@arm.com thread->setFloatReg(reg.index(), val); 20911147Smitch.hayenga@arm.com } 21011147Smitch.hayenga@arm.com 21111147Smitch.hayenga@arm.com /** Sets the bits of a floating point register of single width 21211147Smitch.hayenga@arm.com * to a binary value. */ 21311147Smitch.hayenga@arm.com void setFloatRegOperandBits(const StaticInst *si, int idx, 21411168Sandreas.hansson@arm.com FloatRegBits val) override 21511147Smitch.hayenga@arm.com { 21611147Smitch.hayenga@arm.com numFpRegWrites++; 21712106SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->destRegIdx(idx); 21812106SRekai.GonzalezAlberquilla@arm.com assert(reg.isFloatReg()); 21912106SRekai.GonzalezAlberquilla@arm.com thread->setFloatRegBits(reg.index(), val); 22011147Smitch.hayenga@arm.com } 22111147Smitch.hayenga@arm.com 22211168Sandreas.hansson@arm.com CCReg readCCRegOperand(const StaticInst *si, int idx) override 22311147Smitch.hayenga@arm.com { 22411147Smitch.hayenga@arm.com numCCRegReads++; 22512106SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->srcRegIdx(idx); 22612106SRekai.GonzalezAlberquilla@arm.com assert(reg.isCCReg()); 22712106SRekai.GonzalezAlberquilla@arm.com return thread->readCCReg(reg.index()); 22811147Smitch.hayenga@arm.com } 22911147Smitch.hayenga@arm.com 23011168Sandreas.hansson@arm.com void setCCRegOperand(const StaticInst *si, int idx, CCReg val) override 23111147Smitch.hayenga@arm.com { 23211147Smitch.hayenga@arm.com numCCRegWrites++; 23312106SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->destRegIdx(idx); 23412106SRekai.GonzalezAlberquilla@arm.com assert(reg.isCCReg()); 23512106SRekai.GonzalezAlberquilla@arm.com thread->setCCReg(reg.index(), val); 23611147Smitch.hayenga@arm.com } 23711147Smitch.hayenga@arm.com 23811168Sandreas.hansson@arm.com MiscReg readMiscRegOperand(const StaticInst *si, int idx) override 23911147Smitch.hayenga@arm.com { 24011147Smitch.hayenga@arm.com numIntRegReads++; 24112106SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->srcRegIdx(idx); 24212106SRekai.GonzalezAlberquilla@arm.com assert(reg.isMiscReg()); 24312106SRekai.GonzalezAlberquilla@arm.com return thread->readMiscReg(reg.index()); 24411147Smitch.hayenga@arm.com } 24511147Smitch.hayenga@arm.com 24611168Sandreas.hansson@arm.com void setMiscRegOperand(const StaticInst *si, int idx, 24711168Sandreas.hansson@arm.com const MiscReg &val) override 24811147Smitch.hayenga@arm.com { 24911147Smitch.hayenga@arm.com numIntRegWrites++; 25012106SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->destRegIdx(idx); 25112106SRekai.GonzalezAlberquilla@arm.com assert(reg.isMiscReg()); 25212106SRekai.GonzalezAlberquilla@arm.com thread->setMiscReg(reg.index(), val); 25311147Smitch.hayenga@arm.com } 25411147Smitch.hayenga@arm.com 25511147Smitch.hayenga@arm.com /** 25611147Smitch.hayenga@arm.com * Reads a miscellaneous register, handling any architectural 25711147Smitch.hayenga@arm.com * side effects due to reading that register. 25811147Smitch.hayenga@arm.com */ 25911168Sandreas.hansson@arm.com MiscReg readMiscReg(int misc_reg) override 26011147Smitch.hayenga@arm.com { 26111147Smitch.hayenga@arm.com numIntRegReads++; 26211147Smitch.hayenga@arm.com return thread->readMiscReg(misc_reg); 26311147Smitch.hayenga@arm.com } 26411147Smitch.hayenga@arm.com 26511147Smitch.hayenga@arm.com /** 26611147Smitch.hayenga@arm.com * Sets a miscellaneous register, handling any architectural 26711147Smitch.hayenga@arm.com * side effects due to writing that register. 26811147Smitch.hayenga@arm.com */ 26911168Sandreas.hansson@arm.com void setMiscReg(int misc_reg, const MiscReg &val) override 27011147Smitch.hayenga@arm.com { 27111147Smitch.hayenga@arm.com numIntRegWrites++; 27211147Smitch.hayenga@arm.com thread->setMiscReg(misc_reg, val); 27311147Smitch.hayenga@arm.com } 27411147Smitch.hayenga@arm.com 27511168Sandreas.hansson@arm.com PCState pcState() const override 27611147Smitch.hayenga@arm.com { 27711147Smitch.hayenga@arm.com return thread->pcState(); 27811147Smitch.hayenga@arm.com } 27911147Smitch.hayenga@arm.com 28011168Sandreas.hansson@arm.com void pcState(const PCState &val) override 28111147Smitch.hayenga@arm.com { 28211147Smitch.hayenga@arm.com thread->pcState(val); 28311147Smitch.hayenga@arm.com } 28411147Smitch.hayenga@arm.com 28511147Smitch.hayenga@arm.com 28611147Smitch.hayenga@arm.com /** 28711147Smitch.hayenga@arm.com * Record the effective address of the instruction. 28811147Smitch.hayenga@arm.com * 28911147Smitch.hayenga@arm.com * @note Only valid for memory ops. 29011147Smitch.hayenga@arm.com */ 29111168Sandreas.hansson@arm.com void setEA(Addr EA) override 29211147Smitch.hayenga@arm.com { panic("BaseSimpleCPU::setEA() not implemented\n"); } 29311147Smitch.hayenga@arm.com 29411147Smitch.hayenga@arm.com /** 29511147Smitch.hayenga@arm.com * Get the effective address of the instruction. 29611147Smitch.hayenga@arm.com * 29711147Smitch.hayenga@arm.com * @note Only valid for memory ops. 29811147Smitch.hayenga@arm.com */ 29911168Sandreas.hansson@arm.com Addr getEA() const override 30011147Smitch.hayenga@arm.com { panic("BaseSimpleCPU::getEA() not implemented\n"); } 30111147Smitch.hayenga@arm.com 30211147Smitch.hayenga@arm.com Fault readMem(Addr addr, uint8_t *data, unsigned int size, 30311608Snikos.nikoleris@arm.com Request::Flags flags) override 30411147Smitch.hayenga@arm.com { 30511147Smitch.hayenga@arm.com return cpu->readMem(addr, data, size, flags); 30611147Smitch.hayenga@arm.com } 30711147Smitch.hayenga@arm.com 30811303Ssteve.reinhardt@amd.com Fault initiateMemRead(Addr addr, unsigned int size, 30911608Snikos.nikoleris@arm.com Request::Flags flags) override 31011303Ssteve.reinhardt@amd.com { 31111303Ssteve.reinhardt@amd.com return cpu->initiateMemRead(addr, size, flags); 31211303Ssteve.reinhardt@amd.com } 31311303Ssteve.reinhardt@amd.com 31411147Smitch.hayenga@arm.com Fault writeMem(uint8_t *data, unsigned int size, Addr addr, 31511608Snikos.nikoleris@arm.com Request::Flags flags, uint64_t *res) override 31611147Smitch.hayenga@arm.com { 31711147Smitch.hayenga@arm.com return cpu->writeMem(data, size, addr, flags, res); 31811147Smitch.hayenga@arm.com } 31911147Smitch.hayenga@arm.com 32011147Smitch.hayenga@arm.com /** 32111147Smitch.hayenga@arm.com * Sets the number of consecutive store conditional failures. 32211147Smitch.hayenga@arm.com */ 32311168Sandreas.hansson@arm.com void setStCondFailures(unsigned int sc_failures) override 32411147Smitch.hayenga@arm.com { 32511147Smitch.hayenga@arm.com thread->setStCondFailures(sc_failures); 32611147Smitch.hayenga@arm.com } 32711147Smitch.hayenga@arm.com 32811147Smitch.hayenga@arm.com /** 32911147Smitch.hayenga@arm.com * Returns the number of consecutive store conditional failures. 33011147Smitch.hayenga@arm.com */ 33111168Sandreas.hansson@arm.com unsigned int readStCondFailures() const override 33211147Smitch.hayenga@arm.com { 33311147Smitch.hayenga@arm.com return thread->readStCondFailures(); 33411147Smitch.hayenga@arm.com } 33511147Smitch.hayenga@arm.com 33611147Smitch.hayenga@arm.com /** 33711147Smitch.hayenga@arm.com * Executes a syscall specified by the callnum. 33811147Smitch.hayenga@arm.com */ 33911877Sbrandon.potter@amd.com void syscall(int64_t callnum, Fault *fault) override 34011147Smitch.hayenga@arm.com { 34111147Smitch.hayenga@arm.com if (FullSystem) 34211147Smitch.hayenga@arm.com panic("Syscall emulation isn't available in FS mode."); 34311147Smitch.hayenga@arm.com 34411877Sbrandon.potter@amd.com thread->syscall(callnum, fault); 34511147Smitch.hayenga@arm.com } 34611147Smitch.hayenga@arm.com 34711147Smitch.hayenga@arm.com /** Returns a pointer to the ThreadContext. */ 34811168Sandreas.hansson@arm.com ThreadContext *tcBase() override 34911147Smitch.hayenga@arm.com { 35011147Smitch.hayenga@arm.com return thread->getTC(); 35111147Smitch.hayenga@arm.com } 35211147Smitch.hayenga@arm.com 35311147Smitch.hayenga@arm.com /** 35411147Smitch.hayenga@arm.com * Somewhat Alpha-specific function that handles returning from an 35511147Smitch.hayenga@arm.com * error or interrupt. 35611147Smitch.hayenga@arm.com */ 35711168Sandreas.hansson@arm.com Fault hwrei() override 35811147Smitch.hayenga@arm.com { 35911147Smitch.hayenga@arm.com return thread->hwrei(); 36011147Smitch.hayenga@arm.com } 36111147Smitch.hayenga@arm.com 36211147Smitch.hayenga@arm.com /** 36311147Smitch.hayenga@arm.com * Check for special simulator handling of specific PAL calls. If 36411147Smitch.hayenga@arm.com * return value is false, actual PAL call will be suppressed. 36511147Smitch.hayenga@arm.com */ 36611168Sandreas.hansson@arm.com bool simPalCheck(int palFunc) override 36711147Smitch.hayenga@arm.com { 36811147Smitch.hayenga@arm.com return thread->simPalCheck(palFunc); 36911147Smitch.hayenga@arm.com } 37011147Smitch.hayenga@arm.com 37111168Sandreas.hansson@arm.com bool readPredicate() override 37211147Smitch.hayenga@arm.com { 37311147Smitch.hayenga@arm.com return thread->readPredicate(); 37411147Smitch.hayenga@arm.com } 37511147Smitch.hayenga@arm.com 37611168Sandreas.hansson@arm.com void setPredicate(bool val) override 37711147Smitch.hayenga@arm.com { 37811147Smitch.hayenga@arm.com thread->setPredicate(val); 37911147Smitch.hayenga@arm.com 38011147Smitch.hayenga@arm.com if (cpu->traceData) { 38111147Smitch.hayenga@arm.com cpu->traceData->setPredicate(val); 38211147Smitch.hayenga@arm.com } 38311147Smitch.hayenga@arm.com } 38411147Smitch.hayenga@arm.com 38511147Smitch.hayenga@arm.com /** 38611147Smitch.hayenga@arm.com * Invalidate a page in the DTLB <i>and</i> ITLB. 38711147Smitch.hayenga@arm.com */ 38811168Sandreas.hansson@arm.com void demapPage(Addr vaddr, uint64_t asn) override 38911147Smitch.hayenga@arm.com { 39011147Smitch.hayenga@arm.com thread->demapPage(vaddr, asn); 39111147Smitch.hayenga@arm.com } 39211147Smitch.hayenga@arm.com 39311168Sandreas.hansson@arm.com void armMonitor(Addr address) override 39411147Smitch.hayenga@arm.com { 39511148Smitch.hayenga@arm.com cpu->armMonitor(thread->threadId(), address); 39611147Smitch.hayenga@arm.com } 39711147Smitch.hayenga@arm.com 39811168Sandreas.hansson@arm.com bool mwait(PacketPtr pkt) override 39911147Smitch.hayenga@arm.com { 40011148Smitch.hayenga@arm.com return cpu->mwait(thread->threadId(), pkt); 40111147Smitch.hayenga@arm.com } 40211147Smitch.hayenga@arm.com 40311168Sandreas.hansson@arm.com void mwaitAtomic(ThreadContext *tc) override 40411147Smitch.hayenga@arm.com { 40511148Smitch.hayenga@arm.com cpu->mwaitAtomic(thread->threadId(), tc, thread->dtb); 40611147Smitch.hayenga@arm.com } 40711147Smitch.hayenga@arm.com 40811168Sandreas.hansson@arm.com AddressMonitor *getAddrMonitor() override 40911147Smitch.hayenga@arm.com { 41011148Smitch.hayenga@arm.com return cpu->getCpuAddrMonitor(thread->threadId()); 41111147Smitch.hayenga@arm.com } 41211147Smitch.hayenga@arm.com 41311147Smitch.hayenga@arm.com#if THE_ISA == MIPS_ISA 41412106SRekai.GonzalezAlberquilla@arm.com MiscReg readRegOtherThread(const RegId& reg, 41512106SRekai.GonzalezAlberquilla@arm.com ThreadID tid = InvalidThreadID) 41611168Sandreas.hansson@arm.com override 41711147Smitch.hayenga@arm.com { 41811147Smitch.hayenga@arm.com panic("Simple CPU models do not support multithreaded " 41911147Smitch.hayenga@arm.com "register access."); 42011147Smitch.hayenga@arm.com } 42111147Smitch.hayenga@arm.com 42212106SRekai.GonzalezAlberquilla@arm.com void setRegOtherThread(const RegId& reg, MiscReg val, 42311168Sandreas.hansson@arm.com ThreadID tid = InvalidThreadID) override 42411147Smitch.hayenga@arm.com { 42511147Smitch.hayenga@arm.com panic("Simple CPU models do not support multithreaded " 42611147Smitch.hayenga@arm.com "register access."); 42711147Smitch.hayenga@arm.com } 42811147Smitch.hayenga@arm.com 42911147Smitch.hayenga@arm.com#endif 43011147Smitch.hayenga@arm.com 43111147Smitch.hayenga@arm.com}; 43211147Smitch.hayenga@arm.com 43311147Smitch.hayenga@arm.com#endif // __CPU_EXEC_CONTEXT_HH__ 434