exec_context.hh revision 11147
111147Smitch.hayenga@arm.com/* 211147Smitch.hayenga@arm.com * Copyright (c) 2014-2015 ARM Limited 311147Smitch.hayenga@arm.com * All rights reserved 411147Smitch.hayenga@arm.com * 511147Smitch.hayenga@arm.com * The license below extends only to copyright in the software and shall 611147Smitch.hayenga@arm.com * not be construed as granting a license to any other intellectual 711147Smitch.hayenga@arm.com * property including but not limited to intellectual property relating 811147Smitch.hayenga@arm.com * to a hardware implementation of the functionality of the software 911147Smitch.hayenga@arm.com * licensed hereunder. You may use the software subject to the license 1011147Smitch.hayenga@arm.com * terms below provided that you ensure that this notice is replicated 1111147Smitch.hayenga@arm.com * unmodified and in its entirety in all distributions of the software, 1211147Smitch.hayenga@arm.com * modified or unmodified, in source code or in binary form. 1311147Smitch.hayenga@arm.com * 1411147Smitch.hayenga@arm.com * Copyright (c) 2002-2005 The Regents of The University of Michigan 1511147Smitch.hayenga@arm.com * All rights reserved. 1611147Smitch.hayenga@arm.com * 1711147Smitch.hayenga@arm.com * Redistribution and use in source and binary forms, with or without 1811147Smitch.hayenga@arm.com * modification, are permitted provided that the following conditions are 1911147Smitch.hayenga@arm.com * met: redistributions of source code must retain the above copyright 2011147Smitch.hayenga@arm.com * notice, this list of conditions and the following disclaimer; 2111147Smitch.hayenga@arm.com * redistributions in binary form must reproduce the above copyright 2211147Smitch.hayenga@arm.com * notice, this list of conditions and the following disclaimer in the 2311147Smitch.hayenga@arm.com * documentation and/or other materials provided with the distribution; 2411147Smitch.hayenga@arm.com * neither the name of the copyright holders nor the names of its 2511147Smitch.hayenga@arm.com * contributors may be used to endorse or promote products derived from 2611147Smitch.hayenga@arm.com * this software without specific prior written permission. 2711147Smitch.hayenga@arm.com * 2811147Smitch.hayenga@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2911147Smitch.hayenga@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 3011147Smitch.hayenga@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 3111147Smitch.hayenga@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 3211147Smitch.hayenga@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3311147Smitch.hayenga@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3411147Smitch.hayenga@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3511147Smitch.hayenga@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3611147Smitch.hayenga@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3711147Smitch.hayenga@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3811147Smitch.hayenga@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3911147Smitch.hayenga@arm.com * 4011147Smitch.hayenga@arm.com * Authors: Kevin Lim 4111147Smitch.hayenga@arm.com * Andreas Sandberg 4211147Smitch.hayenga@arm.com * Mitch Hayenga 4311147Smitch.hayenga@arm.com */ 4411147Smitch.hayenga@arm.com 4511147Smitch.hayenga@arm.com#ifndef __CPU_SIMPLE_EXEC_CONTEXT_HH__ 4611147Smitch.hayenga@arm.com#define __CPU_SIMPLE_EXEC_CONTEXT_HH__ 4711147Smitch.hayenga@arm.com 4811147Smitch.hayenga@arm.com#include "arch/registers.hh" 4911147Smitch.hayenga@arm.com#include "base/types.hh" 5011147Smitch.hayenga@arm.com#include "config/the_isa.hh" 5111147Smitch.hayenga@arm.com#include "cpu/base.hh" 5211147Smitch.hayenga@arm.com#include "cpu/exec_context.hh" 5311147Smitch.hayenga@arm.com#include "cpu/simple/base.hh" 5411147Smitch.hayenga@arm.com#include "cpu/static_inst_fwd.hh" 5511147Smitch.hayenga@arm.com#include "cpu/translation.hh" 5611147Smitch.hayenga@arm.com 5711147Smitch.hayenga@arm.comclass BaseSimpleCPU; 5811147Smitch.hayenga@arm.com 5911147Smitch.hayenga@arm.comclass SimpleExecContext : public ExecContext { 6011147Smitch.hayenga@arm.com protected: 6111147Smitch.hayenga@arm.com typedef TheISA::MiscReg MiscReg; 6211147Smitch.hayenga@arm.com typedef TheISA::FloatReg FloatReg; 6311147Smitch.hayenga@arm.com typedef TheISA::FloatRegBits FloatRegBits; 6411147Smitch.hayenga@arm.com typedef TheISA::CCReg CCReg; 6511147Smitch.hayenga@arm.com 6611147Smitch.hayenga@arm.com public: 6711147Smitch.hayenga@arm.com BaseSimpleCPU *cpu; 6811147Smitch.hayenga@arm.com SimpleThread* thread; 6911147Smitch.hayenga@arm.com 7011147Smitch.hayenga@arm.com // This is the offset from the current pc that fetch should be performed 7111147Smitch.hayenga@arm.com Addr fetchOffset; 7211147Smitch.hayenga@arm.com // This flag says to stay at the current pc. This is useful for 7311147Smitch.hayenga@arm.com // instructions which go beyond MachInst boundaries. 7411147Smitch.hayenga@arm.com bool stayAtPC; 7511147Smitch.hayenga@arm.com 7611147Smitch.hayenga@arm.com // Branch prediction 7711147Smitch.hayenga@arm.com TheISA::PCState predPC; 7811147Smitch.hayenga@arm.com 7911147Smitch.hayenga@arm.com /** PER-THREAD STATS */ 8011147Smitch.hayenga@arm.com 8111147Smitch.hayenga@arm.com // Number of simulated instructions 8211147Smitch.hayenga@arm.com Counter numInst; 8311147Smitch.hayenga@arm.com Stats::Scalar numInsts; 8411147Smitch.hayenga@arm.com Counter numOp; 8511147Smitch.hayenga@arm.com Stats::Scalar numOps; 8611147Smitch.hayenga@arm.com 8711147Smitch.hayenga@arm.com // Number of integer alu accesses 8811147Smitch.hayenga@arm.com Stats::Scalar numIntAluAccesses; 8911147Smitch.hayenga@arm.com 9011147Smitch.hayenga@arm.com // Number of float alu accesses 9111147Smitch.hayenga@arm.com Stats::Scalar numFpAluAccesses; 9211147Smitch.hayenga@arm.com 9311147Smitch.hayenga@arm.com // Number of function calls/returns 9411147Smitch.hayenga@arm.com Stats::Scalar numCallsReturns; 9511147Smitch.hayenga@arm.com 9611147Smitch.hayenga@arm.com // Conditional control instructions; 9711147Smitch.hayenga@arm.com Stats::Scalar numCondCtrlInsts; 9811147Smitch.hayenga@arm.com 9911147Smitch.hayenga@arm.com // Number of int instructions 10011147Smitch.hayenga@arm.com Stats::Scalar numIntInsts; 10111147Smitch.hayenga@arm.com 10211147Smitch.hayenga@arm.com // Number of float instructions 10311147Smitch.hayenga@arm.com Stats::Scalar numFpInsts; 10411147Smitch.hayenga@arm.com 10511147Smitch.hayenga@arm.com // Number of integer register file accesses 10611147Smitch.hayenga@arm.com Stats::Scalar numIntRegReads; 10711147Smitch.hayenga@arm.com Stats::Scalar numIntRegWrites; 10811147Smitch.hayenga@arm.com 10911147Smitch.hayenga@arm.com // Number of float register file accesses 11011147Smitch.hayenga@arm.com Stats::Scalar numFpRegReads; 11111147Smitch.hayenga@arm.com Stats::Scalar numFpRegWrites; 11211147Smitch.hayenga@arm.com 11311147Smitch.hayenga@arm.com // Number of condition code register file accesses 11411147Smitch.hayenga@arm.com Stats::Scalar numCCRegReads; 11511147Smitch.hayenga@arm.com Stats::Scalar numCCRegWrites; 11611147Smitch.hayenga@arm.com 11711147Smitch.hayenga@arm.com // Number of simulated memory references 11811147Smitch.hayenga@arm.com Stats::Scalar numMemRefs; 11911147Smitch.hayenga@arm.com Stats::Scalar numLoadInsts; 12011147Smitch.hayenga@arm.com Stats::Scalar numStoreInsts; 12111147Smitch.hayenga@arm.com 12211147Smitch.hayenga@arm.com // Number of idle cycles 12311147Smitch.hayenga@arm.com Stats::Formula numIdleCycles; 12411147Smitch.hayenga@arm.com 12511147Smitch.hayenga@arm.com // Number of busy cycles 12611147Smitch.hayenga@arm.com Stats::Formula numBusyCycles; 12711147Smitch.hayenga@arm.com 12811147Smitch.hayenga@arm.com // Number of simulated loads 12911147Smitch.hayenga@arm.com Counter numLoad; 13011147Smitch.hayenga@arm.com 13111147Smitch.hayenga@arm.com // Number of idle cycles 13211147Smitch.hayenga@arm.com Stats::Average notIdleFraction; 13311147Smitch.hayenga@arm.com Stats::Formula idleFraction; 13411147Smitch.hayenga@arm.com 13511147Smitch.hayenga@arm.com // Number of cycles stalled for I-cache responses 13611147Smitch.hayenga@arm.com Stats::Scalar icacheStallCycles; 13711147Smitch.hayenga@arm.com Counter lastIcacheStall; 13811147Smitch.hayenga@arm.com 13911147Smitch.hayenga@arm.com // Number of cycles stalled for D-cache responses 14011147Smitch.hayenga@arm.com Stats::Scalar dcacheStallCycles; 14111147Smitch.hayenga@arm.com Counter lastDcacheStall; 14211147Smitch.hayenga@arm.com 14311147Smitch.hayenga@arm.com /// @{ 14411147Smitch.hayenga@arm.com /// Total number of branches fetched 14511147Smitch.hayenga@arm.com Stats::Scalar numBranches; 14611147Smitch.hayenga@arm.com /// Number of branches predicted as taken 14711147Smitch.hayenga@arm.com Stats::Scalar numPredictedBranches; 14811147Smitch.hayenga@arm.com /// Number of misprediced branches 14911147Smitch.hayenga@arm.com Stats::Scalar numBranchMispred; 15011147Smitch.hayenga@arm.com /// @} 15111147Smitch.hayenga@arm.com 15211147Smitch.hayenga@arm.com // Instruction mix histogram by OpClass 15311147Smitch.hayenga@arm.com Stats::Vector statExecutedInstType; 15411147Smitch.hayenga@arm.com 15511147Smitch.hayenga@arm.com public: 15611147Smitch.hayenga@arm.com /** Constructor */ 15711147Smitch.hayenga@arm.com SimpleExecContext(BaseSimpleCPU* _cpu, SimpleThread* _thread) 15811147Smitch.hayenga@arm.com : cpu(_cpu), thread(_thread), fetchOffset(0), stayAtPC(false), 15911147Smitch.hayenga@arm.com numInst(0), numOp(0), numLoad(0), lastIcacheStall(0), lastDcacheStall(0) 16011147Smitch.hayenga@arm.com { } 16111147Smitch.hayenga@arm.com 16211147Smitch.hayenga@arm.com /** Reads an integer register. */ 16311147Smitch.hayenga@arm.com IntReg readIntRegOperand(const StaticInst *si, int idx) M5_ATTR_OVERRIDE 16411147Smitch.hayenga@arm.com { 16511147Smitch.hayenga@arm.com numIntRegReads++; 16611147Smitch.hayenga@arm.com return thread->readIntReg(si->srcRegIdx(idx)); 16711147Smitch.hayenga@arm.com } 16811147Smitch.hayenga@arm.com 16911147Smitch.hayenga@arm.com /** Sets an integer register to a value. */ 17011147Smitch.hayenga@arm.com void setIntRegOperand(const StaticInst *si, int idx, IntReg val) 17111147Smitch.hayenga@arm.com M5_ATTR_OVERRIDE 17211147Smitch.hayenga@arm.com { 17311147Smitch.hayenga@arm.com numIntRegWrites++; 17411147Smitch.hayenga@arm.com thread->setIntReg(si->destRegIdx(idx), val); 17511147Smitch.hayenga@arm.com } 17611147Smitch.hayenga@arm.com 17711147Smitch.hayenga@arm.com /** Reads a floating point register of single register width. */ 17811147Smitch.hayenga@arm.com FloatReg readFloatRegOperand(const StaticInst *si, int idx) 17911147Smitch.hayenga@arm.com M5_ATTR_OVERRIDE 18011147Smitch.hayenga@arm.com { 18111147Smitch.hayenga@arm.com numFpRegReads++; 18211147Smitch.hayenga@arm.com int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Reg_Base; 18311147Smitch.hayenga@arm.com return thread->readFloatReg(reg_idx); 18411147Smitch.hayenga@arm.com } 18511147Smitch.hayenga@arm.com 18611147Smitch.hayenga@arm.com /** Reads a floating point register in its binary format, instead 18711147Smitch.hayenga@arm.com * of by value. */ 18811147Smitch.hayenga@arm.com FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx) 18911147Smitch.hayenga@arm.com M5_ATTR_OVERRIDE 19011147Smitch.hayenga@arm.com { 19111147Smitch.hayenga@arm.com numFpRegReads++; 19211147Smitch.hayenga@arm.com int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Reg_Base; 19311147Smitch.hayenga@arm.com return thread->readFloatRegBits(reg_idx); 19411147Smitch.hayenga@arm.com } 19511147Smitch.hayenga@arm.com 19611147Smitch.hayenga@arm.com /** Sets a floating point register of single width to a value. */ 19711147Smitch.hayenga@arm.com void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val) 19811147Smitch.hayenga@arm.com M5_ATTR_OVERRIDE 19911147Smitch.hayenga@arm.com { 20011147Smitch.hayenga@arm.com numFpRegWrites++; 20111147Smitch.hayenga@arm.com int reg_idx = si->destRegIdx(idx) - TheISA::FP_Reg_Base; 20211147Smitch.hayenga@arm.com thread->setFloatReg(reg_idx, val); 20311147Smitch.hayenga@arm.com } 20411147Smitch.hayenga@arm.com 20511147Smitch.hayenga@arm.com /** Sets the bits of a floating point register of single width 20611147Smitch.hayenga@arm.com * to a binary value. */ 20711147Smitch.hayenga@arm.com void setFloatRegOperandBits(const StaticInst *si, int idx, 20811147Smitch.hayenga@arm.com FloatRegBits val) M5_ATTR_OVERRIDE 20911147Smitch.hayenga@arm.com { 21011147Smitch.hayenga@arm.com numFpRegWrites++; 21111147Smitch.hayenga@arm.com int reg_idx = si->destRegIdx(idx) - TheISA::FP_Reg_Base; 21211147Smitch.hayenga@arm.com thread->setFloatRegBits(reg_idx, val); 21311147Smitch.hayenga@arm.com } 21411147Smitch.hayenga@arm.com 21511147Smitch.hayenga@arm.com CCReg readCCRegOperand(const StaticInst *si, int idx) M5_ATTR_OVERRIDE 21611147Smitch.hayenga@arm.com { 21711147Smitch.hayenga@arm.com numCCRegReads++; 21811147Smitch.hayenga@arm.com int reg_idx = si->srcRegIdx(idx) - TheISA::CC_Reg_Base; 21911147Smitch.hayenga@arm.com return thread->readCCReg(reg_idx); 22011147Smitch.hayenga@arm.com } 22111147Smitch.hayenga@arm.com 22211147Smitch.hayenga@arm.com void setCCRegOperand(const StaticInst *si, int idx, CCReg val) 22311147Smitch.hayenga@arm.com M5_ATTR_OVERRIDE 22411147Smitch.hayenga@arm.com { 22511147Smitch.hayenga@arm.com numCCRegWrites++; 22611147Smitch.hayenga@arm.com int reg_idx = si->destRegIdx(idx) - TheISA::CC_Reg_Base; 22711147Smitch.hayenga@arm.com thread->setCCReg(reg_idx, val); 22811147Smitch.hayenga@arm.com } 22911147Smitch.hayenga@arm.com 23011147Smitch.hayenga@arm.com MiscReg readMiscRegOperand(const StaticInst *si, int idx) M5_ATTR_OVERRIDE 23111147Smitch.hayenga@arm.com { 23211147Smitch.hayenga@arm.com numIntRegReads++; 23311147Smitch.hayenga@arm.com int reg_idx = si->srcRegIdx(idx) - TheISA::Misc_Reg_Base; 23411147Smitch.hayenga@arm.com return thread->readMiscReg(reg_idx); 23511147Smitch.hayenga@arm.com } 23611147Smitch.hayenga@arm.com 23711147Smitch.hayenga@arm.com void setMiscRegOperand(const StaticInst *si, int idx, const MiscReg &val) 23811147Smitch.hayenga@arm.com M5_ATTR_OVERRIDE 23911147Smitch.hayenga@arm.com { 24011147Smitch.hayenga@arm.com numIntRegWrites++; 24111147Smitch.hayenga@arm.com int reg_idx = si->destRegIdx(idx) - TheISA::Misc_Reg_Base; 24211147Smitch.hayenga@arm.com thread->setMiscReg(reg_idx, val); 24311147Smitch.hayenga@arm.com } 24411147Smitch.hayenga@arm.com 24511147Smitch.hayenga@arm.com /** 24611147Smitch.hayenga@arm.com * Reads a miscellaneous register, handling any architectural 24711147Smitch.hayenga@arm.com * side effects due to reading that register. 24811147Smitch.hayenga@arm.com */ 24911147Smitch.hayenga@arm.com MiscReg readMiscReg(int misc_reg) M5_ATTR_OVERRIDE 25011147Smitch.hayenga@arm.com { 25111147Smitch.hayenga@arm.com numIntRegReads++; 25211147Smitch.hayenga@arm.com return thread->readMiscReg(misc_reg); 25311147Smitch.hayenga@arm.com } 25411147Smitch.hayenga@arm.com 25511147Smitch.hayenga@arm.com /** 25611147Smitch.hayenga@arm.com * Sets a miscellaneous register, handling any architectural 25711147Smitch.hayenga@arm.com * side effects due to writing that register. 25811147Smitch.hayenga@arm.com */ 25911147Smitch.hayenga@arm.com void setMiscReg(int misc_reg, const MiscReg &val) M5_ATTR_OVERRIDE 26011147Smitch.hayenga@arm.com { 26111147Smitch.hayenga@arm.com numIntRegWrites++; 26211147Smitch.hayenga@arm.com thread->setMiscReg(misc_reg, val); 26311147Smitch.hayenga@arm.com } 26411147Smitch.hayenga@arm.com 26511147Smitch.hayenga@arm.com PCState pcState() const M5_ATTR_OVERRIDE 26611147Smitch.hayenga@arm.com { 26711147Smitch.hayenga@arm.com return thread->pcState(); 26811147Smitch.hayenga@arm.com } 26911147Smitch.hayenga@arm.com 27011147Smitch.hayenga@arm.com void pcState(const PCState &val) M5_ATTR_OVERRIDE 27111147Smitch.hayenga@arm.com { 27211147Smitch.hayenga@arm.com thread->pcState(val); 27311147Smitch.hayenga@arm.com } 27411147Smitch.hayenga@arm.com 27511147Smitch.hayenga@arm.com 27611147Smitch.hayenga@arm.com /** 27711147Smitch.hayenga@arm.com * Record the effective address of the instruction. 27811147Smitch.hayenga@arm.com * 27911147Smitch.hayenga@arm.com * @note Only valid for memory ops. 28011147Smitch.hayenga@arm.com */ 28111147Smitch.hayenga@arm.com void setEA(Addr EA) M5_ATTR_OVERRIDE 28211147Smitch.hayenga@arm.com { panic("BaseSimpleCPU::setEA() not implemented\n"); } 28311147Smitch.hayenga@arm.com 28411147Smitch.hayenga@arm.com /** 28511147Smitch.hayenga@arm.com * Get the effective address of the instruction. 28611147Smitch.hayenga@arm.com * 28711147Smitch.hayenga@arm.com * @note Only valid for memory ops. 28811147Smitch.hayenga@arm.com */ 28911147Smitch.hayenga@arm.com Addr getEA() const M5_ATTR_OVERRIDE 29011147Smitch.hayenga@arm.com { panic("BaseSimpleCPU::getEA() not implemented\n"); } 29111147Smitch.hayenga@arm.com 29211147Smitch.hayenga@arm.com Fault readMem(Addr addr, uint8_t *data, unsigned int size, 29311147Smitch.hayenga@arm.com unsigned int flags) M5_ATTR_OVERRIDE 29411147Smitch.hayenga@arm.com { 29511147Smitch.hayenga@arm.com return cpu->readMem(addr, data, size, flags); 29611147Smitch.hayenga@arm.com } 29711147Smitch.hayenga@arm.com 29811147Smitch.hayenga@arm.com Fault writeMem(uint8_t *data, unsigned int size, Addr addr, 29911147Smitch.hayenga@arm.com unsigned int flags, uint64_t *res) M5_ATTR_OVERRIDE 30011147Smitch.hayenga@arm.com { 30111147Smitch.hayenga@arm.com return cpu->writeMem(data, size, addr, flags, res); 30211147Smitch.hayenga@arm.com } 30311147Smitch.hayenga@arm.com 30411147Smitch.hayenga@arm.com /** 30511147Smitch.hayenga@arm.com * Sets the number of consecutive store conditional failures. 30611147Smitch.hayenga@arm.com */ 30711147Smitch.hayenga@arm.com void setStCondFailures(unsigned int sc_failures) M5_ATTR_OVERRIDE 30811147Smitch.hayenga@arm.com { 30911147Smitch.hayenga@arm.com thread->setStCondFailures(sc_failures); 31011147Smitch.hayenga@arm.com } 31111147Smitch.hayenga@arm.com 31211147Smitch.hayenga@arm.com /** 31311147Smitch.hayenga@arm.com * Returns the number of consecutive store conditional failures. 31411147Smitch.hayenga@arm.com */ 31511147Smitch.hayenga@arm.com unsigned int readStCondFailures() const M5_ATTR_OVERRIDE 31611147Smitch.hayenga@arm.com { 31711147Smitch.hayenga@arm.com return thread->readStCondFailures(); 31811147Smitch.hayenga@arm.com } 31911147Smitch.hayenga@arm.com 32011147Smitch.hayenga@arm.com /** 32111147Smitch.hayenga@arm.com * Executes a syscall specified by the callnum. 32211147Smitch.hayenga@arm.com */ 32311147Smitch.hayenga@arm.com void syscall(int64_t callnum) M5_ATTR_OVERRIDE 32411147Smitch.hayenga@arm.com { 32511147Smitch.hayenga@arm.com if (FullSystem) 32611147Smitch.hayenga@arm.com panic("Syscall emulation isn't available in FS mode."); 32711147Smitch.hayenga@arm.com 32811147Smitch.hayenga@arm.com thread->syscall(callnum); 32911147Smitch.hayenga@arm.com } 33011147Smitch.hayenga@arm.com 33111147Smitch.hayenga@arm.com /** Returns a pointer to the ThreadContext. */ 33211147Smitch.hayenga@arm.com ThreadContext *tcBase() M5_ATTR_OVERRIDE 33311147Smitch.hayenga@arm.com { 33411147Smitch.hayenga@arm.com return thread->getTC(); 33511147Smitch.hayenga@arm.com } 33611147Smitch.hayenga@arm.com 33711147Smitch.hayenga@arm.com /** 33811147Smitch.hayenga@arm.com * Somewhat Alpha-specific function that handles returning from an 33911147Smitch.hayenga@arm.com * error or interrupt. 34011147Smitch.hayenga@arm.com */ 34111147Smitch.hayenga@arm.com Fault hwrei() M5_ATTR_OVERRIDE 34211147Smitch.hayenga@arm.com { 34311147Smitch.hayenga@arm.com return thread->hwrei(); 34411147Smitch.hayenga@arm.com } 34511147Smitch.hayenga@arm.com 34611147Smitch.hayenga@arm.com /** 34711147Smitch.hayenga@arm.com * Check for special simulator handling of specific PAL calls. If 34811147Smitch.hayenga@arm.com * return value is false, actual PAL call will be suppressed. 34911147Smitch.hayenga@arm.com */ 35011147Smitch.hayenga@arm.com bool simPalCheck(int palFunc) M5_ATTR_OVERRIDE 35111147Smitch.hayenga@arm.com { 35211147Smitch.hayenga@arm.com return thread->simPalCheck(palFunc); 35311147Smitch.hayenga@arm.com } 35411147Smitch.hayenga@arm.com 35511147Smitch.hayenga@arm.com bool readPredicate() M5_ATTR_OVERRIDE 35611147Smitch.hayenga@arm.com { 35711147Smitch.hayenga@arm.com return thread->readPredicate(); 35811147Smitch.hayenga@arm.com } 35911147Smitch.hayenga@arm.com 36011147Smitch.hayenga@arm.com void setPredicate(bool val) M5_ATTR_OVERRIDE 36111147Smitch.hayenga@arm.com { 36211147Smitch.hayenga@arm.com thread->setPredicate(val); 36311147Smitch.hayenga@arm.com 36411147Smitch.hayenga@arm.com if (cpu->traceData) { 36511147Smitch.hayenga@arm.com cpu->traceData->setPredicate(val); 36611147Smitch.hayenga@arm.com } 36711147Smitch.hayenga@arm.com } 36811147Smitch.hayenga@arm.com 36911147Smitch.hayenga@arm.com /** 37011147Smitch.hayenga@arm.com * Invalidate a page in the DTLB <i>and</i> ITLB. 37111147Smitch.hayenga@arm.com */ 37211147Smitch.hayenga@arm.com void demapPage(Addr vaddr, uint64_t asn) M5_ATTR_OVERRIDE 37311147Smitch.hayenga@arm.com { 37411147Smitch.hayenga@arm.com thread->demapPage(vaddr, asn); 37511147Smitch.hayenga@arm.com } 37611147Smitch.hayenga@arm.com 37711147Smitch.hayenga@arm.com void armMonitor(Addr address) M5_ATTR_OVERRIDE 37811147Smitch.hayenga@arm.com { 37911147Smitch.hayenga@arm.com cpu->armMonitor(address); 38011147Smitch.hayenga@arm.com } 38111147Smitch.hayenga@arm.com 38211147Smitch.hayenga@arm.com bool mwait(PacketPtr pkt) M5_ATTR_OVERRIDE 38311147Smitch.hayenga@arm.com { 38411147Smitch.hayenga@arm.com return cpu->mwait(pkt); 38511147Smitch.hayenga@arm.com } 38611147Smitch.hayenga@arm.com 38711147Smitch.hayenga@arm.com void mwaitAtomic(ThreadContext *tc) M5_ATTR_OVERRIDE 38811147Smitch.hayenga@arm.com { 38911147Smitch.hayenga@arm.com cpu->mwaitAtomic(tc, thread->dtb); 39011147Smitch.hayenga@arm.com } 39111147Smitch.hayenga@arm.com 39211147Smitch.hayenga@arm.com AddressMonitor *getAddrMonitor() M5_ATTR_OVERRIDE 39311147Smitch.hayenga@arm.com { 39411147Smitch.hayenga@arm.com return cpu->getCpuAddrMonitor(); 39511147Smitch.hayenga@arm.com } 39611147Smitch.hayenga@arm.com 39711147Smitch.hayenga@arm.com#if THE_ISA == MIPS_ISA 39811147Smitch.hayenga@arm.com MiscReg readRegOtherThread(int regIdx, ThreadID tid = InvalidThreadID) 39911147Smitch.hayenga@arm.com M5_ATTR_OVERRIDE 40011147Smitch.hayenga@arm.com { 40111147Smitch.hayenga@arm.com panic("Simple CPU models do not support multithreaded " 40211147Smitch.hayenga@arm.com "register access."); 40311147Smitch.hayenga@arm.com } 40411147Smitch.hayenga@arm.com 40511147Smitch.hayenga@arm.com void setRegOtherThread(int regIdx, MiscReg val, 40611147Smitch.hayenga@arm.com ThreadID tid = InvalidThreadID) M5_ATTR_OVERRIDE 40711147Smitch.hayenga@arm.com { 40811147Smitch.hayenga@arm.com panic("Simple CPU models do not support multithreaded " 40911147Smitch.hayenga@arm.com "register access."); 41011147Smitch.hayenga@arm.com } 41111147Smitch.hayenga@arm.com 41211147Smitch.hayenga@arm.com#endif 41311147Smitch.hayenga@arm.com 41411147Smitch.hayenga@arm.com}; 41511147Smitch.hayenga@arm.com 41611147Smitch.hayenga@arm.com#endif // __CPU_EXEC_CONTEXT_HH__ 417