base.hh revision 9918:2c7219e2d999
1807SN/A/* 21762SN/A * Copyright (c) 2011-2012 ARM Limited 3807SN/A * All rights reserved 4807SN/A * 5807SN/A * The license below extends only to copyright in the software and shall 6807SN/A * not be construed as granting a license to any other intellectual 7807SN/A * property including but not limited to intellectual property relating 8807SN/A * to a hardware implementation of the functionality of the software 9807SN/A * licensed hereunder. You may use the software subject to the license 10807SN/A * terms below provided that you ensure that this notice is replicated 11807SN/A * unmodified and in its entirety in all distributions of the software, 12807SN/A * modified or unmodified, in source code or in binary form. 13807SN/A * 14807SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 15807SN/A * All rights reserved. 16807SN/A * 17807SN/A * Redistribution and use in source and binary forms, with or without 18807SN/A * modification, are permitted provided that the following conditions are 19807SN/A * met: redistributions of source code must retain the above copyright 20807SN/A * notice, this list of conditions and the following disclaimer; 21807SN/A * redistributions in binary form must reproduce the above copyright 22807SN/A * notice, this list of conditions and the following disclaimer in the 23807SN/A * documentation and/or other materials provided with the distribution; 24807SN/A * neither the name of the copyright holders nor the names of its 25807SN/A * contributors may be used to endorse or promote products derived from 26807SN/A * this software without specific prior written permission. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292760Sbinkertn@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30807SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31807SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32807SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33807SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34807SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35807SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36807SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 371634SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 381634SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39807SN/A * 402846Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 412846Ssaidi@eecs.umich.edu * Dave Greene 422846Ssaidi@eecs.umich.edu * Nathan Binkert 43807SN/A */ 442080SN/A 45807SN/A#ifndef __CPU_SIMPLE_BASE_HH__ 46849SN/A#define __CPU_SIMPLE_BASE_HH__ 47807SN/A 48807SN/A#include "base/statistics.hh" 49932SN/A#include "config/the_isa.hh" 502384SN/A#include "cpu/base.hh" 51807SN/A#include "cpu/checker/cpu.hh" 52807SN/A#include "cpu/pc_event.hh" 53807SN/A#include "cpu/simple_thread.hh" 54807SN/A#include "cpu/static_inst.hh" 55807SN/A#include "mem/packet.hh" 56807SN/A#include "mem/port.hh" 571634SN/A#include "mem/request.hh" 58932SN/A#include "sim/eventq.hh" 59932SN/A#include "sim/full_system.hh" 60932SN/A#include "sim/system.hh" 612384SN/A 622384SN/A// forward declarations 632384SN/Aclass Checkpoint; 64807SN/Aclass Process; 652542SN/Aclass Processor; 661634SN/Aclass ThreadContext; 67865SN/A 68865SN/Anamespace TheISA 69891SN/A{ 701149SN/A class DTB; 711149SN/A class ITB; 721149SN/A} 732846Ssaidi@eecs.umich.edu 742846Ssaidi@eecs.umich.edunamespace Trace { 752846Ssaidi@eecs.umich.edu class InstRecord; 762846Ssaidi@eecs.umich.edu} 772846Ssaidi@eecs.umich.edu 782846Ssaidi@eecs.umich.edustruct BaseSimpleCPUParams; 792846Ssaidi@eecs.umich.edu 802846Ssaidi@eecs.umich.edu 81807SN/Aclass BaseSimpleCPU : public BaseCPU 82807SN/A{ 831634SN/A protected: 84 typedef TheISA::MiscReg MiscReg; 85 typedef TheISA::FloatReg FloatReg; 86 typedef TheISA::FloatRegBits FloatRegBits; 87 88 protected: 89 Trace::InstRecord *traceData; 90 91 inline void checkPcEventQueue() { 92 Addr oldpc, pc = thread->instAddr(); 93 do { 94 oldpc = pc; 95 system->pcEventQueue.service(tc); 96 pc = thread->instAddr(); 97 } while (oldpc != pc); 98 } 99 100 public: 101 void wakeup(); 102 103 void zero_fill_64(Addr addr) { 104 static int warned = 0; 105 if (!warned) { 106 warn ("WH64 is not implemented"); 107 warned = 1; 108 } 109 }; 110 111 public: 112 BaseSimpleCPU(BaseSimpleCPUParams *params); 113 virtual ~BaseSimpleCPU(); 114 115 public: 116 /** SimpleThread object, provides all the architectural state. */ 117 SimpleThread *thread; 118 119 /** ThreadContext object, provides an interface for external 120 * objects to modify this thread's state. 121 */ 122 ThreadContext *tc; 123 124 CheckerCPU *checker; 125 126 protected: 127 128 enum Status { 129 Idle, 130 Running, 131 Faulting, 132 ITBWaitResponse, 133 IcacheRetry, 134 IcacheWaitResponse, 135 IcacheWaitSwitch, 136 DTBWaitResponse, 137 DcacheRetry, 138 DcacheWaitResponse, 139 DcacheWaitSwitch, 140 }; 141 142 Status _status; 143 144 public: 145 146 Addr dbg_vtophys(Addr addr); 147 148 bool interval_stats; 149 150 // current instruction 151 TheISA::MachInst inst; 152 153 StaticInstPtr curStaticInst; 154 StaticInstPtr curMacroStaticInst; 155 156 //This is the offset from the current pc that fetch should be performed at 157 Addr fetchOffset; 158 //This flag says to stay at the current pc. This is useful for 159 //instructions which go beyond MachInst boundaries. 160 bool stayAtPC; 161 162 void checkForInterrupts(); 163 void setupFetchRequest(Request *req); 164 void preExecute(); 165 void postExecute(); 166 void advancePC(Fault fault); 167 168 virtual void deallocateContext(ThreadID thread_num); 169 virtual void haltContext(ThreadID thread_num); 170 171 // statistics 172 virtual void regStats(); 173 virtual void resetStats(); 174 175 virtual void startup(); 176 177 // number of simulated instructions 178 Counter numInst; 179 Counter startNumInst; 180 Stats::Scalar numInsts; 181 Counter numOp; 182 Counter startNumOp; 183 Stats::Scalar numOps; 184 185 void countInst() 186 { 187 if (!curStaticInst->isMicroop() || curStaticInst->isLastMicroop()) { 188 numInst++; 189 numInsts++; 190 } 191 numOp++; 192 numOps++; 193 194 system->totalNumInsts++; 195 thread->funcExeInst++; 196 } 197 198 virtual Counter totalInsts() const 199 { 200 return numInst - startNumInst; 201 } 202 203 virtual Counter totalOps() const 204 { 205 return numOp - startNumOp; 206 } 207 208 //number of integer alu accesses 209 Stats::Scalar numIntAluAccesses; 210 211 //number of float alu accesses 212 Stats::Scalar numFpAluAccesses; 213 214 //number of function calls/returns 215 Stats::Scalar numCallsReturns; 216 217 //conditional control instructions; 218 Stats::Scalar numCondCtrlInsts; 219 220 //number of int instructions 221 Stats::Scalar numIntInsts; 222 223 //number of float instructions 224 Stats::Scalar numFpInsts; 225 226 //number of integer register file accesses 227 Stats::Scalar numIntRegReads; 228 Stats::Scalar numIntRegWrites; 229 230 //number of float register file accesses 231 Stats::Scalar numFpRegReads; 232 Stats::Scalar numFpRegWrites; 233 234 // number of simulated memory references 235 Stats::Scalar numMemRefs; 236 Stats::Scalar numLoadInsts; 237 Stats::Scalar numStoreInsts; 238 239 // number of idle cycles 240 Stats::Formula numIdleCycles; 241 242 // number of busy cycles 243 Stats::Formula numBusyCycles; 244 245 // number of simulated loads 246 Counter numLoad; 247 Counter startNumLoad; 248 249 // number of idle cycles 250 Stats::Average notIdleFraction; 251 Stats::Formula idleFraction; 252 253 // number of cycles stalled for I-cache responses 254 Stats::Scalar icacheStallCycles; 255 Counter lastIcacheStall; 256 257 // number of cycles stalled for I-cache retries 258 Stats::Scalar icacheRetryCycles; 259 Counter lastIcacheRetry; 260 261 // number of cycles stalled for D-cache responses 262 Stats::Scalar dcacheStallCycles; 263 Counter lastDcacheStall; 264 265 // number of cycles stalled for D-cache retries 266 Stats::Scalar dcacheRetryCycles; 267 Counter lastDcacheRetry; 268 269 void serializeThread(std::ostream &os, ThreadID tid); 270 void unserializeThread(Checkpoint *cp, const std::string §ion, 271 ThreadID tid); 272 273 // These functions are only used in CPU models that split 274 // effective address computation from the actual memory access. 275 void setEA(Addr EA) { panic("BaseSimpleCPU::setEA() not implemented\n"); } 276 Addr getEA() { panic("BaseSimpleCPU::getEA() not implemented\n"); 277 M5_DUMMY_RETURN} 278 279 // The register accessor methods provide the index of the 280 // instruction's operand (e.g., 0 or 1), not the architectural 281 // register index, to simplify the implementation of register 282 // renaming. We find the architectural register index by indexing 283 // into the instruction's own operand index table. Note that a 284 // raw pointer to the StaticInst is provided instead of a 285 // ref-counted StaticInstPtr to redice overhead. This is fine as 286 // long as these methods don't copy the pointer into any long-term 287 // storage (which is pretty hard to imagine they would have reason 288 // to do). 289 290 uint64_t readIntRegOperand(const StaticInst *si, int idx) 291 { 292 numIntRegReads++; 293 return thread->readIntReg(si->srcRegIdx(idx)); 294 } 295 296 FloatReg readFloatRegOperand(const StaticInst *si, int idx) 297 { 298 numFpRegReads++; 299 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Reg_Base; 300 return thread->readFloatReg(reg_idx); 301 } 302 303 FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx) 304 { 305 numFpRegReads++; 306 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Reg_Base; 307 return thread->readFloatRegBits(reg_idx); 308 } 309 310 void setIntRegOperand(const StaticInst *si, int idx, uint64_t val) 311 { 312 numIntRegWrites++; 313 thread->setIntReg(si->destRegIdx(idx), val); 314 } 315 316 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val) 317 { 318 numFpRegWrites++; 319 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Reg_Base; 320 thread->setFloatReg(reg_idx, val); 321 } 322 323 void setFloatRegOperandBits(const StaticInst *si, int idx, 324 FloatRegBits val) 325 { 326 numFpRegWrites++; 327 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Reg_Base; 328 thread->setFloatRegBits(reg_idx, val); 329 } 330 331 bool readPredicate() { return thread->readPredicate(); } 332 void setPredicate(bool val) 333 { 334 thread->setPredicate(val); 335 if (traceData) { 336 traceData->setPredicate(val); 337 } 338 } 339 TheISA::PCState pcState() { return thread->pcState(); } 340 void pcState(const TheISA::PCState &val) { thread->pcState(val); } 341 Addr instAddr() { return thread->instAddr(); } 342 Addr nextInstAddr() { return thread->nextInstAddr(); } 343 MicroPC microPC() { return thread->microPC(); } 344 345 MiscReg readMiscRegNoEffect(int misc_reg) 346 { 347 return thread->readMiscRegNoEffect(misc_reg); 348 } 349 350 MiscReg readMiscReg(int misc_reg) 351 { 352 numIntRegReads++; 353 return thread->readMiscReg(misc_reg); 354 } 355 356 void setMiscReg(int misc_reg, const MiscReg &val) 357 { 358 numIntRegWrites++; 359 return thread->setMiscReg(misc_reg, val); 360 } 361 362 MiscReg readMiscRegOperand(const StaticInst *si, int idx) 363 { 364 numIntRegReads++; 365 int reg_idx = si->srcRegIdx(idx) - TheISA::Misc_Reg_Base; 366 return thread->readMiscReg(reg_idx); 367 } 368 369 void setMiscRegOperand( 370 const StaticInst *si, int idx, const MiscReg &val) 371 { 372 numIntRegWrites++; 373 int reg_idx = si->destRegIdx(idx) - TheISA::Misc_Reg_Base; 374 return thread->setMiscReg(reg_idx, val); 375 } 376 377 void demapPage(Addr vaddr, uint64_t asn) 378 { 379 thread->demapPage(vaddr, asn); 380 } 381 382 void demapInstPage(Addr vaddr, uint64_t asn) 383 { 384 thread->demapInstPage(vaddr, asn); 385 } 386 387 void demapDataPage(Addr vaddr, uint64_t asn) 388 { 389 thread->demapDataPage(vaddr, asn); 390 } 391 392 unsigned readStCondFailures() { 393 return thread->readStCondFailures(); 394 } 395 396 void setStCondFailures(unsigned sc_failures) { 397 thread->setStCondFailures(sc_failures); 398 } 399 400 MiscReg readRegOtherThread(int regIdx, ThreadID tid = InvalidThreadID) 401 { 402 panic("Simple CPU models do not support multithreaded " 403 "register access.\n"); 404 } 405 406 void setRegOtherThread(int regIdx, const MiscReg &val, 407 ThreadID tid = InvalidThreadID) 408 { 409 panic("Simple CPU models do not support multithreaded " 410 "register access.\n"); 411 } 412 413 //Fault CacheOp(uint8_t Op, Addr EA); 414 415 Fault hwrei() { return thread->hwrei(); } 416 bool simPalCheck(int palFunc) { return thread->simPalCheck(palFunc); } 417 418 void 419 syscall(int64_t callnum) 420 { 421 if (FullSystem) 422 panic("Syscall emulation isn't available in FS mode.\n"); 423 424 thread->syscall(callnum); 425 } 426 427 bool misspeculating() { return thread->misspeculating(); } 428 ThreadContext *tcBase() { return tc; } 429}; 430 431#endif // __CPU_SIMPLE_BASE_HH__ 432