base.hh revision 9023:e9201a7bce59
1/* 2 * Copyright (c) 2011 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2002-2005 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Steve Reinhardt 41 * Dave Greene 42 * Nathan Binkert 43 */ 44 45#ifndef __CPU_SIMPLE_BASE_HH__ 46#define __CPU_SIMPLE_BASE_HH__ 47 48#include "base/statistics.hh" 49#include "config/the_isa.hh" 50#include "cpu/base.hh" 51#include "cpu/checker/cpu.hh" 52#include "cpu/pc_event.hh" 53#include "cpu/simple_thread.hh" 54#include "cpu/static_inst.hh" 55#include "mem/packet.hh" 56#include "mem/port.hh" 57#include "mem/request.hh" 58#include "sim/eventq.hh" 59#include "sim/full_system.hh" 60#include "sim/system.hh" 61 62// forward declarations 63class Checkpoint; 64class Process; 65class Processor; 66class ThreadContext; 67 68namespace TheISA 69{ 70 class DTB; 71 class ITB; 72} 73 74namespace Trace { 75 class InstRecord; 76} 77 78struct BaseSimpleCPUParams; 79 80 81class BaseSimpleCPU : public BaseCPU 82{ 83 protected: 84 typedef TheISA::MiscReg MiscReg; 85 typedef TheISA::FloatReg FloatReg; 86 typedef TheISA::FloatRegBits FloatRegBits; 87 88 protected: 89 Trace::InstRecord *traceData; 90 91 inline void checkPcEventQueue() { 92 Addr oldpc, pc = thread->instAddr(); 93 do { 94 oldpc = pc; 95 system->pcEventQueue.service(tc); 96 pc = thread->instAddr(); 97 } while (oldpc != pc); 98 } 99 100 public: 101 void wakeup(); 102 103 void zero_fill_64(Addr addr) { 104 static int warned = 0; 105 if (!warned) { 106 warn ("WH64 is not implemented"); 107 warned = 1; 108 } 109 }; 110 111 public: 112 BaseSimpleCPU(BaseSimpleCPUParams *params); 113 virtual ~BaseSimpleCPU(); 114 115 public: 116 /** SimpleThread object, provides all the architectural state. */ 117 SimpleThread *thread; 118 119 /** ThreadContext object, provides an interface for external 120 * objects to modify this thread's state. 121 */ 122 ThreadContext *tc; 123 124 CheckerCPU *checker; 125 126 protected: 127 128 enum Status { 129 Idle, 130 Running, 131 Faulting, 132 ITBWaitResponse, 133 IcacheRetry, 134 IcacheWaitResponse, 135 IcacheWaitSwitch, 136 DTBWaitResponse, 137 DcacheRetry, 138 DcacheWaitResponse, 139 DcacheWaitSwitch, 140 SwitchedOut 141 }; 142 143 Status _status; 144 145 public: 146 147 Addr dbg_vtophys(Addr addr); 148 149 bool interval_stats; 150 151 // current instruction 152 TheISA::MachInst inst; 153 154 StaticInstPtr curStaticInst; 155 StaticInstPtr curMacroStaticInst; 156 157 //This is the offset from the current pc that fetch should be performed at 158 Addr fetchOffset; 159 //This flag says to stay at the current pc. This is useful for 160 //instructions which go beyond MachInst boundaries. 161 bool stayAtPC; 162 163 void checkForInterrupts(); 164 void setupFetchRequest(Request *req); 165 void preExecute(); 166 void postExecute(); 167 void advancePC(Fault fault); 168 169 virtual void deallocateContext(ThreadID thread_num); 170 virtual void haltContext(ThreadID thread_num); 171 172 // statistics 173 virtual void regStats(); 174 virtual void resetStats(); 175 176 // number of simulated instructions 177 Counter numInst; 178 Counter startNumInst; 179 Stats::Scalar numInsts; 180 Counter numOp; 181 Counter startNumOp; 182 Stats::Scalar numOps; 183 184 void countInst() 185 { 186 if (!curStaticInst->isMicroop() || curStaticInst->isLastMicroop()) { 187 numInst++; 188 numInsts++; 189 } 190 numOp++; 191 numOps++; 192 193 system->totalNumInsts++; 194 thread->funcExeInst++; 195 } 196 197 virtual Counter totalInsts() const 198 { 199 return numInst - startNumInst; 200 } 201 202 virtual Counter totalOps() const 203 { 204 return numOp - startNumOp; 205 } 206 207 //number of integer alu accesses 208 Stats::Scalar numIntAluAccesses; 209 210 //number of float alu accesses 211 Stats::Scalar numFpAluAccesses; 212 213 //number of function calls/returns 214 Stats::Scalar numCallsReturns; 215 216 //conditional control instructions; 217 Stats::Scalar numCondCtrlInsts; 218 219 //number of int instructions 220 Stats::Scalar numIntInsts; 221 222 //number of float instructions 223 Stats::Scalar numFpInsts; 224 225 //number of integer register file accesses 226 Stats::Scalar numIntRegReads; 227 Stats::Scalar numIntRegWrites; 228 229 //number of float register file accesses 230 Stats::Scalar numFpRegReads; 231 Stats::Scalar numFpRegWrites; 232 233 // number of simulated memory references 234 Stats::Scalar numMemRefs; 235 Stats::Scalar numLoadInsts; 236 Stats::Scalar numStoreInsts; 237 238 // number of idle cycles 239 Stats::Formula numIdleCycles; 240 241 // number of busy cycles 242 Stats::Formula numBusyCycles; 243 244 // number of simulated loads 245 Counter numLoad; 246 Counter startNumLoad; 247 248 // number of idle cycles 249 Stats::Average notIdleFraction; 250 Stats::Formula idleFraction; 251 252 // number of cycles stalled for I-cache responses 253 Stats::Scalar icacheStallCycles; 254 Counter lastIcacheStall; 255 256 // number of cycles stalled for I-cache retries 257 Stats::Scalar icacheRetryCycles; 258 Counter lastIcacheRetry; 259 260 // number of cycles stalled for D-cache responses 261 Stats::Scalar dcacheStallCycles; 262 Counter lastDcacheStall; 263 264 // number of cycles stalled for D-cache retries 265 Stats::Scalar dcacheRetryCycles; 266 Counter lastDcacheRetry; 267 268 virtual void serialize(std::ostream &os); 269 virtual void unserialize(Checkpoint *cp, const std::string §ion); 270 271 // These functions are only used in CPU models that split 272 // effective address computation from the actual memory access. 273 void setEA(Addr EA) { panic("BaseSimpleCPU::setEA() not implemented\n"); } 274 Addr getEA() { panic("BaseSimpleCPU::getEA() not implemented\n"); 275 M5_DUMMY_RETURN} 276 277 // The register accessor methods provide the index of the 278 // instruction's operand (e.g., 0 or 1), not the architectural 279 // register index, to simplify the implementation of register 280 // renaming. We find the architectural register index by indexing 281 // into the instruction's own operand index table. Note that a 282 // raw pointer to the StaticInst is provided instead of a 283 // ref-counted StaticInstPtr to redice overhead. This is fine as 284 // long as these methods don't copy the pointer into any long-term 285 // storage (which is pretty hard to imagine they would have reason 286 // to do). 287 288 uint64_t readIntRegOperand(const StaticInst *si, int idx) 289 { 290 numIntRegReads++; 291 return thread->readIntReg(si->srcRegIdx(idx)); 292 } 293 294 FloatReg readFloatRegOperand(const StaticInst *si, int idx) 295 { 296 numFpRegReads++; 297 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; 298 return thread->readFloatReg(reg_idx); 299 } 300 301 FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx) 302 { 303 numFpRegReads++; 304 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; 305 return thread->readFloatRegBits(reg_idx); 306 } 307 308 void setIntRegOperand(const StaticInst *si, int idx, uint64_t val) 309 { 310 numIntRegWrites++; 311 thread->setIntReg(si->destRegIdx(idx), val); 312 } 313 314 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val) 315 { 316 numFpRegWrites++; 317 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; 318 thread->setFloatReg(reg_idx, val); 319 } 320 321 void setFloatRegOperandBits(const StaticInst *si, int idx, 322 FloatRegBits val) 323 { 324 numFpRegWrites++; 325 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; 326 thread->setFloatRegBits(reg_idx, val); 327 } 328 329 bool readPredicate() { return thread->readPredicate(); } 330 void setPredicate(bool val) 331 { 332 thread->setPredicate(val); 333 if (traceData) { 334 traceData->setPredicate(val); 335 } 336 } 337 TheISA::PCState pcState() { return thread->pcState(); } 338 void pcState(const TheISA::PCState &val) { thread->pcState(val); } 339 Addr instAddr() { return thread->instAddr(); } 340 Addr nextInstAddr() { return thread->nextInstAddr(); } 341 MicroPC microPC() { return thread->microPC(); } 342 343 MiscReg readMiscRegNoEffect(int misc_reg) 344 { 345 return thread->readMiscRegNoEffect(misc_reg); 346 } 347 348 MiscReg readMiscReg(int misc_reg) 349 { 350 numIntRegReads++; 351 return thread->readMiscReg(misc_reg); 352 } 353 354 void setMiscReg(int misc_reg, const MiscReg &val) 355 { 356 numIntRegWrites++; 357 return thread->setMiscReg(misc_reg, val); 358 } 359 360 MiscReg readMiscRegOperand(const StaticInst *si, int idx) 361 { 362 numIntRegReads++; 363 int reg_idx = si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag; 364 return thread->readMiscReg(reg_idx); 365 } 366 367 void setMiscRegOperand( 368 const StaticInst *si, int idx, const MiscReg &val) 369 { 370 numIntRegWrites++; 371 int reg_idx = si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag; 372 return thread->setMiscReg(reg_idx, val); 373 } 374 375 void demapPage(Addr vaddr, uint64_t asn) 376 { 377 thread->demapPage(vaddr, asn); 378 } 379 380 void demapInstPage(Addr vaddr, uint64_t asn) 381 { 382 thread->demapInstPage(vaddr, asn); 383 } 384 385 void demapDataPage(Addr vaddr, uint64_t asn) 386 { 387 thread->demapDataPage(vaddr, asn); 388 } 389 390 unsigned readStCondFailures() { 391 return thread->readStCondFailures(); 392 } 393 394 void setStCondFailures(unsigned sc_failures) { 395 thread->setStCondFailures(sc_failures); 396 } 397 398 MiscReg readRegOtherThread(int regIdx, ThreadID tid = InvalidThreadID) 399 { 400 panic("Simple CPU models do not support multithreaded " 401 "register access.\n"); 402 } 403 404 void setRegOtherThread(int regIdx, const MiscReg &val, 405 ThreadID tid = InvalidThreadID) 406 { 407 panic("Simple CPU models do not support multithreaded " 408 "register access.\n"); 409 } 410 411 //Fault CacheOp(uint8_t Op, Addr EA); 412 413 Fault hwrei() { return thread->hwrei(); } 414 bool simPalCheck(int palFunc) { return thread->simPalCheck(palFunc); } 415 416 void 417 syscall(int64_t callnum) 418 { 419 if (FullSystem) 420 panic("Syscall emulation isn't available in FS mode.\n"); 421 422 thread->syscall(callnum); 423 } 424 425 bool misspeculating() { return thread->misspeculating(); } 426 ThreadContext *tcBase() { return tc; } 427}; 428 429#endif // __CPU_SIMPLE_BASE_HH__ 430