base.hh revision 7764:03efcdc3421f
1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Steve Reinhardt 29 * Dave Greene 30 * Nathan Binkert 31 */ 32 33#ifndef __CPU_SIMPLE_BASE_HH__ 34#define __CPU_SIMPLE_BASE_HH__ 35 36#include "arch/predecoder.hh" 37#include "base/statistics.hh" 38#include "config/full_system.hh" 39#include "config/the_isa.hh" 40#include "cpu/base.hh" 41#include "cpu/simple_thread.hh" 42#include "cpu/pc_event.hh" 43#include "cpu/static_inst.hh" 44#include "mem/packet.hh" 45#include "mem/port.hh" 46#include "mem/request.hh" 47#include "sim/eventq.hh" 48#include "sim/system.hh" 49 50// forward declarations 51#if FULL_SYSTEM 52class Processor; 53namespace TheISA 54{ 55 class ITB; 56 class DTB; 57} 58class MemObject; 59 60#else 61 62class Process; 63 64#endif // FULL_SYSTEM 65 66namespace TheISA 67{ 68 class Predecoder; 69} 70class ThreadContext; 71class Checkpoint; 72 73namespace Trace { 74 class InstRecord; 75} 76 77class BaseSimpleCPUParams; 78 79 80class BaseSimpleCPU : public BaseCPU 81{ 82 protected: 83 typedef TheISA::MiscReg MiscReg; 84 typedef TheISA::FloatReg FloatReg; 85 typedef TheISA::FloatRegBits FloatRegBits; 86 87 protected: 88 Trace::InstRecord *traceData; 89 90 inline void checkPcEventQueue() { 91 Addr oldpc, pc = thread->instAddr(); 92 do { 93 oldpc = pc; 94 system->pcEventQueue.service(tc); 95 pc = thread->instAddr(); 96 } while (oldpc != pc); 97 } 98 99 public: 100 void wakeup(); 101 102 void zero_fill_64(Addr addr) { 103 static int warned = 0; 104 if (!warned) { 105 warn ("WH64 is not implemented"); 106 warned = 1; 107 } 108 }; 109 110 public: 111 BaseSimpleCPU(BaseSimpleCPUParams *params); 112 virtual ~BaseSimpleCPU(); 113 114 public: 115 /** SimpleThread object, provides all the architectural state. */ 116 SimpleThread *thread; 117 118 /** ThreadContext object, provides an interface for external 119 * objects to modify this thread's state. 120 */ 121 ThreadContext *tc; 122 protected: 123 124 enum Status { 125 Idle, 126 Running, 127 ITBWaitResponse, 128 IcacheRetry, 129 IcacheWaitResponse, 130 IcacheWaitSwitch, 131 DTBWaitResponse, 132 DcacheRetry, 133 DcacheWaitResponse, 134 DcacheWaitSwitch, 135 SwitchedOut 136 }; 137 138 Status _status; 139 140 public: 141 142#if FULL_SYSTEM 143 Addr dbg_vtophys(Addr addr); 144 145 bool interval_stats; 146#endif 147 148 // current instruction 149 TheISA::MachInst inst; 150 151 // The predecoder 152 TheISA::Predecoder predecoder; 153 154 StaticInstPtr curStaticInst; 155 StaticInstPtr curMacroStaticInst; 156 157 //This is the offset from the current pc that fetch should be performed at 158 Addr fetchOffset; 159 //This flag says to stay at the current pc. This is useful for 160 //instructions which go beyond MachInst boundaries. 161 bool stayAtPC; 162 163 void checkForInterrupts(); 164 void setupFetchRequest(Request *req); 165 void preExecute(); 166 void postExecute(); 167 void advancePC(Fault fault); 168 169 virtual void deallocateContext(int thread_num); 170 virtual void haltContext(int thread_num); 171 172 // statistics 173 virtual void regStats(); 174 virtual void resetStats(); 175 176 // number of simulated instructions 177 Counter numInst; 178 Counter startNumInst; 179 Stats::Scalar numInsts; 180 181 void countInst() 182 { 183 numInst++; 184 numInsts++; 185 186 thread->funcExeInst++; 187 } 188 189 virtual Counter totalInstructions() const 190 { 191 return numInst - startNumInst; 192 } 193 194 // number of simulated memory references 195 Stats::Scalar numMemRefs; 196 197 // number of simulated loads 198 Counter numLoad; 199 Counter startNumLoad; 200 201 // number of idle cycles 202 Stats::Average notIdleFraction; 203 Stats::Formula idleFraction; 204 205 // number of cycles stalled for I-cache responses 206 Stats::Scalar icacheStallCycles; 207 Counter lastIcacheStall; 208 209 // number of cycles stalled for I-cache retries 210 Stats::Scalar icacheRetryCycles; 211 Counter lastIcacheRetry; 212 213 // number of cycles stalled for D-cache responses 214 Stats::Scalar dcacheStallCycles; 215 Counter lastDcacheStall; 216 217 // number of cycles stalled for D-cache retries 218 Stats::Scalar dcacheRetryCycles; 219 Counter lastDcacheRetry; 220 221 virtual void serialize(std::ostream &os); 222 virtual void unserialize(Checkpoint *cp, const std::string §ion); 223 224 // These functions are only used in CPU models that split 225 // effective address computation from the actual memory access. 226 void setEA(Addr EA) { panic("BaseSimpleCPU::setEA() not implemented\n"); } 227 Addr getEA() { panic("BaseSimpleCPU::getEA() not implemented\n"); 228 M5_DUMMY_RETURN} 229 230 // The register accessor methods provide the index of the 231 // instruction's operand (e.g., 0 or 1), not the architectural 232 // register index, to simplify the implementation of register 233 // renaming. We find the architectural register index by indexing 234 // into the instruction's own operand index table. Note that a 235 // raw pointer to the StaticInst is provided instead of a 236 // ref-counted StaticInstPtr to redice overhead. This is fine as 237 // long as these methods don't copy the pointer into any long-term 238 // storage (which is pretty hard to imagine they would have reason 239 // to do). 240 241 uint64_t readIntRegOperand(const StaticInst *si, int idx) 242 { 243 return thread->readIntReg(si->srcRegIdx(idx)); 244 } 245 246 FloatReg readFloatRegOperand(const StaticInst *si, int idx) 247 { 248 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; 249 return thread->readFloatReg(reg_idx); 250 } 251 252 FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx) 253 { 254 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; 255 return thread->readFloatRegBits(reg_idx); 256 } 257 258 void setIntRegOperand(const StaticInst *si, int idx, uint64_t val) 259 { 260 thread->setIntReg(si->destRegIdx(idx), val); 261 } 262 263 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val) 264 { 265 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; 266 thread->setFloatReg(reg_idx, val); 267 } 268 269 void setFloatRegOperandBits(const StaticInst *si, int idx, 270 FloatRegBits val) 271 { 272 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; 273 thread->setFloatRegBits(reg_idx, val); 274 } 275 276 bool readPredicate() { return thread->readPredicate(); } 277 void setPredicate(bool val) 278 { 279 thread->setPredicate(val); 280 if (traceData) { 281 traceData->setPredicate(val); 282 } 283 } 284 TheISA::PCState pcState() { return thread->pcState(); } 285 void pcState(const TheISA::PCState &val) { thread->pcState(val); } 286 Addr instAddr() { return thread->instAddr(); } 287 Addr nextInstAddr() { return thread->nextInstAddr(); } 288 MicroPC microPC() { return thread->microPC(); } 289 290 MiscReg readMiscRegNoEffect(int misc_reg) 291 { 292 return thread->readMiscRegNoEffect(misc_reg); 293 } 294 295 MiscReg readMiscReg(int misc_reg) 296 { 297 return thread->readMiscReg(misc_reg); 298 } 299 300 void setMiscRegNoEffect(int misc_reg, const MiscReg &val) 301 { 302 return thread->setMiscRegNoEffect(misc_reg, val); 303 } 304 305 void setMiscReg(int misc_reg, const MiscReg &val) 306 { 307 return thread->setMiscReg(misc_reg, val); 308 } 309 310 MiscReg readMiscRegOperandNoEffect(const StaticInst *si, int idx) 311 { 312 int reg_idx = si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag; 313 return thread->readMiscRegNoEffect(reg_idx); 314 } 315 316 MiscReg readMiscRegOperand(const StaticInst *si, int idx) 317 { 318 int reg_idx = si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag; 319 return thread->readMiscReg(reg_idx); 320 } 321 322 void setMiscRegOperandNoEffect(const StaticInst *si, int idx, const MiscReg &val) 323 { 324 int reg_idx = si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag; 325 return thread->setMiscRegNoEffect(reg_idx, val); 326 } 327 328 void setMiscRegOperand( 329 const StaticInst *si, int idx, const MiscReg &val) 330 { 331 int reg_idx = si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag; 332 return thread->setMiscReg(reg_idx, val); 333 } 334 335 void demapPage(Addr vaddr, uint64_t asn) 336 { 337 thread->demapPage(vaddr, asn); 338 } 339 340 void demapInstPage(Addr vaddr, uint64_t asn) 341 { 342 thread->demapInstPage(vaddr, asn); 343 } 344 345 void demapDataPage(Addr vaddr, uint64_t asn) 346 { 347 thread->demapDataPage(vaddr, asn); 348 } 349 350 unsigned readStCondFailures() { 351 return thread->readStCondFailures(); 352 } 353 354 void setStCondFailures(unsigned sc_failures) { 355 thread->setStCondFailures(sc_failures); 356 } 357 358 MiscReg readRegOtherThread(int regIdx, ThreadID tid = InvalidThreadID) 359 { 360 panic("Simple CPU models do not support multithreaded " 361 "register access.\n"); 362 } 363 364 void setRegOtherThread(int regIdx, const MiscReg &val, 365 ThreadID tid = InvalidThreadID) 366 { 367 panic("Simple CPU models do not support multithreaded " 368 "register access.\n"); 369 } 370 371 //Fault CacheOp(uint8_t Op, Addr EA); 372 373#if FULL_SYSTEM 374 Fault hwrei() { return thread->hwrei(); } 375 bool simPalCheck(int palFunc) { return thread->simPalCheck(palFunc); } 376#else 377 void syscall(int64_t callnum) { thread->syscall(callnum); } 378#endif 379 380 bool misspeculating() { return thread->misspeculating(); } 381 ThreadContext *tcBase() { return tc; } 382}; 383 384#endif // __CPU_SIMPLE_BASE_HH__ 385