base.hh revision 707 
1/*
2 * Copyright (c) 2003 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#ifndef __SIMPLE_CPU_HH__
30#define __SIMPLE_CPU_HH__
31
32#include "cpu/base_cpu.hh"
33#include "sim/eventq.hh"
34#include "base/loader/symtab.hh"
35#include "cpu/pc_event.hh"
36#include "base/statistics.hh"
37
38
39// forward declarations
40#ifdef FULL_SYSTEM
41class Processor;
42class Kernel;
43class AlphaITB;
44class AlphaDTB;
45class PhysicalMemory;
46
47class RemoteGDB;
48class GDBListener;
49#endif // FULL_SYSTEM
50
51class MemInterface;
52class Checkpoint;
53
54namespace Trace {
55    class InstRecord;
56}
57
58class SimpleCPU : public BaseCPU
59{
60  public:
61    // main simulation loop (one cycle)
62    void tick();
63
64  private:
65    class TickEvent : public Event
66    {
67      private:
68        SimpleCPU *cpu;
69
70      public:
71        TickEvent(SimpleCPU *c);
72        void process();
73        const char *description();
74    };
75
76    TickEvent tickEvent;
77
78    /// Schedule tick event, regardless of its current state.
79    void scheduleTickEvent(int delay)
80    {
81        if (tickEvent.squashed())
82            tickEvent.reschedule(curTick + delay);
83        else if (!tickEvent.scheduled())
84            tickEvent.schedule(curTick + delay);
85    }
86
87    /// Unschedule tick event, regardless of its current state.
88    void unscheduleTickEvent()
89    {
90        if (tickEvent.scheduled())
91            tickEvent.squash();
92    }
93
94  private:
95    Trace::InstRecord *traceData;
96    template<typename T>
97    void trace_data(T data) {
98      if (traceData) {
99        traceData->setData(data);
100      }
101    };
102
103  public:
104    //
105    enum Status {
106        Running,
107        Idle,
108        IcacheMissStall,
109        IcacheMissComplete,
110        DcacheMissStall,
111        SwitchedOut
112    };
113
114  private:
115    Status _status;
116
117  public:
118    void post_interrupt(int int_num, int index);
119
120    void zero_fill_64(Addr addr) {
121      static int warned = 0;
122      if (!warned) {
123        warn ("WH64 is not implemented");
124        warned = 1;
125      }
126    };
127
128#ifdef FULL_SYSTEM
129
130    SimpleCPU(const std::string &_name,
131              System *_system,
132              Counter max_insts_any_thread, Counter max_insts_all_threads,
133              Counter max_loads_any_thread, Counter max_loads_all_threads,
134              AlphaITB *itb, AlphaDTB *dtb, FunctionalMemory *mem,
135              MemInterface *icache_interface, MemInterface *dcache_interface,
136              bool _def_reg, Tick freq);
137
138#else
139
140    SimpleCPU(const std::string &_name, Process *_process,
141              Counter max_insts_any_thread,
142              Counter max_insts_all_threads,
143              Counter max_loads_any_thread,
144              Counter max_loads_all_threads,
145              MemInterface *icache_interface, MemInterface *dcache_interface,
146              bool _def_reg);
147
148#endif
149
150    virtual ~SimpleCPU();
151    virtual void init();
152
153    // execution context
154    ExecContext *xc;
155
156    void switchOut();
157    void takeOverFrom(BaseCPU *oldCPU);
158
159#ifdef FULL_SYSTEM
160    Addr dbg_vtophys(Addr addr);
161
162    bool interval_stats;
163#endif
164
165    // L1 instruction cache
166    MemInterface *icacheInterface;
167
168    // L1 data cache
169    MemInterface *dcacheInterface;
170
171    bool defer_registration;
172
173    // current instruction
174    MachInst inst;
175
176    // Refcounted pointer to the one memory request.
177    MemReqPtr memReq;
178
179    class CacheCompletionEvent : public Event
180    {
181      private:
182        SimpleCPU *cpu;
183
184      public:
185        CacheCompletionEvent(SimpleCPU *_cpu);
186
187        virtual void process();
188        virtual const char *description();
189    };
190
191    CacheCompletionEvent cacheCompletionEvent;
192
193    Status status() const { return _status; }
194
195    virtual void activateContext(int thread_num, int delay);
196    virtual void suspendContext(int thread_num);
197    virtual void deallocateContext(int thread_num);
198    virtual void haltContext(int thread_num);
199
200    // statistics
201    virtual void regStats();
202    virtual void resetStats();
203
204    // number of simulated instructions
205    Counter numInst;
206    Counter startNumInst;
207    Statistics::Scalar<> numInsts;
208
209    virtual Counter totalInstructions() const
210    {
211        return numInst - startNumInst;
212    }
213
214    // number of simulated memory references
215    Statistics::Scalar<> numMemRefs;
216
217    // number of simulated loads
218    Counter numLoad;
219    Counter startNumLoad;
220
221    // number of idle cycles
222    Statistics::Average<> notIdleFraction;
223    Statistics::Formula idleFraction;
224
225    // number of cycles stalled for I-cache misses
226    Statistics::Scalar<> icacheStallCycles;
227    Counter lastIcacheStall;
228
229    // number of cycles stalled for D-cache misses
230    Statistics::Scalar<> dcacheStallCycles;
231    Counter lastDcacheStall;
232
233    void processCacheCompletion();
234
235    virtual void serialize(std::ostream &os);
236    virtual void unserialize(Checkpoint *cp, const std::string &section);
237
238    template <class T>
239    Fault read(Addr addr, T &data, unsigned flags);
240
241    template <class T>
242    Fault write(T data, Addr addr, unsigned flags,
243                        uint64_t *res);
244
245    void prefetch(Addr addr, unsigned flags)
246    {
247        // need to do this...
248    }
249
250    void writeHint(Addr addr, int size)
251    {
252        // need to do this...
253    }
254
255    Fault copySrcTranslate(Addr src);
256
257    Fault copy(Addr dest);
258
259    uint64_t readIntReg(int reg_idx) { return xc->readIntReg(reg_idx); }
260
261    float readFloatRegSingle(int reg_idx)
262    { return xc->readFloatRegSingle(reg_idx); }
263
264    double readFloatRegDouble(int reg_idx)
265    { return xc->readFloatRegDouble(reg_idx); }
266
267    uint64_t readFloatRegInt(int reg_idx)
268    { return xc->readFloatRegInt(reg_idx); }
269
270    void setIntReg(int reg_idx, uint64_t val)
271    { return xc->setIntReg(reg_idx, val); }
272
273    void setFloatRegSingle(int reg_idx, float val)
274    { return xc->setFloatRegSingle(reg_idx, val); }
275
276    void setFloatRegDouble(int reg_idx, double val)
277    { return xc->setFloatRegDouble(reg_idx, val); }
278
279    void setFloatRegInt(int reg_idx, uint64_t val)
280    { return xc->setFloatRegInt(reg_idx, val); }
281
282    uint64_t readPC() { return xc->readPC(); }
283    void setNextPC(uint64_t val) { return xc->setNextPC(val); }
284
285    uint64_t readUniq() { return xc->readUniq(); }
286    void setUniq(uint64_t val) { return xc->setUniq(val); }
287
288    uint64_t readFpcr() { return xc->readFpcr(); }
289    void setFpcr(uint64_t val) { return xc->setFpcr(val); }
290
291#ifdef FULL_SYSTEM
292    uint64_t readIpr(int idx, Fault &fault) { return xc->readIpr(idx, fault); }
293    Fault setIpr(int idx, uint64_t val) { return xc->setIpr(idx, val); }
294    Fault hwrei() { return xc->hwrei(); }
295    int readIntrFlag() { return xc->readIntrFlag(); }
296    void setIntrFlag(int val) { xc->setIntrFlag(val); }
297    bool inPalMode() { return xc->inPalMode(); }
298    void ev5_trap(Fault fault) { return xc->ev5_trap(fault); }
299    bool simPalCheck(int palFunc) { return xc->simPalCheck(palFunc); }
300#else
301    void syscall() { xc->syscall(); }
302#endif
303
304    bool misspeculating() { return xc->misspeculating(); }
305    ExecContext *xcBase() { return xc; }
306};
307
308typedef SimpleCPU SimpleCPUExecContext;
309
310#endif // __SIMPLE_CPU_HH__
311