base.hh revision 6314:781969fbeca9
1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Steve Reinhardt 29 * Dave Greene 30 * Nathan Binkert 31 */ 32 33#ifndef __CPU_SIMPLE_BASE_HH__ 34#define __CPU_SIMPLE_BASE_HH__ 35 36#include "arch/predecoder.hh" 37#include "base/statistics.hh" 38#include "config/full_system.hh" 39#include "cpu/base.hh" 40#include "cpu/simple_thread.hh" 41#include "cpu/pc_event.hh" 42#include "cpu/static_inst.hh" 43#include "mem/packet.hh" 44#include "mem/port.hh" 45#include "mem/request.hh" 46#include "sim/eventq.hh" 47#include "sim/system.hh" 48 49// forward declarations 50#if FULL_SYSTEM 51class Processor; 52namespace TheISA 53{ 54 class ITB; 55 class DTB; 56} 57class MemObject; 58 59#else 60 61class Process; 62 63#endif // FULL_SYSTEM 64 65class RemoteGDB; 66class GDBListener; 67 68namespace TheISA 69{ 70 class Predecoder; 71} 72class ThreadContext; 73class Checkpoint; 74 75namespace Trace { 76 class InstRecord; 77} 78 79class BaseSimpleCPUParams; 80 81 82class BaseSimpleCPU : public BaseCPU 83{ 84 protected: 85 typedef TheISA::MiscReg MiscReg; 86 typedef TheISA::FloatReg FloatReg; 87 typedef TheISA::FloatRegBits FloatRegBits; 88 89 protected: 90 Trace::InstRecord *traceData; 91 92 inline void checkPcEventQueue() { 93 Addr oldpc; 94 do { 95 oldpc = thread->readPC(); 96 system->pcEventQueue.service(tc); 97 } while (oldpc != thread->readPC()); 98 } 99 100 public: 101 void wakeup(); 102 103 void zero_fill_64(Addr addr) { 104 static int warned = 0; 105 if (!warned) { 106 warn ("WH64 is not implemented"); 107 warned = 1; 108 } 109 }; 110 111 public: 112 BaseSimpleCPU(BaseSimpleCPUParams *params); 113 virtual ~BaseSimpleCPU(); 114 115 public: 116 /** SimpleThread object, provides all the architectural state. */ 117 SimpleThread *thread; 118 119 /** ThreadContext object, provides an interface for external 120 * objects to modify this thread's state. 121 */ 122 ThreadContext *tc; 123 protected: 124 125 enum Status { 126 Idle, 127 Running, 128 ITBWaitResponse, 129 IcacheRetry, 130 IcacheWaitResponse, 131 IcacheWaitSwitch, 132 DTBWaitResponse, 133 DcacheRetry, 134 DcacheWaitResponse, 135 DcacheWaitSwitch, 136 SwitchedOut 137 }; 138 139 Status _status; 140 141 public: 142 143#if FULL_SYSTEM 144 Addr dbg_vtophys(Addr addr); 145 146 bool interval_stats; 147#endif 148 149 // current instruction 150 TheISA::MachInst inst; 151 152 // The predecoder 153 TheISA::Predecoder predecoder; 154 155 StaticInstPtr curStaticInst; 156 StaticInstPtr curMacroStaticInst; 157 158 //This is the offset from the current pc that fetch should be performed at 159 Addr fetchOffset; 160 //This flag says to stay at the current pc. This is useful for 161 //instructions which go beyond MachInst boundaries. 162 bool stayAtPC; 163 164 void checkForInterrupts(); 165 void setupFetchRequest(Request *req); 166 void preExecute(); 167 void postExecute(); 168 void advancePC(Fault fault); 169 170 virtual void deallocateContext(int thread_num); 171 virtual void haltContext(int thread_num); 172 173 // statistics 174 virtual void regStats(); 175 virtual void resetStats(); 176 177 // number of simulated instructions 178 Counter numInst; 179 Counter startNumInst; 180 Stats::Scalar numInsts; 181 182 void countInst() 183 { 184 numInst++; 185 numInsts++; 186 187 thread->funcExeInst++; 188 } 189 190 virtual Counter totalInstructions() const 191 { 192 return numInst - startNumInst; 193 } 194 195 // Mask to align PCs to MachInst sized boundaries 196 static const Addr PCMask = ~((Addr)sizeof(TheISA::MachInst) - 1); 197 198 // number of simulated memory references 199 Stats::Scalar numMemRefs; 200 201 // number of simulated loads 202 Counter numLoad; 203 Counter startNumLoad; 204 205 // number of idle cycles 206 Stats::Average notIdleFraction; 207 Stats::Formula idleFraction; 208 209 // number of cycles stalled for I-cache responses 210 Stats::Scalar icacheStallCycles; 211 Counter lastIcacheStall; 212 213 // number of cycles stalled for I-cache retries 214 Stats::Scalar icacheRetryCycles; 215 Counter lastIcacheRetry; 216 217 // number of cycles stalled for D-cache responses 218 Stats::Scalar dcacheStallCycles; 219 Counter lastDcacheStall; 220 221 // number of cycles stalled for D-cache retries 222 Stats::Scalar dcacheRetryCycles; 223 Counter lastDcacheRetry; 224 225 virtual void serialize(std::ostream &os); 226 virtual void unserialize(Checkpoint *cp, const std::string §ion); 227 228 // These functions are only used in CPU models that split 229 // effective address computation from the actual memory access. 230 void setEA(Addr EA) { panic("BaseSimpleCPU::setEA() not implemented\n"); } 231 Addr getEA() { panic("BaseSimpleCPU::getEA() not implemented\n"); 232 M5_DUMMY_RETURN} 233 234 void prefetch(Addr addr, unsigned flags) 235 { 236 // need to do this... 237 } 238 239 void writeHint(Addr addr, int size, unsigned flags) 240 { 241 // need to do this... 242 } 243 244 245 Fault copySrcTranslate(Addr src); 246 247 Fault copy(Addr dest); 248 249 // The register accessor methods provide the index of the 250 // instruction's operand (e.g., 0 or 1), not the architectural 251 // register index, to simplify the implementation of register 252 // renaming. We find the architectural register index by indexing 253 // into the instruction's own operand index table. Note that a 254 // raw pointer to the StaticInst is provided instead of a 255 // ref-counted StaticInstPtr to redice overhead. This is fine as 256 // long as these methods don't copy the pointer into any long-term 257 // storage (which is pretty hard to imagine they would have reason 258 // to do). 259 260 uint64_t readIntRegOperand(const StaticInst *si, int idx) 261 { 262 return thread->readIntReg(si->srcRegIdx(idx)); 263 } 264 265 FloatReg readFloatRegOperand(const StaticInst *si, int idx) 266 { 267 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; 268 return thread->readFloatReg(reg_idx); 269 } 270 271 FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx) 272 { 273 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; 274 return thread->readFloatRegBits(reg_idx); 275 } 276 277 void setIntRegOperand(const StaticInst *si, int idx, uint64_t val) 278 { 279 thread->setIntReg(si->destRegIdx(idx), val); 280 } 281 282 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val) 283 { 284 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; 285 thread->setFloatReg(reg_idx, val); 286 } 287 288 void setFloatRegOperandBits(const StaticInst *si, int idx, 289 FloatRegBits val) 290 { 291 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; 292 thread->setFloatRegBits(reg_idx, val); 293 } 294 295 uint64_t readPC() { return thread->readPC(); } 296 uint64_t readMicroPC() { return thread->readMicroPC(); } 297 uint64_t readNextPC() { return thread->readNextPC(); } 298 uint64_t readNextMicroPC() { return thread->readNextMicroPC(); } 299 uint64_t readNextNPC() { return thread->readNextNPC(); } 300 301 void setPC(uint64_t val) { thread->setPC(val); } 302 void setMicroPC(uint64_t val) { thread->setMicroPC(val); } 303 void setNextPC(uint64_t val) { thread->setNextPC(val); } 304 void setNextMicroPC(uint64_t val) { thread->setNextMicroPC(val); } 305 void setNextNPC(uint64_t val) { thread->setNextNPC(val); } 306 307 MiscReg readMiscRegNoEffect(int misc_reg) 308 { 309 return thread->readMiscRegNoEffect(misc_reg); 310 } 311 312 MiscReg readMiscReg(int misc_reg) 313 { 314 return thread->readMiscReg(misc_reg); 315 } 316 317 void setMiscRegNoEffect(int misc_reg, const MiscReg &val) 318 { 319 return thread->setMiscRegNoEffect(misc_reg, val); 320 } 321 322 void setMiscReg(int misc_reg, const MiscReg &val) 323 { 324 return thread->setMiscReg(misc_reg, val); 325 } 326 327 MiscReg readMiscRegOperandNoEffect(const StaticInst *si, int idx) 328 { 329 int reg_idx = si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag; 330 return thread->readMiscRegNoEffect(reg_idx); 331 } 332 333 MiscReg readMiscRegOperand(const StaticInst *si, int idx) 334 { 335 int reg_idx = si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag; 336 return thread->readMiscReg(reg_idx); 337 } 338 339 void setMiscRegOperandNoEffect(const StaticInst *si, int idx, const MiscReg &val) 340 { 341 int reg_idx = si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag; 342 return thread->setMiscRegNoEffect(reg_idx, val); 343 } 344 345 void setMiscRegOperand( 346 const StaticInst *si, int idx, const MiscReg &val) 347 { 348 int reg_idx = si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag; 349 return thread->setMiscReg(reg_idx, val); 350 } 351 352 void demapPage(Addr vaddr, uint64_t asn) 353 { 354 thread->demapPage(vaddr, asn); 355 } 356 357 void demapInstPage(Addr vaddr, uint64_t asn) 358 { 359 thread->demapInstPage(vaddr, asn); 360 } 361 362 void demapDataPage(Addr vaddr, uint64_t asn) 363 { 364 thread->demapDataPage(vaddr, asn); 365 } 366 367 unsigned readStCondFailures() { 368 return thread->readStCondFailures(); 369 } 370 371 void setStCondFailures(unsigned sc_failures) { 372 thread->setStCondFailures(sc_failures); 373 } 374 375 MiscReg readRegOtherThread(int regIdx, ThreadID tid = InvalidThreadID) 376 { 377 panic("Simple CPU models do not support multithreaded " 378 "register access.\n"); 379 } 380 381 void setRegOtherThread(int regIdx, const MiscReg &val, 382 ThreadID tid = InvalidThreadID) 383 { 384 panic("Simple CPU models do not support multithreaded " 385 "register access.\n"); 386 } 387 388 //Fault CacheOp(uint8_t Op, Addr EA); 389 390#if FULL_SYSTEM 391 Fault hwrei() { return thread->hwrei(); } 392 void ev5_trap(Fault fault) { fault->invoke(tc); } 393 bool simPalCheck(int palFunc) { return thread->simPalCheck(palFunc); } 394#else 395 void syscall(int64_t callnum) { thread->syscall(callnum); } 396#endif 397 398 bool misspeculating() { return thread->misspeculating(); } 399 ThreadContext *tcBase() { return tc; } 400}; 401 402#endif // __CPU_SIMPLE_BASE_HH__ 403