base.hh revision 4182
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 *          Dave Greene
30 *          Nathan Binkert
31 */
32
33#ifndef __CPU_SIMPLE_BASE_HH__
34#define __CPU_SIMPLE_BASE_HH__
35
36#include "arch/predecoder.hh"
37#include "base/statistics.hh"
38#include "config/full_system.hh"
39#include "cpu/base.hh"
40#include "cpu/simple_thread.hh"
41#include "cpu/pc_event.hh"
42#include "cpu/static_inst.hh"
43#include "mem/packet.hh"
44#include "mem/port.hh"
45#include "mem/request.hh"
46#include "sim/eventq.hh"
47
48// forward declarations
49#if FULL_SYSTEM
50class Processor;
51namespace TheISA
52{
53    class ITB;
54    class DTB;
55}
56class MemObject;
57
58#else
59
60class Process;
61
62#endif // FULL_SYSTEM
63
64class RemoteGDB;
65class GDBListener;
66
67namespace TheISA
68{
69    class Predecoder;
70}
71class ThreadContext;
72class Checkpoint;
73
74namespace Trace {
75    class InstRecord;
76}
77
78
79class BaseSimpleCPU : public BaseCPU
80{
81  protected:
82    typedef TheISA::MiscReg MiscReg;
83    typedef TheISA::FloatReg FloatReg;
84    typedef TheISA::FloatRegBits FloatRegBits;
85
86  protected:
87    Trace::InstRecord *traceData;
88
89  public:
90    void post_interrupt(int int_num, int index);
91
92    void zero_fill_64(Addr addr) {
93      static int warned = 0;
94      if (!warned) {
95        warn ("WH64 is not implemented");
96        warned = 1;
97      }
98    };
99
100  public:
101    struct Params : public BaseCPU::Params
102    {
103#if FULL_SYSTEM
104        TheISA::ITB *itb;
105        TheISA::DTB *dtb;
106#else
107        Process *process;
108#endif
109    };
110    BaseSimpleCPU(Params *params);
111    virtual ~BaseSimpleCPU();
112
113  public:
114    /** SimpleThread object, provides all the architectural state. */
115    SimpleThread *thread;
116
117    /** ThreadContext object, provides an interface for external
118     * objects to modify this thread's state.
119     */
120    ThreadContext *tc;
121
122#if FULL_SYSTEM
123    Addr dbg_vtophys(Addr addr);
124
125    bool interval_stats;
126#endif
127
128    // current instruction
129    TheISA::MachInst inst;
130
131    // The predecoder
132    TheISA::Predecoder predecoder;
133
134    // Static data storage
135    TheISA::LargestRead dataReg;
136
137    StaticInstPtr curStaticInst;
138    StaticInstPtr curMacroStaticInst;
139
140    void checkForInterrupts();
141    Fault setupFetchRequest(Request *req);
142    void preExecute();
143    void postExecute();
144    void advancePC(Fault fault);
145
146    virtual void deallocateContext(int thread_num);
147    virtual void haltContext(int thread_num);
148
149    // statistics
150    virtual void regStats();
151    virtual void resetStats();
152
153    // number of simulated instructions
154    Counter numInst;
155    Counter startNumInst;
156    Stats::Scalar<> numInsts;
157
158    virtual Counter totalInstructions() const
159    {
160        return numInst - startNumInst;
161    }
162
163    // number of simulated memory references
164    Stats::Scalar<> numMemRefs;
165
166    // number of simulated loads
167    Counter numLoad;
168    Counter startNumLoad;
169
170    // number of idle cycles
171    Stats::Average<> notIdleFraction;
172    Stats::Formula idleFraction;
173
174    // number of cycles stalled for I-cache responses
175    Stats::Scalar<> icacheStallCycles;
176    Counter lastIcacheStall;
177
178    // number of cycles stalled for I-cache retries
179    Stats::Scalar<> icacheRetryCycles;
180    Counter lastIcacheRetry;
181
182    // number of cycles stalled for D-cache responses
183    Stats::Scalar<> dcacheStallCycles;
184    Counter lastDcacheStall;
185
186    // number of cycles stalled for D-cache retries
187    Stats::Scalar<> dcacheRetryCycles;
188    Counter lastDcacheRetry;
189
190    virtual void serialize(std::ostream &os);
191    virtual void unserialize(Checkpoint *cp, const std::string &section);
192
193    // These functions are only used in CPU models that split
194    // effective address computation from the actual memory access.
195    void setEA(Addr EA) { panic("BaseSimpleCPU::setEA() not implemented\n"); }
196    Addr getEA() 	{ panic("BaseSimpleCPU::getEA() not implemented\n");
197        M5_DUMMY_RETURN}
198
199    void prefetch(Addr addr, unsigned flags)
200    {
201        // need to do this...
202    }
203
204    void writeHint(Addr addr, int size, unsigned flags)
205    {
206        // need to do this...
207    }
208
209    Fault copySrcTranslate(Addr src);
210
211    Fault copy(Addr dest);
212
213    // The register accessor methods provide the index of the
214    // instruction's operand (e.g., 0 or 1), not the architectural
215    // register index, to simplify the implementation of register
216    // renaming.  We find the architectural register index by indexing
217    // into the instruction's own operand index table.  Note that a
218    // raw pointer to the StaticInst is provided instead of a
219    // ref-counted StaticInstPtr to redice overhead.  This is fine as
220    // long as these methods don't copy the pointer into any long-term
221    // storage (which is pretty hard to imagine they would have reason
222    // to do).
223
224    uint64_t readIntRegOperand(const StaticInst *si, int idx)
225    {
226        return thread->readIntReg(si->srcRegIdx(idx));
227    }
228
229    FloatReg readFloatRegOperand(const StaticInst *si, int idx, int width)
230    {
231        int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
232        return thread->readFloatReg(reg_idx, width);
233    }
234
235    FloatReg readFloatRegOperand(const StaticInst *si, int idx)
236    {
237        int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
238        return thread->readFloatReg(reg_idx);
239    }
240
241    FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx,
242                                         int width)
243    {
244        int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
245        return thread->readFloatRegBits(reg_idx, width);
246    }
247
248    FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx)
249    {
250        int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
251        return thread->readFloatRegBits(reg_idx);
252    }
253
254    void setIntRegOperand(const StaticInst *si, int idx, uint64_t val)
255    {
256        thread->setIntReg(si->destRegIdx(idx), val);
257    }
258
259    void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val,
260                            int width)
261    {
262        int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
263        thread->setFloatReg(reg_idx, val, width);
264    }
265
266    void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
267    {
268        int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
269        thread->setFloatReg(reg_idx, val);
270    }
271
272    void setFloatRegOperandBits(const StaticInst *si, int idx,
273                                FloatRegBits val, int width)
274    {
275        int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
276        thread->setFloatRegBits(reg_idx, val, width);
277    }
278
279    void setFloatRegOperandBits(const StaticInst *si, int idx,
280                                FloatRegBits val)
281    {
282        int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
283        thread->setFloatRegBits(reg_idx, val);
284    }
285
286    uint64_t readPC() { return thread->readPC(); }
287    uint64_t readNextPC() { return thread->readNextPC(); }
288    uint64_t readNextNPC() { return thread->readNextNPC(); }
289
290    void setPC(uint64_t val) { thread->setPC(val); }
291    void setNextPC(uint64_t val) { thread->setNextPC(val); }
292    void setNextNPC(uint64_t val) { thread->setNextNPC(val); }
293
294    MiscReg readMiscRegNoEffect(int misc_reg)
295    {
296        return thread->readMiscRegNoEffect(misc_reg);
297    }
298
299    MiscReg readMiscReg(int misc_reg)
300    {
301        return thread->readMiscReg(misc_reg);
302    }
303
304    void setMiscRegNoEffect(int misc_reg, const MiscReg &val)
305    {
306        return thread->setMiscRegNoEffect(misc_reg, val);
307    }
308
309    void setMiscReg(int misc_reg, const MiscReg &val)
310    {
311        return thread->setMiscReg(misc_reg, val);
312    }
313
314    MiscReg readMiscRegOperand(const StaticInst *si, int idx)
315    {
316        int reg_idx = si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
317        return thread->readMiscRegNoEffect(reg_idx);
318    }
319
320    MiscReg readMiscRegOperandWithEffect(const StaticInst *si, int idx)
321    {
322        int reg_idx = si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
323        return thread->readMiscReg(reg_idx);
324    }
325
326    void setMiscRegOperand(const StaticInst *si, int idx, const MiscReg &val)
327    {
328        int reg_idx = si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
329        return thread->setMiscRegNoEffect(reg_idx, val);
330    }
331
332    void setMiscRegOperandWithEffect(
333            const StaticInst *si, int idx, const MiscReg &val)
334    {
335        int reg_idx = si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
336        return thread->setMiscReg(reg_idx, val);
337    }
338
339    unsigned readStCondFailures() {
340        return thread->readStCondFailures();
341    }
342
343    void setStCondFailures(unsigned sc_failures) {
344        thread->setStCondFailures(sc_failures);
345    }
346
347#if FULL_SYSTEM
348    Fault hwrei() { return thread->hwrei(); }
349    void ev5_trap(Fault fault) { fault->invoke(tc); }
350    bool simPalCheck(int palFunc) { return thread->simPalCheck(palFunc); }
351#else
352    void syscall(int64_t callnum) { thread->syscall(callnum); }
353#endif
354
355    bool misspeculating() { return thread->misspeculating(); }
356    ThreadContext *tcBase() { return tc; }
357};
358
359#endif // __CPU_SIMPLE_BASE_HH__
360