base.hh revision 2159
1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29#ifndef __CPU_SIMPLE_CPU_SIMPLE_CPU_HH__ 30#define __CPU_SIMPLE_CPU_SIMPLE_CPU_HH__ 31 32#include "base/statistics.hh" 33#include "config/full_system.hh" 34#include "cpu/base.hh" 35#include "cpu/exec_context.hh" 36#include "cpu/pc_event.hh" 37#include "cpu/sampler/sampler.hh" 38#include "cpu/static_inst.hh" 39#include "sim/eventq.hh" 40 41// forward declarations 42#if FULL_SYSTEM 43class Processor; 44class AlphaITB; 45class AlphaDTB; 46class PhysicalMemory; 47 48class RemoteGDB; 49class GDBListener; 50 51#else 52 53class Process; 54 55#endif // FULL_SYSTEM 56 57class MemInterface; 58class Checkpoint; 59 60namespace Trace { 61 class InstRecord; 62} 63 64class SimpleCPU : public BaseCPU 65{ 66 protected: 67 typedef TheISA::MachInst MachInst; 68 typedef TheISA::MiscReg MiscReg; 69 public: 70 // main simulation loop (one cycle) 71 void tick(); 72 virtual void init(); 73 74 private: 75 struct TickEvent : public Event 76 { 77 SimpleCPU *cpu; 78 int width; 79 80 TickEvent(SimpleCPU *c, int w); 81 void process(); 82 const char *description(); 83 }; 84 85 TickEvent tickEvent; 86 87 /// Schedule tick event, regardless of its current state. 88 void scheduleTickEvent(int numCycles) 89 { 90 if (tickEvent.squashed()) 91 tickEvent.reschedule(curTick + cycles(numCycles)); 92 else if (!tickEvent.scheduled()) 93 tickEvent.schedule(curTick + cycles(numCycles)); 94 } 95 96 /// Unschedule tick event, regardless of its current state. 97 void unscheduleTickEvent() 98 { 99 if (tickEvent.scheduled()) 100 tickEvent.squash(); 101 } 102 103 private: 104 Trace::InstRecord *traceData; 105 106 public: 107 // 108 enum Status { 109 Running, 110 Idle, 111 IcacheMissStall, 112 IcacheMissComplete, 113 DcacheMissStall, 114 DcacheMissSwitch, 115 SwitchedOut 116 }; 117 118 private: 119 Status _status; 120 121 public: 122 void post_interrupt(int int_num, int index); 123 124 void zero_fill_64(Addr addr) { 125 static int warned = 0; 126 if (!warned) { 127 warn ("WH64 is not implemented"); 128 warned = 1; 129 } 130 }; 131 132 public: 133 struct Params : public BaseCPU::Params 134 { 135 MemInterface *icache_interface; 136 MemInterface *dcache_interface; 137 int width; 138#if FULL_SYSTEM 139 AlphaITB *itb; 140 AlphaDTB *dtb; 141 FunctionalMemory *mem; 142#else 143 Process *process; 144#endif 145 }; 146 SimpleCPU(Params *params); 147 virtual ~SimpleCPU(); 148 149 public: 150 // execution context 151 ExecContext *xc; 152 153 void switchOut(Sampler *s); 154 void takeOverFrom(BaseCPU *oldCPU); 155 156#if FULL_SYSTEM 157 Addr dbg_vtophys(Addr addr); 158 159 bool interval_stats; 160#endif 161 162 // L1 instruction cache 163 MemInterface *icacheInterface; 164 165 // L1 data cache 166 MemInterface *dcacheInterface; 167 168 // current instruction 169 MachInst inst; 170 171 // Refcounted pointer to the one memory request. 172 MemReqPtr memReq; 173 174 // Pointer to the sampler that is telling us to switchover. 175 // Used to signal the completion of the pipe drain and schedule 176 // the next switchover 177 Sampler *sampler; 178 179 StaticInstPtr curStaticInst; 180 181 class CacheCompletionEvent : public Event 182 { 183 private: 184 SimpleCPU *cpu; 185 186 public: 187 CacheCompletionEvent(SimpleCPU *_cpu); 188 189 virtual void process(); 190 virtual const char *description(); 191 }; 192 193 CacheCompletionEvent cacheCompletionEvent; 194 195 Status status() const { return _status; } 196 197 virtual void activateContext(int thread_num, int delay); 198 virtual void suspendContext(int thread_num); 199 virtual void deallocateContext(int thread_num); 200 virtual void haltContext(int thread_num); 201 202 // statistics 203 virtual void regStats(); 204 virtual void resetStats(); 205 206 // number of simulated instructions 207 Counter numInst; 208 Counter startNumInst; 209 Stats::Scalar<> numInsts; 210 211 virtual Counter totalInstructions() const 212 { 213 return numInst - startNumInst; 214 } 215 216 // number of simulated memory references 217 Stats::Scalar<> numMemRefs; 218 219 // number of simulated loads 220 Counter numLoad; 221 Counter startNumLoad; 222 223 // number of idle cycles 224 Stats::Average<> notIdleFraction; 225 Stats::Formula idleFraction; 226 227 // number of cycles stalled for I-cache misses 228 Stats::Scalar<> icacheStallCycles; 229 Counter lastIcacheStall; 230 231 // number of cycles stalled for D-cache misses 232 Stats::Scalar<> dcacheStallCycles; 233 Counter lastDcacheStall; 234 235 void processCacheCompletion(); 236 237 virtual void serialize(std::ostream &os); 238 virtual void unserialize(Checkpoint *cp, const std::string §ion); 239 240 template <class T> 241 Fault read(Addr addr, T &data, unsigned flags); 242 243 template <class T> 244 Fault write(T data, Addr addr, unsigned flags, uint64_t *res); 245 246 // These functions are only used in CPU models that split 247 // effective address computation from the actual memory access. 248 void setEA(Addr EA) { panic("SimpleCPU::setEA() not implemented\n"); } 249 Addr getEA() { panic("SimpleCPU::getEA() not implemented\n"); } 250 251 void prefetch(Addr addr, unsigned flags) 252 { 253 // need to do this... 254 } 255 256 void writeHint(Addr addr, int size, unsigned flags) 257 { 258 // need to do this... 259 } 260 261 Fault copySrcTranslate(Addr src); 262 263 Fault copy(Addr dest); 264 265 // The register accessor methods provide the index of the 266 // instruction's operand (e.g., 0 or 1), not the architectural 267 // register index, to simplify the implementation of register 268 // renaming. We find the architectural register index by indexing 269 // into the instruction's own operand index table. Note that a 270 // raw pointer to the StaticInst is provided instead of a 271 // ref-counted StaticInstPtr to redice overhead. This is fine as 272 // long as these methods don't copy the pointer into any long-term 273 // storage (which is pretty hard to imagine they would have reason 274 // to do). 275 276 uint64_t readIntReg(const StaticInst *si, int idx) 277 { 278 return xc->readIntReg(si->srcRegIdx(idx)); 279 } 280 281 float readFloatRegSingle(const StaticInst *si, int idx) 282 { 283 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; 284 return xc->readFloatRegSingle(reg_idx); 285 } 286 287 double readFloatRegDouble(const StaticInst *si, int idx) 288 { 289 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; 290 return xc->readFloatRegDouble(reg_idx); 291 } 292 293 uint64_t readFloatRegInt(const StaticInst *si, int idx) 294 { 295 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; 296 return xc->readFloatRegInt(reg_idx); 297 } 298 299 void setIntReg(const StaticInst *si, int idx, uint64_t val) 300 { 301 xc->setIntReg(si->destRegIdx(idx), val); 302 } 303 304 void setFloatRegSingle(const StaticInst *si, int idx, float val) 305 { 306 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; 307 xc->setFloatRegSingle(reg_idx, val); 308 } 309 310 void setFloatRegDouble(const StaticInst *si, int idx, double val) 311 { 312 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; 313 xc->setFloatRegDouble(reg_idx, val); 314 } 315 316 void setFloatRegInt(const StaticInst *si, int idx, uint64_t val) 317 { 318 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; 319 xc->setFloatRegInt(reg_idx, val); 320 } 321 322 uint64_t readPC() { return xc->readPC(); } 323 void setNextPC(uint64_t val) { xc->setNextPC(val); } 324 325 MiscReg readMiscReg(int misc_reg) 326 { 327 return xc->readMiscReg(misc_reg); 328 } 329 330 MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault) 331 { 332 return xc->readMiscRegWithEffect(misc_reg, fault); 333 } 334 335 Fault setMiscReg(int misc_reg, const MiscReg &val) 336 { 337 return xc->setMiscReg(misc_reg, val); 338 } 339 340 Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val) 341 { 342 return xc->setMiscRegWithEffect(misc_reg, val); 343 } 344 345#if FULL_SYSTEM 346 Fault hwrei() { return xc->hwrei(); } 347 int readIntrFlag() { return xc->readIntrFlag(); } 348 void setIntrFlag(int val) { xc->setIntrFlag(val); } 349 bool inPalMode() { return xc->inPalMode(); } 350 void ev5_trap(Fault fault) { xc->ev5_trap(fault); } 351 bool simPalCheck(int palFunc) { return xc->simPalCheck(palFunc); } 352#else 353 void syscall() { xc->syscall(); } 354#endif 355 356 bool misspeculating() { return xc->misspeculating(); } 357 ExecContext *xcBase() { return xc; } 358}; 359 360#endif // __CPU_SIMPLE_CPU_SIMPLE_CPU_HH__ 361