base.hh revision 180 
1/*
2 * Copyright (c) 2003 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#ifndef __SIMPLE_CPU_HH__
30#define __SIMPLE_CPU_HH__
31
32#include "cpu/base_cpu.hh"
33#include "sim/eventq.hh"
34#include "base/loader/symtab.hh"
35#include "cpu/pc_event.hh"
36#include "base/statistics.hh"
37
38
39// forward declarations
40#ifdef FULL_SYSTEM
41class Processor;
42class Kernel;
43class AlphaItb;
44class AlphaDtb;
45class PhysicalMemory;
46
47class RemoteGDB;
48class GDBListener;
49#endif // FULL_SYSTEM
50
51class MemInterface;
52class IniFile;
53
54namespace Trace {
55    class InstRecord;
56}
57
58class SimpleCPU : public BaseCPU
59{
60  public:
61    // main simulation loop (one cycle)
62    void tick();
63
64  private:
65    class TickEvent : public Event
66    {
67      private:
68        SimpleCPU *cpu;
69
70      public:
71        TickEvent(SimpleCPU *c)
72            : Event(&mainEventQueue, 100), cpu(c) { }
73        void process() { cpu->tick(); }
74        virtual const char *description() { return "tick event"; }
75    };
76
77    TickEvent tickEvent;
78
79  private:
80    Trace::InstRecord *traceData;
81    template<typename T>
82    void trace_data(T data) {
83      if (traceData) {
84        traceData->setData(data);
85      }
86    };
87
88  public:
89    //
90    enum Status {
91        Running,
92        Idle,
93        IcacheMissStall,
94        IcacheMissComplete,
95        DcacheMissStall,
96        SwitchedOut
97    };
98
99  private:
100    Status _status;
101
102  public:
103    void post_interrupt(int int_num, int index);
104
105    void zero_fill_64(Addr addr) {
106      static int warned = 0;
107      if (!warned) {
108        warn ("WH64 is not implemented");
109        warned = 1;
110      }
111    };
112
113#ifdef FULL_SYSTEM
114
115    SimpleCPU(const std::string &_name,
116              System *_system,
117              Counter max_insts_any_thread, Counter max_insts_all_threads,
118              Counter max_loads_any_thread, Counter max_loads_all_threads,
119              AlphaItb *itb, AlphaDtb *dtb, FunctionalMemory *mem,
120              MemInterface *icache_interface, MemInterface *dcache_interface,
121              Tick freq);
122
123#else
124
125    SimpleCPU(const std::string &_name, Process *_process,
126              Counter max_insts_any_thread,
127              Counter max_insts_all_threads,
128              Counter max_loads_any_thread,
129              Counter max_loads_all_threads,
130              MemInterface *icache_interface, MemInterface *dcache_interface);
131
132#endif
133
134    virtual ~SimpleCPU();
135
136    // execution context
137    ExecContext *xc;
138
139    void registerExecContexts();
140
141    void switchOut();
142    void takeOverFrom(BaseCPU *oldCPU);
143
144#ifdef FULL_SYSTEM
145    Addr dbg_vtophys(Addr addr);
146
147    bool interval_stats;
148#endif
149
150    // L1 instruction cache
151    MemInterface *icacheInterface;
152
153    // L1 data cache
154    MemInterface *dcacheInterface;
155
156    // current instruction
157    MachInst inst;
158
159    // current fault status
160    Fault fault;
161
162    // Refcounted pointer to the one memory request.
163    MemReqPtr memReq;
164
165    class CacheCompletionEvent : public Event
166    {
167      private:
168        SimpleCPU *cpu;
169
170      public:
171        CacheCompletionEvent(SimpleCPU *_cpu);
172
173        virtual void process();
174        virtual const char *description();
175    };
176
177    CacheCompletionEvent cacheCompletionEvent;
178
179    Status status() const { return _status; }
180
181    virtual void execCtxStatusChg() {
182        if (xc) {
183            if (xc->status() == ExecContext::Active)
184                setStatus(Running);
185            else
186                setStatus(Idle);
187        }
188    }
189
190    void setStatus(Status new_status) {
191        Status old_status = status();
192
193        // We should never even get here if the CPU has been switched out.
194        assert(old_status != SwitchedOut);
195
196        _status = new_status;
197
198        switch (status()) {
199          case IcacheMissStall:
200            assert(old_status == Running);
201            lastIcacheStall = curTick;
202            if (tickEvent.scheduled())
203                tickEvent.squash();
204            break;
205
206          case IcacheMissComplete:
207            assert(old_status == IcacheMissStall);
208            if (tickEvent.squashed())
209                tickEvent.reschedule(curTick + 1);
210            else if (!tickEvent.scheduled())
211                tickEvent.schedule(curTick + 1);
212            break;
213
214          case DcacheMissStall:
215            assert(old_status == Running);
216            lastDcacheStall = curTick;
217            if (tickEvent.scheduled())
218                tickEvent.squash();
219            break;
220
221          case Idle:
222            assert(old_status == Running);
223            last_idle = curTick;
224            if (tickEvent.scheduled())
225                tickEvent.squash();
226            break;
227
228          case Running:
229            assert(old_status == Idle ||
230                   old_status == DcacheMissStall ||
231                   old_status == IcacheMissComplete);
232            if (old_status == Idle)
233                idleCycles += curTick - last_idle;
234
235            if (tickEvent.squashed())
236                tickEvent.reschedule(curTick + 1);
237            else if (!tickEvent.scheduled())
238                tickEvent.schedule(curTick + 1);
239            break;
240
241          default:
242            panic("can't get here");
243        }
244    }
245
246    // statistics
247    void regStats();
248
249    // number of simulated instructions
250    Counter numInst;
251    Statistics::Formula numInsts;
252
253    // number of simulated memory references
254    Statistics::Scalar<> numMemRefs;
255
256    // number of simulated loads
257    Counter numLoad;
258
259    // number of idle cycles
260    Statistics::Scalar<> idleCycles;
261    Statistics::Formula idleFraction;
262    Counter last_idle;
263
264    // number of cycles stalled for I-cache misses
265    Statistics::Scalar<> icacheStallCycles;
266    Counter lastIcacheStall;
267
268    // number of cycles stalled for D-cache misses
269    Statistics::Scalar<> dcacheStallCycles;
270    Counter lastDcacheStall;
271
272    void processCacheCompletion();
273
274    virtual void serialize();
275    virtual void unserialize(IniFile &db, const std::string &category,
276                             ConfigNode *node);
277
278    template <class T>
279    Fault read(Addr addr, T& data, unsigned flags);
280
281    template <class T>
282    Fault write(T data, Addr addr, unsigned flags,
283                        uint64_t *res);
284
285    Fault prefetch(Addr addr, unsigned flags)
286    {
287        // need to do this...
288        return No_Fault;
289    }
290
291    void writeHint(Addr addr, int size)
292    {
293        // need to do this...
294    }
295};
296
297#endif // __SIMPLE_CPU_HH__
298