base.hh revision 13954:2f400a5f2627
15217Ssaidi@eecs.umich.edu/* 29428SAndreas.Sandberg@ARM.com * Copyright (c) 2011-2012,2015,2018 ARM Limited 39428SAndreas.Sandberg@ARM.com * Copyright (c) 2013 Advanced Micro Devices, Inc. 49428SAndreas.Sandberg@ARM.com * All rights reserved 59428SAndreas.Sandberg@ARM.com * 69428SAndreas.Sandberg@ARM.com * The license below extends only to copyright in the software and shall 79428SAndreas.Sandberg@ARM.com * not be construed as granting a license to any other intellectual 89428SAndreas.Sandberg@ARM.com * property including but not limited to intellectual property relating 99428SAndreas.Sandberg@ARM.com * to a hardware implementation of the functionality of the software 109428SAndreas.Sandberg@ARM.com * licensed hereunder. You may use the software subject to the license 119428SAndreas.Sandberg@ARM.com * terms below provided that you ensure that this notice is replicated 129428SAndreas.Sandberg@ARM.com * unmodified and in its entirety in all distributions of the software, 139428SAndreas.Sandberg@ARM.com * modified or unmodified, in source code or in binary form. 145217Ssaidi@eecs.umich.edu * 155217Ssaidi@eecs.umich.edu * Copyright (c) 2002-2005 The Regents of The University of Michigan 165217Ssaidi@eecs.umich.edu * All rights reserved. 175217Ssaidi@eecs.umich.edu * 185217Ssaidi@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 195217Ssaidi@eecs.umich.edu * modification, are permitted provided that the following conditions are 205217Ssaidi@eecs.umich.edu * met: redistributions of source code must retain the above copyright 215217Ssaidi@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 225217Ssaidi@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 235217Ssaidi@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 245217Ssaidi@eecs.umich.edu * documentation and/or other materials provided with the distribution; 255217Ssaidi@eecs.umich.edu * neither the name of the copyright holders nor the names of its 265217Ssaidi@eecs.umich.edu * contributors may be used to endorse or promote products derived from 275217Ssaidi@eecs.umich.edu * this software without specific prior written permission. 285217Ssaidi@eecs.umich.edu * 295217Ssaidi@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 305217Ssaidi@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 315217Ssaidi@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 325217Ssaidi@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 335217Ssaidi@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 345217Ssaidi@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 355217Ssaidi@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 365217Ssaidi@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 375217Ssaidi@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 385217Ssaidi@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 395217Ssaidi@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 405217Ssaidi@eecs.umich.edu * 415217Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 425217Ssaidi@eecs.umich.edu * Dave Greene 435217Ssaidi@eecs.umich.edu * Nathan Binkert 445217Ssaidi@eecs.umich.edu */ 456658Snate@binkert.org 465217Ssaidi@eecs.umich.edu#ifndef __CPU_SIMPLE_BASE_HH__ 478232Snate@binkert.org#define __CPU_SIMPLE_BASE_HH__ 485217Ssaidi@eecs.umich.edu 495217Ssaidi@eecs.umich.edu#include "base/statistics.hh" 505217Ssaidi@eecs.umich.edu#include "config/the_isa.hh" 515217Ssaidi@eecs.umich.edu#include "cpu/base.hh" 525217Ssaidi@eecs.umich.edu#include "cpu/checker/cpu.hh" 535217Ssaidi@eecs.umich.edu#include "cpu/exec_context.hh" 545217Ssaidi@eecs.umich.edu#include "cpu/pc_event.hh" 555217Ssaidi@eecs.umich.edu#include "cpu/simple_thread.hh" 565217Ssaidi@eecs.umich.edu#include "cpu/static_inst.hh" 575217Ssaidi@eecs.umich.edu#include "mem/packet.hh" 585217Ssaidi@eecs.umich.edu#include "mem/port.hh" 595217Ssaidi@eecs.umich.edu#include "mem/request.hh" 605217Ssaidi@eecs.umich.edu#include "sim/eventq.hh" 615217Ssaidi@eecs.umich.edu#include "sim/full_system.hh" 625217Ssaidi@eecs.umich.edu#include "sim/system.hh" 635217Ssaidi@eecs.umich.edu 645217Ssaidi@eecs.umich.edu// forward declarations 655217Ssaidi@eecs.umich.educlass Checkpoint; 665217Ssaidi@eecs.umich.educlass Process; 675217Ssaidi@eecs.umich.educlass Processor; 685217Ssaidi@eecs.umich.educlass ThreadContext; 695217Ssaidi@eecs.umich.edu 705217Ssaidi@eecs.umich.edunamespace TheISA 715217Ssaidi@eecs.umich.edu{ 725217Ssaidi@eecs.umich.edu class DTB; 735217Ssaidi@eecs.umich.edu class ITB; 745217Ssaidi@eecs.umich.edu} 755217Ssaidi@eecs.umich.edu 765217Ssaidi@eecs.umich.edunamespace Trace { 775217Ssaidi@eecs.umich.edu class InstRecord; 785217Ssaidi@eecs.umich.edu} 797720Sgblack@eecs.umich.edu 807720Sgblack@eecs.umich.edustruct BaseSimpleCPUParams; 815712Shsul@eecs.umich.educlass BPredUnit; 825712Shsul@eecs.umich.educlass SimpleExecContext; 835217Ssaidi@eecs.umich.edu 845217Ssaidi@eecs.umich.educlass BaseSimpleCPU : public BaseCPU 855714Shsul@eecs.umich.edu{ 865714Shsul@eecs.umich.edu protected: 875714Shsul@eecs.umich.edu ThreadID curThread; 885714Shsul@eecs.umich.edu BPredUnit *branchPred; 895714Shsul@eecs.umich.edu 905714Shsul@eecs.umich.edu void checkPcEventQueue(); 915714Shsul@eecs.umich.edu void swapActiveThread(); 925217Ssaidi@eecs.umich.edu 939428SAndreas.Sandberg@ARM.com public: 949428SAndreas.Sandberg@ARM.com BaseSimpleCPU(BaseSimpleCPUParams *params); 959428SAndreas.Sandberg@ARM.com virtual ~BaseSimpleCPU(); 969428SAndreas.Sandberg@ARM.com void wakeup(ThreadID tid) override; 979428SAndreas.Sandberg@ARM.com void init() override; 989428SAndreas.Sandberg@ARM.com public: 999428SAndreas.Sandberg@ARM.com Trace::InstRecord *traceData; 1009428SAndreas.Sandberg@ARM.com CheckerCPU *checker; 1019428SAndreas.Sandberg@ARM.com 1029428SAndreas.Sandberg@ARM.com std::vector<SimpleExecContext*> threadInfo; 1039428SAndreas.Sandberg@ARM.com std::list<ThreadID> activeThreads; 1049428SAndreas.Sandberg@ARM.com 1059428SAndreas.Sandberg@ARM.com /** Current instruction */ 1069428SAndreas.Sandberg@ARM.com TheISA::MachInst inst; 1079428SAndreas.Sandberg@ARM.com StaticInstPtr curStaticInst; 1089428SAndreas.Sandberg@ARM.com StaticInstPtr curMacroStaticInst; 1099428SAndreas.Sandberg@ARM.com 1109428SAndreas.Sandberg@ARM.com protected: 1119428SAndreas.Sandberg@ARM.com enum Status { 1129428SAndreas.Sandberg@ARM.com Idle, 1139428SAndreas.Sandberg@ARM.com Running, 1149428SAndreas.Sandberg@ARM.com Faulting, 1159428SAndreas.Sandberg@ARM.com ITBWaitResponse, 1169428SAndreas.Sandberg@ARM.com IcacheRetry, 1179428SAndreas.Sandberg@ARM.com IcacheWaitResponse, 1189428SAndreas.Sandberg@ARM.com IcacheWaitSwitch, 1199428SAndreas.Sandberg@ARM.com DTBWaitResponse, 1209428SAndreas.Sandberg@ARM.com DcacheRetry, 1219428SAndreas.Sandberg@ARM.com DcacheWaitResponse, 1229428SAndreas.Sandberg@ARM.com DcacheWaitSwitch, 1239428SAndreas.Sandberg@ARM.com }; 1249428SAndreas.Sandberg@ARM.com 1259428SAndreas.Sandberg@ARM.com Status _status; 1269428SAndreas.Sandberg@ARM.com 1279428SAndreas.Sandberg@ARM.com public: 1289428SAndreas.Sandberg@ARM.com Addr dbg_vtophys(Addr addr); 1299428SAndreas.Sandberg@ARM.com 1309428SAndreas.Sandberg@ARM.com 1319428SAndreas.Sandberg@ARM.com void checkForInterrupts(); 1329428SAndreas.Sandberg@ARM.com void setupFetchRequest(const RequestPtr &req); 1339428SAndreas.Sandberg@ARM.com void preExecute(); 1349428SAndreas.Sandberg@ARM.com void postExecute(); 1359428SAndreas.Sandberg@ARM.com void advancePC(const Fault &fault); 1369428SAndreas.Sandberg@ARM.com 1379428SAndreas.Sandberg@ARM.com void haltContext(ThreadID thread_num) override; 1389428SAndreas.Sandberg@ARM.com 139 // statistics 140 void regStats() override; 141 void resetStats() override; 142 143 void startup() override; 144 145 virtual Fault readMem(Addr addr, uint8_t* data, unsigned size, 146 Request::Flags flags, 147 const std::vector<bool>& byteEnable = 148 std::vector<bool>()) 149 { panic("readMem() is not implemented\n"); } 150 151 virtual Fault initiateMemRead(Addr addr, unsigned size, 152 Request::Flags flags, 153 const std::vector<bool>& byteEnable = 154 std::vector<bool>()) 155 { panic("initiateMemRead() is not implemented\n"); } 156 157 virtual Fault writeMem(uint8_t* data, unsigned size, Addr addr, 158 Request::Flags flags, uint64_t* res, 159 const std::vector<bool>& byteEnable = 160 std::vector<bool>()) 161 { panic("writeMem() is not implemented\n"); } 162 163 virtual Fault amoMem(Addr addr, uint8_t* data, unsigned size, 164 Request::Flags flags, 165 AtomicOpFunctor *amo_op) 166 { panic("amoMem() is not implemented\n"); } 167 168 virtual Fault initiateMemAMO(Addr addr, unsigned size, 169 Request::Flags flags, 170 AtomicOpFunctor *amo_op) 171 { panic("initiateMemAMO() is not implemented\n"); } 172 173 void countInst(); 174 Counter totalInsts() const override; 175 Counter totalOps() const override; 176 177 void serializeThread(CheckpointOut &cp, ThreadID tid) const override; 178 void unserializeThread(CheckpointIn &cp, ThreadID tid) override; 179 180}; 181 182#endif // __CPU_SIMPLE_BASE_HH__ 183