base.hh revision 13652:45d94ac03a27
15818Sgblack@eecs.umich.edu/* 25818Sgblack@eecs.umich.edu * Copyright (c) 2011-2012,2015 ARM Limited 35818Sgblack@eecs.umich.edu * Copyright (c) 2013 Advanced Micro Devices, Inc. 45818Sgblack@eecs.umich.edu * All rights reserved 55818Sgblack@eecs.umich.edu * 65818Sgblack@eecs.umich.edu * The license below extends only to copyright in the software and shall 75818Sgblack@eecs.umich.edu * not be construed as granting a license to any other intellectual 85818Sgblack@eecs.umich.edu * property including but not limited to intellectual property relating 95818Sgblack@eecs.umich.edu * to a hardware implementation of the functionality of the software 105818Sgblack@eecs.umich.edu * licensed hereunder. You may use the software subject to the license 115818Sgblack@eecs.umich.edu * terms below provided that you ensure that this notice is replicated 125818Sgblack@eecs.umich.edu * unmodified and in its entirety in all distributions of the software, 135818Sgblack@eecs.umich.edu * modified or unmodified, in source code or in binary form. 145818Sgblack@eecs.umich.edu * 155818Sgblack@eecs.umich.edu * Copyright (c) 2002-2005 The Regents of The University of Michigan 165818Sgblack@eecs.umich.edu * All rights reserved. 175818Sgblack@eecs.umich.edu * 185818Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 195818Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 205818Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 215818Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 225818Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 235818Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 245818Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 255818Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 265818Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 275818Sgblack@eecs.umich.edu * this software without specific prior written permission. 285818Sgblack@eecs.umich.edu * 295818Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 305818Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 315818Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 325818Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 335818Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 345818Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 355818Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 365818Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 375818Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 385818Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 395818Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 405818Sgblack@eecs.umich.edu * 415818Sgblack@eecs.umich.edu * Authors: Steve Reinhardt 425818Sgblack@eecs.umich.edu * Dave Greene 435818Sgblack@eecs.umich.edu * Nathan Binkert 445818Sgblack@eecs.umich.edu */ 455818Sgblack@eecs.umich.edu 465818Sgblack@eecs.umich.edu#ifndef __CPU_SIMPLE_BASE_HH__ 475818Sgblack@eecs.umich.edu#define __CPU_SIMPLE_BASE_HH__ 485818Sgblack@eecs.umich.edu 495818Sgblack@eecs.umich.edu#include "base/statistics.hh" 505818Sgblack@eecs.umich.edu#include "config/the_isa.hh" 515818Sgblack@eecs.umich.edu#include "cpu/base.hh" 525818Sgblack@eecs.umich.edu#include "cpu/checker/cpu.hh" 535818Sgblack@eecs.umich.edu#include "cpu/exec_context.hh" 545818Sgblack@eecs.umich.edu#include "cpu/pc_event.hh" 555818Sgblack@eecs.umich.edu#include "cpu/simple_thread.hh" 565818Sgblack@eecs.umich.edu#include "cpu/static_inst.hh" 575818Sgblack@eecs.umich.edu#include "mem/packet.hh" 585818Sgblack@eecs.umich.edu#include "mem/port.hh" 595818Sgblack@eecs.umich.edu#include "mem/request.hh" 605818Sgblack@eecs.umich.edu#include "sim/eventq.hh" 615818Sgblack@eecs.umich.edu#include "sim/full_system.hh" 625818Sgblack@eecs.umich.edu#include "sim/system.hh" 635818Sgblack@eecs.umich.edu 645818Sgblack@eecs.umich.edu// forward declarations 655818Sgblack@eecs.umich.educlass Checkpoint; 665818Sgblack@eecs.umich.educlass Process; 67class Processor; 68class ThreadContext; 69 70namespace TheISA 71{ 72 class DTB; 73 class ITB; 74} 75 76namespace Trace { 77 class InstRecord; 78} 79 80struct BaseSimpleCPUParams; 81class BPredUnit; 82class SimpleExecContext; 83 84class BaseSimpleCPU : public BaseCPU 85{ 86 protected: 87 ThreadID curThread; 88 BPredUnit *branchPred; 89 90 void checkPcEventQueue(); 91 void swapActiveThread(); 92 93 public: 94 BaseSimpleCPU(BaseSimpleCPUParams *params); 95 virtual ~BaseSimpleCPU(); 96 void wakeup(ThreadID tid) override; 97 void init() override; 98 public: 99 Trace::InstRecord *traceData; 100 CheckerCPU *checker; 101 102 std::vector<SimpleExecContext*> threadInfo; 103 std::list<ThreadID> activeThreads; 104 105 /** Current instruction */ 106 TheISA::MachInst inst; 107 StaticInstPtr curStaticInst; 108 StaticInstPtr curMacroStaticInst; 109 110 protected: 111 enum Status { 112 Idle, 113 Running, 114 Faulting, 115 ITBWaitResponse, 116 IcacheRetry, 117 IcacheWaitResponse, 118 IcacheWaitSwitch, 119 DTBWaitResponse, 120 DcacheRetry, 121 DcacheWaitResponse, 122 DcacheWaitSwitch, 123 }; 124 125 Status _status; 126 127 public: 128 Addr dbg_vtophys(Addr addr); 129 130 131 void checkForInterrupts(); 132 void setupFetchRequest(const RequestPtr &req); 133 void preExecute(); 134 void postExecute(); 135 void advancePC(const Fault &fault); 136 137 void haltContext(ThreadID thread_num) override; 138 139 // statistics 140 void regStats() override; 141 void resetStats() override; 142 143 void startup() override; 144 145 virtual Fault readMem(Addr addr, uint8_t* data, unsigned size, 146 Request::Flags flags) 147 { panic("readMem() is not implemented\n"); } 148 149 virtual Fault initiateMemRead(Addr addr, unsigned size, 150 Request::Flags flags) 151 { panic("initiateMemRead() is not implemented\n"); } 152 153 virtual Fault writeMem(uint8_t* data, unsigned size, Addr addr, 154 Request::Flags flags, uint64_t* res) 155 { panic("writeMem() is not implemented\n"); } 156 157 virtual Fault amoMem(Addr addr, uint8_t* data, unsigned size, 158 Request::Flags flags, 159 AtomicOpFunctor *amo_op) 160 { panic("amoMem() is not implemented\n"); } 161 162 virtual Fault initiateMemAMO(Addr addr, unsigned size, 163 Request::Flags flags, 164 AtomicOpFunctor *amo_op) 165 { panic("initiateMemAMO() is not implemented\n"); } 166 167 void countInst(); 168 Counter totalInsts() const override; 169 Counter totalOps() const override; 170 171 void serializeThread(CheckpointOut &cp, ThreadID tid) const override; 172 void unserializeThread(CheckpointIn &cp, ThreadID tid) override; 173 174}; 175 176#endif // __CPU_SIMPLE_BASE_HH__ 177