base.hh revision 9461
12889Sbinkertn@umich.edu/* 22889Sbinkertn@umich.edu * Copyright (c) 2011-2012 ARM Limited 32889Sbinkertn@umich.edu * All rights reserved 42889Sbinkertn@umich.edu * 52889Sbinkertn@umich.edu * The license below extends only to copyright in the software and shall 62889Sbinkertn@umich.edu * not be construed as granting a license to any other intellectual 72889Sbinkertn@umich.edu * property including but not limited to intellectual property relating 82889Sbinkertn@umich.edu * to a hardware implementation of the functionality of the software 92889Sbinkertn@umich.edu * licensed hereunder. You may use the software subject to the license 102889Sbinkertn@umich.edu * terms below provided that you ensure that this notice is replicated 112889Sbinkertn@umich.edu * unmodified and in its entirety in all distributions of the software, 122889Sbinkertn@umich.edu * modified or unmodified, in source code or in binary form. 132889Sbinkertn@umich.edu * 142889Sbinkertn@umich.edu * Copyright (c) 2002-2005 The Regents of The University of Michigan 152889Sbinkertn@umich.edu * All rights reserved. 162889Sbinkertn@umich.edu * 172889Sbinkertn@umich.edu * Redistribution and use in source and binary forms, with or without 182889Sbinkertn@umich.edu * modification, are permitted provided that the following conditions are 192889Sbinkertn@umich.edu * met: redistributions of source code must retain the above copyright 202889Sbinkertn@umich.edu * notice, this list of conditions and the following disclaimer; 212889Sbinkertn@umich.edu * redistributions in binary form must reproduce the above copyright 222889Sbinkertn@umich.edu * notice, this list of conditions and the following disclaimer in the 232889Sbinkertn@umich.edu * documentation and/or other materials provided with the distribution; 242889Sbinkertn@umich.edu * neither the name of the copyright holders nor the names of its 252889Sbinkertn@umich.edu * contributors may be used to endorse or promote products derived from 262889Sbinkertn@umich.edu * this software without specific prior written permission. 272889Sbinkertn@umich.edu * 282889Sbinkertn@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292889Sbinkertn@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302889Sbinkertn@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312889Sbinkertn@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322889Sbinkertn@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332889Sbinkertn@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342889Sbinkertn@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352889Sbinkertn@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362889Sbinkertn@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372889Sbinkertn@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382889Sbinkertn@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392889Sbinkertn@umich.edu * 402889Sbinkertn@umich.edu * Authors: Steve Reinhardt 412889Sbinkertn@umich.edu * Dave Greene 422889Sbinkertn@umich.edu * Nathan Binkert 432889Sbinkertn@umich.edu */ 442889Sbinkertn@umich.edu 452889Sbinkertn@umich.edu#ifndef __CPU_SIMPLE_BASE_HH__ 462889Sbinkertn@umich.edu#define __CPU_SIMPLE_BASE_HH__ 472889Sbinkertn@umich.edu 482889Sbinkertn@umich.edu#include "base/statistics.hh" 492889Sbinkertn@umich.edu#include "config/the_isa.hh" 502889Sbinkertn@umich.edu#include "cpu/base.hh" 512889Sbinkertn@umich.edu#include "cpu/checker/cpu.hh" 522889Sbinkertn@umich.edu#include "cpu/pc_event.hh" 532890Sbinkertn@umich.edu#include "cpu/simple_thread.hh" 542889Sbinkertn@umich.edu#include "cpu/static_inst.hh" 552889Sbinkertn@umich.edu#include "mem/packet.hh" 562889Sbinkertn@umich.edu#include "mem/port.hh" 572889Sbinkertn@umich.edu#include "mem/request.hh" 582889Sbinkertn@umich.edu#include "sim/eventq.hh" 592889Sbinkertn@umich.edu#include "sim/full_system.hh" 602889Sbinkertn@umich.edu#include "sim/system.hh" 612889Sbinkertn@umich.edu 622889Sbinkertn@umich.edu// forward declarations 632889Sbinkertn@umich.educlass Checkpoint; 642889Sbinkertn@umich.educlass Process; 652889Sbinkertn@umich.educlass Processor; 662889Sbinkertn@umich.educlass ThreadContext; 672889Sbinkertn@umich.edu 682889Sbinkertn@umich.edunamespace TheISA 692889Sbinkertn@umich.edu{ 702889Sbinkertn@umich.edu class DTB; 712889Sbinkertn@umich.edu class ITB; 722889Sbinkertn@umich.edu} 732889Sbinkertn@umich.edu 742889Sbinkertn@umich.edunamespace Trace { 752889Sbinkertn@umich.edu class InstRecord; 762889Sbinkertn@umich.edu} 772889Sbinkertn@umich.edu 782889Sbinkertn@umich.edustruct BaseSimpleCPUParams; 792889Sbinkertn@umich.edu 802889Sbinkertn@umich.edu 812889Sbinkertn@umich.educlass BaseSimpleCPU : public BaseCPU 822889Sbinkertn@umich.edu{ 832889Sbinkertn@umich.edu protected: 842889Sbinkertn@umich.edu typedef TheISA::MiscReg MiscReg; 852889Sbinkertn@umich.edu typedef TheISA::FloatReg FloatReg; 862889Sbinkertn@umich.edu typedef TheISA::FloatRegBits FloatRegBits; 872889Sbinkertn@umich.edu 882889Sbinkertn@umich.edu protected: 892889Sbinkertn@umich.edu Trace::InstRecord *traceData; 902889Sbinkertn@umich.edu 912889Sbinkertn@umich.edu inline void checkPcEventQueue() { 922889Sbinkertn@umich.edu Addr oldpc, pc = thread->instAddr(); 932889Sbinkertn@umich.edu do { 942889Sbinkertn@umich.edu oldpc = pc; 952889Sbinkertn@umich.edu system->pcEventQueue.service(tc); 962889Sbinkertn@umich.edu pc = thread->instAddr(); 972889Sbinkertn@umich.edu } while (oldpc != pc); 982889Sbinkertn@umich.edu } 992889Sbinkertn@umich.edu 1002889Sbinkertn@umich.edu public: 1012889Sbinkertn@umich.edu void wakeup(); 1022889Sbinkertn@umich.edu 1032889Sbinkertn@umich.edu void zero_fill_64(Addr addr) { 1042889Sbinkertn@umich.edu static int warned = 0; 1052889Sbinkertn@umich.edu if (!warned) { 1062889Sbinkertn@umich.edu warn ("WH64 is not implemented"); 1072889Sbinkertn@umich.edu warned = 1; 1082889Sbinkertn@umich.edu } 1092889Sbinkertn@umich.edu }; 1102889Sbinkertn@umich.edu 1112889Sbinkertn@umich.edu public: 1122889Sbinkertn@umich.edu BaseSimpleCPU(BaseSimpleCPUParams *params); 1132889Sbinkertn@umich.edu virtual ~BaseSimpleCPU(); 1142889Sbinkertn@umich.edu 1152889Sbinkertn@umich.edu public: 1162889Sbinkertn@umich.edu /** SimpleThread object, provides all the architectural state. */ 1172889Sbinkertn@umich.edu SimpleThread *thread; 1182889Sbinkertn@umich.edu 1192889Sbinkertn@umich.edu /** ThreadContext object, provides an interface for external 1202889Sbinkertn@umich.edu * objects to modify this thread's state. 1212889Sbinkertn@umich.edu */ 1222889Sbinkertn@umich.edu ThreadContext *tc; 1232889Sbinkertn@umich.edu 1242889Sbinkertn@umich.edu CheckerCPU *checker; 1252889Sbinkertn@umich.edu 1262889Sbinkertn@umich.edu protected: 1272889Sbinkertn@umich.edu 1282889Sbinkertn@umich.edu enum Status { 1292889Sbinkertn@umich.edu Idle, 1302889Sbinkertn@umich.edu Running, 1312889Sbinkertn@umich.edu Faulting, 1322889Sbinkertn@umich.edu ITBWaitResponse, 1332889Sbinkertn@umich.edu IcacheRetry, 1342889Sbinkertn@umich.edu IcacheWaitResponse, 1352889Sbinkertn@umich.edu IcacheWaitSwitch, 1362889Sbinkertn@umich.edu DTBWaitResponse, 1372889Sbinkertn@umich.edu DcacheRetry, 1382889Sbinkertn@umich.edu DcacheWaitResponse, 1392889Sbinkertn@umich.edu DcacheWaitSwitch, 1402889Sbinkertn@umich.edu }; 1412889Sbinkertn@umich.edu 1422889Sbinkertn@umich.edu Status _status; 1432889Sbinkertn@umich.edu 1442889Sbinkertn@umich.edu public: 1452889Sbinkertn@umich.edu 1462889Sbinkertn@umich.edu Addr dbg_vtophys(Addr addr); 1472889Sbinkertn@umich.edu 1482889Sbinkertn@umich.edu bool interval_stats; 1492889Sbinkertn@umich.edu 1502889Sbinkertn@umich.edu // current instruction 1512889Sbinkertn@umich.edu TheISA::MachInst inst; 1522889Sbinkertn@umich.edu 1532889Sbinkertn@umich.edu StaticInstPtr curStaticInst; 1542889Sbinkertn@umich.edu StaticInstPtr curMacroStaticInst; 1552889Sbinkertn@umich.edu 1562889Sbinkertn@umich.edu //This is the offset from the current pc that fetch should be performed at 1572889Sbinkertn@umich.edu Addr fetchOffset; 1582889Sbinkertn@umich.edu //This flag says to stay at the current pc. This is useful for 1592889Sbinkertn@umich.edu //instructions which go beyond MachInst boundaries. 1602889Sbinkertn@umich.edu bool stayAtPC; 1612889Sbinkertn@umich.edu 1622889Sbinkertn@umich.edu void checkForInterrupts(); 1632889Sbinkertn@umich.edu void setupFetchRequest(Request *req); 1642889Sbinkertn@umich.edu void preExecute(); 1652889Sbinkertn@umich.edu void postExecute(); 1662889Sbinkertn@umich.edu void advancePC(Fault fault); 1672889Sbinkertn@umich.edu 1682889Sbinkertn@umich.edu virtual void deallocateContext(ThreadID thread_num); 1692889Sbinkertn@umich.edu virtual void haltContext(ThreadID thread_num); 1702889Sbinkertn@umich.edu 1712889Sbinkertn@umich.edu // statistics 1722889Sbinkertn@umich.edu virtual void regStats(); 1732889Sbinkertn@umich.edu virtual void resetStats(); 1742889Sbinkertn@umich.edu 1752889Sbinkertn@umich.edu virtual void startup(); 1762889Sbinkertn@umich.edu 1772889Sbinkertn@umich.edu // number of simulated instructions 1782889Sbinkertn@umich.edu Counter numInst; 1792889Sbinkertn@umich.edu Counter startNumInst; 1802889Sbinkertn@umich.edu Stats::Scalar numInsts; 1812889Sbinkertn@umich.edu Counter numOp; 1822889Sbinkertn@umich.edu Counter startNumOp; 1832889Sbinkertn@umich.edu Stats::Scalar numOps; 1842889Sbinkertn@umich.edu 1852889Sbinkertn@umich.edu void countInst() 1862889Sbinkertn@umich.edu { 1872889Sbinkertn@umich.edu if (!curStaticInst->isMicroop() || curStaticInst->isLastMicroop()) { 1882889Sbinkertn@umich.edu numInst++; 1892889Sbinkertn@umich.edu numInsts++; 1902889Sbinkertn@umich.edu } 1912889Sbinkertn@umich.edu numOp++; 1922889Sbinkertn@umich.edu numOps++; 1932889Sbinkertn@umich.edu 1942889Sbinkertn@umich.edu system->totalNumInsts++; 1952889Sbinkertn@umich.edu thread->funcExeInst++; 1962889Sbinkertn@umich.edu } 1972889Sbinkertn@umich.edu 1982889Sbinkertn@umich.edu virtual Counter totalInsts() const 1992889Sbinkertn@umich.edu { 2002889Sbinkertn@umich.edu return numInst - startNumInst; 2012889Sbinkertn@umich.edu } 2022889Sbinkertn@umich.edu 2032889Sbinkertn@umich.edu virtual Counter totalOps() const 2042889Sbinkertn@umich.edu { 2052889Sbinkertn@umich.edu return numOp - startNumOp; 2062889Sbinkertn@umich.edu } 2072889Sbinkertn@umich.edu 2082889Sbinkertn@umich.edu //number of integer alu accesses 2092889Sbinkertn@umich.edu Stats::Scalar numIntAluAccesses; 2102889Sbinkertn@umich.edu 2112889Sbinkertn@umich.edu //number of float alu accesses 2122889Sbinkertn@umich.edu Stats::Scalar numFpAluAccesses; 2132889Sbinkertn@umich.edu 2142889Sbinkertn@umich.edu //number of function calls/returns 2152889Sbinkertn@umich.edu Stats::Scalar numCallsReturns; 2162889Sbinkertn@umich.edu 2172889Sbinkertn@umich.edu //conditional control instructions; 2182889Sbinkertn@umich.edu Stats::Scalar numCondCtrlInsts; 2192889Sbinkertn@umich.edu 2202889Sbinkertn@umich.edu //number of int instructions 2212889Sbinkertn@umich.edu Stats::Scalar numIntInsts; 2222889Sbinkertn@umich.edu 2232889Sbinkertn@umich.edu //number of float instructions 2242889Sbinkertn@umich.edu Stats::Scalar numFpInsts; 2252889Sbinkertn@umich.edu 2262889Sbinkertn@umich.edu //number of integer register file accesses 2272889Sbinkertn@umich.edu Stats::Scalar numIntRegReads; 2282889Sbinkertn@umich.edu Stats::Scalar numIntRegWrites; 2292889Sbinkertn@umich.edu 2302889Sbinkertn@umich.edu //number of float register file accesses 2312889Sbinkertn@umich.edu Stats::Scalar numFpRegReads; 2322889Sbinkertn@umich.edu Stats::Scalar numFpRegWrites; 2332889Sbinkertn@umich.edu 2342889Sbinkertn@umich.edu // number of simulated memory references 2352889Sbinkertn@umich.edu Stats::Scalar numMemRefs; 2362889Sbinkertn@umich.edu Stats::Scalar numLoadInsts; 2372889Sbinkertn@umich.edu Stats::Scalar numStoreInsts; 2382889Sbinkertn@umich.edu 2392889Sbinkertn@umich.edu // number of idle cycles 2402889Sbinkertn@umich.edu Stats::Formula numIdleCycles; 2412889Sbinkertn@umich.edu 2422889Sbinkertn@umich.edu // number of busy cycles 2432889Sbinkertn@umich.edu Stats::Formula numBusyCycles; 2442889Sbinkertn@umich.edu 2452889Sbinkertn@umich.edu // number of simulated loads 2462889Sbinkertn@umich.edu Counter numLoad; 2472889Sbinkertn@umich.edu Counter startNumLoad; 2482889Sbinkertn@umich.edu 2492889Sbinkertn@umich.edu // number of idle cycles 2502889Sbinkertn@umich.edu Stats::Average notIdleFraction; 2512889Sbinkertn@umich.edu Stats::Formula idleFraction; 2522889Sbinkertn@umich.edu 2532889Sbinkertn@umich.edu // number of cycles stalled for I-cache responses 2542889Sbinkertn@umich.edu Stats::Scalar icacheStallCycles; 2552889Sbinkertn@umich.edu Counter lastIcacheStall; 2562889Sbinkertn@umich.edu 2572889Sbinkertn@umich.edu // number of cycles stalled for I-cache retries 2582889Sbinkertn@umich.edu Stats::Scalar icacheRetryCycles; 2592889Sbinkertn@umich.edu Counter lastIcacheRetry; 2602889Sbinkertn@umich.edu 2612889Sbinkertn@umich.edu // number of cycles stalled for D-cache responses 2622889Sbinkertn@umich.edu Stats::Scalar dcacheStallCycles; 2632889Sbinkertn@umich.edu Counter lastDcacheStall; 2642889Sbinkertn@umich.edu 2652889Sbinkertn@umich.edu // number of cycles stalled for D-cache retries 2662889Sbinkertn@umich.edu Stats::Scalar dcacheRetryCycles; 2672889Sbinkertn@umich.edu Counter lastDcacheRetry; 2682889Sbinkertn@umich.edu 2692889Sbinkertn@umich.edu void serializeThread(std::ostream &os, ThreadID tid); 2702889Sbinkertn@umich.edu void unserializeThread(Checkpoint *cp, const std::string §ion, 2712889Sbinkertn@umich.edu ThreadID tid); 2722889Sbinkertn@umich.edu 2732889Sbinkertn@umich.edu // These functions are only used in CPU models that split 2742889Sbinkertn@umich.edu // effective address computation from the actual memory access. 2752889Sbinkertn@umich.edu void setEA(Addr EA) { panic("BaseSimpleCPU::setEA() not implemented\n"); } 2762889Sbinkertn@umich.edu Addr getEA() { panic("BaseSimpleCPU::getEA() not implemented\n"); 2772889Sbinkertn@umich.edu M5_DUMMY_RETURN} 2782889Sbinkertn@umich.edu 2792889Sbinkertn@umich.edu // The register accessor methods provide the index of the 2802889Sbinkertn@umich.edu // instruction's operand (e.g., 0 or 1), not the architectural 2812889Sbinkertn@umich.edu // register index, to simplify the implementation of register 2822889Sbinkertn@umich.edu // renaming. We find the architectural register index by indexing 2832889Sbinkertn@umich.edu // into the instruction's own operand index table. Note that a 2842889Sbinkertn@umich.edu // raw pointer to the StaticInst is provided instead of a 2852889Sbinkertn@umich.edu // ref-counted StaticInstPtr to redice overhead. This is fine as 2862889Sbinkertn@umich.edu // long as these methods don't copy the pointer into any long-term 2872889Sbinkertn@umich.edu // storage (which is pretty hard to imagine they would have reason 2882889Sbinkertn@umich.edu // to do). 2892889Sbinkertn@umich.edu 2902889Sbinkertn@umich.edu uint64_t readIntRegOperand(const StaticInst *si, int idx) 2912889Sbinkertn@umich.edu { 2922889Sbinkertn@umich.edu numIntRegReads++; 2932889Sbinkertn@umich.edu return thread->readIntReg(si->srcRegIdx(idx)); 2942889Sbinkertn@umich.edu } 2952889Sbinkertn@umich.edu 2962889Sbinkertn@umich.edu FloatReg readFloatRegOperand(const StaticInst *si, int idx) 2972889Sbinkertn@umich.edu { 2982889Sbinkertn@umich.edu numFpRegReads++; 2992889Sbinkertn@umich.edu int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; 3002889Sbinkertn@umich.edu return thread->readFloatReg(reg_idx); 3012889Sbinkertn@umich.edu } 3022889Sbinkertn@umich.edu 3032889Sbinkertn@umich.edu FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx) 3042889Sbinkertn@umich.edu { 3052889Sbinkertn@umich.edu numFpRegReads++; 3062889Sbinkertn@umich.edu int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; 3072889Sbinkertn@umich.edu return thread->readFloatRegBits(reg_idx); 308 } 309 310 void setIntRegOperand(const StaticInst *si, int idx, uint64_t val) 311 { 312 numIntRegWrites++; 313 thread->setIntReg(si->destRegIdx(idx), val); 314 } 315 316 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val) 317 { 318 numFpRegWrites++; 319 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; 320 thread->setFloatReg(reg_idx, val); 321 } 322 323 void setFloatRegOperandBits(const StaticInst *si, int idx, 324 FloatRegBits val) 325 { 326 numFpRegWrites++; 327 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; 328 thread->setFloatRegBits(reg_idx, val); 329 } 330 331 bool readPredicate() { return thread->readPredicate(); } 332 void setPredicate(bool val) 333 { 334 thread->setPredicate(val); 335 if (traceData) { 336 traceData->setPredicate(val); 337 } 338 } 339 TheISA::PCState pcState() { return thread->pcState(); } 340 void pcState(const TheISA::PCState &val) { thread->pcState(val); } 341 Addr instAddr() { return thread->instAddr(); } 342 Addr nextInstAddr() { return thread->nextInstAddr(); } 343 MicroPC microPC() { return thread->microPC(); } 344 345 MiscReg readMiscRegNoEffect(int misc_reg) 346 { 347 return thread->readMiscRegNoEffect(misc_reg); 348 } 349 350 MiscReg readMiscReg(int misc_reg) 351 { 352 numIntRegReads++; 353 return thread->readMiscReg(misc_reg); 354 } 355 356 void setMiscReg(int misc_reg, const MiscReg &val) 357 { 358 numIntRegWrites++; 359 return thread->setMiscReg(misc_reg, val); 360 } 361 362 MiscReg readMiscRegOperand(const StaticInst *si, int idx) 363 { 364 numIntRegReads++; 365 int reg_idx = si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag; 366 return thread->readMiscReg(reg_idx); 367 } 368 369 void setMiscRegOperand( 370 const StaticInst *si, int idx, const MiscReg &val) 371 { 372 numIntRegWrites++; 373 int reg_idx = si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag; 374 return thread->setMiscReg(reg_idx, val); 375 } 376 377 void demapPage(Addr vaddr, uint64_t asn) 378 { 379 thread->demapPage(vaddr, asn); 380 } 381 382 void demapInstPage(Addr vaddr, uint64_t asn) 383 { 384 thread->demapInstPage(vaddr, asn); 385 } 386 387 void demapDataPage(Addr vaddr, uint64_t asn) 388 { 389 thread->demapDataPage(vaddr, asn); 390 } 391 392 unsigned readStCondFailures() { 393 return thread->readStCondFailures(); 394 } 395 396 void setStCondFailures(unsigned sc_failures) { 397 thread->setStCondFailures(sc_failures); 398 } 399 400 MiscReg readRegOtherThread(int regIdx, ThreadID tid = InvalidThreadID) 401 { 402 panic("Simple CPU models do not support multithreaded " 403 "register access.\n"); 404 } 405 406 void setRegOtherThread(int regIdx, const MiscReg &val, 407 ThreadID tid = InvalidThreadID) 408 { 409 panic("Simple CPU models do not support multithreaded " 410 "register access.\n"); 411 } 412 413 //Fault CacheOp(uint8_t Op, Addr EA); 414 415 Fault hwrei() { return thread->hwrei(); } 416 bool simPalCheck(int palFunc) { return thread->simPalCheck(palFunc); } 417 418 void 419 syscall(int64_t callnum) 420 { 421 if (FullSystem) 422 panic("Syscall emulation isn't available in FS mode.\n"); 423 424 thread->syscall(callnum); 425 } 426 427 bool misspeculating() { return thread->misspeculating(); } 428 ThreadContext *tcBase() { return tc; } 429}; 430 431#endif // __CPU_SIMPLE_BASE_HH__ 432