base.hh revision 9448
12SN/A/* 29448SAndreas.Sandberg@ARM.com * Copyright (c) 2011-2012 ARM Limited 38733Sgeoffrey.blake@arm.com * All rights reserved 48733Sgeoffrey.blake@arm.com * 58733Sgeoffrey.blake@arm.com * The license below extends only to copyright in the software and shall 68733Sgeoffrey.blake@arm.com * not be construed as granting a license to any other intellectual 78733Sgeoffrey.blake@arm.com * property including but not limited to intellectual property relating 88733Sgeoffrey.blake@arm.com * to a hardware implementation of the functionality of the software 98733Sgeoffrey.blake@arm.com * licensed hereunder. You may use the software subject to the license 108733Sgeoffrey.blake@arm.com * terms below provided that you ensure that this notice is replicated 118733Sgeoffrey.blake@arm.com * unmodified and in its entirety in all distributions of the software, 128733Sgeoffrey.blake@arm.com * modified or unmodified, in source code or in binary form. 138733Sgeoffrey.blake@arm.com * 141762SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 152SN/A * All rights reserved. 162SN/A * 172SN/A * Redistribution and use in source and binary forms, with or without 182SN/A * modification, are permitted provided that the following conditions are 192SN/A * met: redistributions of source code must retain the above copyright 202SN/A * notice, this list of conditions and the following disclaimer; 212SN/A * redistributions in binary form must reproduce the above copyright 222SN/A * notice, this list of conditions and the following disclaimer in the 232SN/A * documentation and/or other materials provided with the distribution; 242SN/A * neither the name of the copyright holders nor the names of its 252SN/A * contributors may be used to endorse or promote products derived from 262SN/A * this software without specific prior written permission. 272SN/A * 282SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392665Ssaidi@eecs.umich.edu * 402665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 412665Ssaidi@eecs.umich.edu * Dave Greene 422665Ssaidi@eecs.umich.edu * Nathan Binkert 432SN/A */ 442SN/A 452623SN/A#ifndef __CPU_SIMPLE_BASE_HH__ 462623SN/A#define __CPU_SIMPLE_BASE_HH__ 472SN/A 481354SN/A#include "base/statistics.hh" 496658Snate@binkert.org#include "config/the_isa.hh" 501717SN/A#include "cpu/base.hh" 518887Sgeoffrey.blake@arm.com#include "cpu/checker/cpu.hh" 528229Snate@binkert.org#include "cpu/pc_event.hh" 532683Sktlim@umich.edu#include "cpu/simple_thread.hh" 541354SN/A#include "cpu/static_inst.hh" 552387SN/A#include "mem/packet.hh" 562387SN/A#include "mem/port.hh" 572387SN/A#include "mem/request.hh" 5856SN/A#include "sim/eventq.hh" 598779Sgblack@eecs.umich.edu#include "sim/full_system.hh" 605348Ssaidi@eecs.umich.edu#include "sim/system.hh" 612SN/A 622SN/A// forward declarations 638779Sgblack@eecs.umich.educlass Checkpoint; 648779Sgblack@eecs.umich.educlass Process; 652SN/Aclass Processor; 668779Sgblack@eecs.umich.educlass ThreadContext; 672SN/A 684182Sgblack@eecs.umich.edunamespace TheISA 694182Sgblack@eecs.umich.edu{ 708779Sgblack@eecs.umich.edu class DTB; 718779Sgblack@eecs.umich.edu class ITB; 724182Sgblack@eecs.umich.edu} 732SN/A 742SN/Anamespace Trace { 752SN/A class InstRecord; 762SN/A} 772SN/A 788737Skoansin.tan@gmail.comstruct BaseSimpleCPUParams; 795529Snate@binkert.org 802420SN/A 812623SN/Aclass BaseSimpleCPU : public BaseCPU 822SN/A{ 832107SN/A protected: 842159SN/A typedef TheISA::MiscReg MiscReg; 852455SN/A typedef TheISA::FloatReg FloatReg; 862455SN/A typedef TheISA::FloatRegBits FloatRegBits; 872386SN/A 882623SN/A protected: 892SN/A Trace::InstRecord *traceData; 901371SN/A 915348Ssaidi@eecs.umich.edu inline void checkPcEventQueue() { 927720Sgblack@eecs.umich.edu Addr oldpc, pc = thread->instAddr(); 935348Ssaidi@eecs.umich.edu do { 947720Sgblack@eecs.umich.edu oldpc = pc; 955348Ssaidi@eecs.umich.edu system->pcEventQueue.service(tc); 967720Sgblack@eecs.umich.edu pc = thread->instAddr(); 977720Sgblack@eecs.umich.edu } while (oldpc != pc); 985348Ssaidi@eecs.umich.edu } 995348Ssaidi@eecs.umich.edu 1002SN/A public: 1015807Snate@binkert.org void wakeup(); 1022SN/A 1032SN/A void zero_fill_64(Addr addr) { 1042SN/A static int warned = 0; 1052SN/A if (!warned) { 1062SN/A warn ("WH64 is not implemented"); 1072SN/A warned = 1; 1082SN/A } 1092SN/A }; 1102SN/A 1111400SN/A public: 1125529Snate@binkert.org BaseSimpleCPU(BaseSimpleCPUParams *params); 1132623SN/A virtual ~BaseSimpleCPU(); 1142SN/A 1151400SN/A public: 1162683Sktlim@umich.edu /** SimpleThread object, provides all the architectural state. */ 1172683Sktlim@umich.edu SimpleThread *thread; 1182190SN/A 1192683Sktlim@umich.edu /** ThreadContext object, provides an interface for external 1202683Sktlim@umich.edu * objects to modify this thread's state. 1212683Sktlim@umich.edu */ 1222680Sktlim@umich.edu ThreadContext *tc; 1238733Sgeoffrey.blake@arm.com 1248733Sgeoffrey.blake@arm.com CheckerCPU *checker; 1258887Sgeoffrey.blake@arm.com 1265169Ssaidi@eecs.umich.edu protected: 1275169Ssaidi@eecs.umich.edu 1285496Ssaidi@eecs.umich.edu enum Status { 1295496Ssaidi@eecs.umich.edu Idle, 1305496Ssaidi@eecs.umich.edu Running, 1318276SAli.Saidi@ARM.com Faulting, 1325894Sgblack@eecs.umich.edu ITBWaitResponse, 1335496Ssaidi@eecs.umich.edu IcacheRetry, 1345496Ssaidi@eecs.umich.edu IcacheWaitResponse, 1355496Ssaidi@eecs.umich.edu IcacheWaitSwitch, 1365894Sgblack@eecs.umich.edu DTBWaitResponse, 1375496Ssaidi@eecs.umich.edu DcacheRetry, 1385496Ssaidi@eecs.umich.edu DcacheWaitResponse, 1395496Ssaidi@eecs.umich.edu DcacheWaitSwitch, 1405496Ssaidi@eecs.umich.edu }; 1415496Ssaidi@eecs.umich.edu 1425496Ssaidi@eecs.umich.edu Status _status; 1435496Ssaidi@eecs.umich.edu 1445169Ssaidi@eecs.umich.edu public: 1452SN/A 1462SN/A Addr dbg_vtophys(Addr addr); 1472SN/A 1482SN/A bool interval_stats; 1492SN/A 1502SN/A // current instruction 1514181Sgblack@eecs.umich.edu TheISA::MachInst inst; 1524181Sgblack@eecs.umich.edu 1532107SN/A StaticInstPtr curStaticInst; 1543276Sgblack@eecs.umich.edu StaticInstPtr curMacroStaticInst; 1551469SN/A 1564377Sgblack@eecs.umich.edu //This is the offset from the current pc that fetch should be performed at 1574377Sgblack@eecs.umich.edu Addr fetchOffset; 1584377Sgblack@eecs.umich.edu //This flag says to stay at the current pc. This is useful for 1594377Sgblack@eecs.umich.edu //instructions which go beyond MachInst boundaries. 1604377Sgblack@eecs.umich.edu bool stayAtPC; 1614377Sgblack@eecs.umich.edu 1622623SN/A void checkForInterrupts(); 1635894Sgblack@eecs.umich.edu void setupFetchRequest(Request *req); 1642623SN/A void preExecute(); 1652623SN/A void postExecute(); 1662623SN/A void advancePC(Fault fault); 167180SN/A 1688737Skoansin.tan@gmail.com virtual void deallocateContext(ThreadID thread_num); 1698737Skoansin.tan@gmail.com virtual void haltContext(ThreadID thread_num); 1702SN/A 1712SN/A // statistics 172334SN/A virtual void regStats(); 173334SN/A virtual void resetStats(); 1742SN/A 1752SN/A // number of simulated instructions 1762SN/A Counter numInst; 177334SN/A Counter startNumInst; 1785999Snate@binkert.org Stats::Scalar numInsts; 1798834Satgutier@umich.edu Counter numOp; 1808834Satgutier@umich.edu Counter startNumOp; 1818834Satgutier@umich.edu Stats::Scalar numOps; 182707SN/A 1834998Sgblack@eecs.umich.edu void countInst() 1844998Sgblack@eecs.umich.edu { 1858834Satgutier@umich.edu if (!curStaticInst->isMicroop() || curStaticInst->isLastMicroop()) { 1868834Satgutier@umich.edu numInst++; 1878834Satgutier@umich.edu numInsts++; 1888834Satgutier@umich.edu } 1898834Satgutier@umich.edu numOp++; 1908834Satgutier@umich.edu numOps++; 1918834Satgutier@umich.edu 1927897Shestness@cs.utexas.edu system->totalNumInsts++; 1934998Sgblack@eecs.umich.edu thread->funcExeInst++; 1944998Sgblack@eecs.umich.edu } 1954998Sgblack@eecs.umich.edu 1968834Satgutier@umich.edu virtual Counter totalInsts() const 197707SN/A { 198707SN/A return numInst - startNumInst; 199707SN/A } 2002SN/A 2018834Satgutier@umich.edu virtual Counter totalOps() const 2028834Satgutier@umich.edu { 2038834Satgutier@umich.edu return numOp - startNumOp; 2048834Satgutier@umich.edu } 2058834Satgutier@umich.edu 2067897Shestness@cs.utexas.edu //number of integer alu accesses 2077897Shestness@cs.utexas.edu Stats::Scalar numIntAluAccesses; 2087897Shestness@cs.utexas.edu 2097897Shestness@cs.utexas.edu //number of float alu accesses 2107897Shestness@cs.utexas.edu Stats::Scalar numFpAluAccesses; 2117897Shestness@cs.utexas.edu 2127897Shestness@cs.utexas.edu //number of function calls/returns 2137897Shestness@cs.utexas.edu Stats::Scalar numCallsReturns; 2147897Shestness@cs.utexas.edu 2157897Shestness@cs.utexas.edu //conditional control instructions; 2167897Shestness@cs.utexas.edu Stats::Scalar numCondCtrlInsts; 2177897Shestness@cs.utexas.edu 2187897Shestness@cs.utexas.edu //number of int instructions 2197897Shestness@cs.utexas.edu Stats::Scalar numIntInsts; 2207897Shestness@cs.utexas.edu 2217897Shestness@cs.utexas.edu //number of float instructions 2227897Shestness@cs.utexas.edu Stats::Scalar numFpInsts; 2237897Shestness@cs.utexas.edu 2247897Shestness@cs.utexas.edu //number of integer register file accesses 2257897Shestness@cs.utexas.edu Stats::Scalar numIntRegReads; 2267897Shestness@cs.utexas.edu Stats::Scalar numIntRegWrites; 2277897Shestness@cs.utexas.edu 2287897Shestness@cs.utexas.edu //number of float register file accesses 2297897Shestness@cs.utexas.edu Stats::Scalar numFpRegReads; 2307897Shestness@cs.utexas.edu Stats::Scalar numFpRegWrites; 2317897Shestness@cs.utexas.edu 2322SN/A // number of simulated memory references 2335999Snate@binkert.org Stats::Scalar numMemRefs; 2347897Shestness@cs.utexas.edu Stats::Scalar numLoadInsts; 2357897Shestness@cs.utexas.edu Stats::Scalar numStoreInsts; 2367897Shestness@cs.utexas.edu 2377897Shestness@cs.utexas.edu // number of idle cycles 2387897Shestness@cs.utexas.edu Stats::Formula numIdleCycles; 2397897Shestness@cs.utexas.edu 2407897Shestness@cs.utexas.edu // number of busy cycles 2417897Shestness@cs.utexas.edu Stats::Formula numBusyCycles; 2422SN/A 243124SN/A // number of simulated loads 244124SN/A Counter numLoad; 245334SN/A Counter startNumLoad; 246124SN/A 2472SN/A // number of idle cycles 2485999Snate@binkert.org Stats::Average notIdleFraction; 249729SN/A Stats::Formula idleFraction; 2502SN/A 2512390SN/A // number of cycles stalled for I-cache responses 2525999Snate@binkert.org Stats::Scalar icacheStallCycles; 2532SN/A Counter lastIcacheStall; 2542SN/A 2552390SN/A // number of cycles stalled for I-cache retries 2565999Snate@binkert.org Stats::Scalar icacheRetryCycles; 2572390SN/A Counter lastIcacheRetry; 2582390SN/A 2592390SN/A // number of cycles stalled for D-cache responses 2605999Snate@binkert.org Stats::Scalar dcacheStallCycles; 2612SN/A Counter lastDcacheStall; 2622SN/A 2632390SN/A // number of cycles stalled for D-cache retries 2645999Snate@binkert.org Stats::Scalar dcacheRetryCycles; 2652390SN/A Counter lastDcacheRetry; 2662390SN/A 2679448SAndreas.Sandberg@ARM.com void serializeThread(std::ostream &os, ThreadID tid); 2689448SAndreas.Sandberg@ARM.com void unserializeThread(Checkpoint *cp, const std::string §ion, 2699448SAndreas.Sandberg@ARM.com ThreadID tid); 2702SN/A 2711371SN/A // These functions are only used in CPU models that split 2721371SN/A // effective address computation from the actual memory access. 2732623SN/A void setEA(Addr EA) { panic("BaseSimpleCPU::setEA() not implemented\n"); } 2745543Ssaidi@eecs.umich.edu Addr getEA() { panic("BaseSimpleCPU::getEA() not implemented\n"); 2753918Ssaidi@eecs.umich.edu M5_DUMMY_RETURN} 2761371SN/A 277726SN/A // The register accessor methods provide the index of the 278726SN/A // instruction's operand (e.g., 0 or 1), not the architectural 279726SN/A // register index, to simplify the implementation of register 280726SN/A // renaming. We find the architectural register index by indexing 281726SN/A // into the instruction's own operand index table. Note that a 282726SN/A // raw pointer to the StaticInst is provided instead of a 283726SN/A // ref-counted StaticInstPtr to redice overhead. This is fine as 284726SN/A // long as these methods don't copy the pointer into any long-term 285726SN/A // storage (which is pretty hard to imagine they would have reason 286726SN/A // to do). 287705SN/A 2883735Sstever@eecs.umich.edu uint64_t readIntRegOperand(const StaticInst *si, int idx) 289726SN/A { 2907897Shestness@cs.utexas.edu numIntRegReads++; 2912683Sktlim@umich.edu return thread->readIntReg(si->srcRegIdx(idx)); 292726SN/A } 293705SN/A 2943735Sstever@eecs.umich.edu FloatReg readFloatRegOperand(const StaticInst *si, int idx) 295726SN/A { 2967897Shestness@cs.utexas.edu numFpRegReads++; 297726SN/A int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; 2982683Sktlim@umich.edu return thread->readFloatReg(reg_idx); 299726SN/A } 300705SN/A 3013735Sstever@eecs.umich.edu FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx) 3022455SN/A { 3037897Shestness@cs.utexas.edu numFpRegReads++; 3042455SN/A int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; 3052683Sktlim@umich.edu return thread->readFloatRegBits(reg_idx); 306726SN/A } 307705SN/A 3083735Sstever@eecs.umich.edu void setIntRegOperand(const StaticInst *si, int idx, uint64_t val) 309726SN/A { 3107897Shestness@cs.utexas.edu numIntRegWrites++; 3112683Sktlim@umich.edu thread->setIntReg(si->destRegIdx(idx), val); 312726SN/A } 313705SN/A 3143735Sstever@eecs.umich.edu void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val) 315726SN/A { 3167897Shestness@cs.utexas.edu numFpRegWrites++; 317726SN/A int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; 3182683Sktlim@umich.edu thread->setFloatReg(reg_idx, val); 319726SN/A } 320726SN/A 3213735Sstever@eecs.umich.edu void setFloatRegOperandBits(const StaticInst *si, int idx, 3223735Sstever@eecs.umich.edu FloatRegBits val) 3232455SN/A { 3247897Shestness@cs.utexas.edu numFpRegWrites++; 3252455SN/A int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; 3262683Sktlim@umich.edu thread->setFloatRegBits(reg_idx, val); 327726SN/A } 328705SN/A 3297597Sminkyu.jeong@arm.com bool readPredicate() { return thread->readPredicate(); } 3307597Sminkyu.jeong@arm.com void setPredicate(bool val) 3317600Sminkyu.jeong@arm.com { 3327600Sminkyu.jeong@arm.com thread->setPredicate(val); 3337600Sminkyu.jeong@arm.com if (traceData) { 3347600Sminkyu.jeong@arm.com traceData->setPredicate(val); 3357600Sminkyu.jeong@arm.com } 3367600Sminkyu.jeong@arm.com } 3377720Sgblack@eecs.umich.edu TheISA::PCState pcState() { return thread->pcState(); } 3387720Sgblack@eecs.umich.edu void pcState(const TheISA::PCState &val) { thread->pcState(val); } 3397720Sgblack@eecs.umich.edu Addr instAddr() { return thread->instAddr(); } 3407720Sgblack@eecs.umich.edu Addr nextInstAddr() { return thread->nextInstAddr(); } 3417720Sgblack@eecs.umich.edu MicroPC microPC() { return thread->microPC(); } 342705SN/A 3434172Ssaidi@eecs.umich.edu MiscReg readMiscRegNoEffect(int misc_reg) 3444172Ssaidi@eecs.umich.edu { 3454172Ssaidi@eecs.umich.edu return thread->readMiscRegNoEffect(misc_reg); 3464172Ssaidi@eecs.umich.edu } 3474172Ssaidi@eecs.umich.edu 3482159SN/A MiscReg readMiscReg(int misc_reg) 3492159SN/A { 3507897Shestness@cs.utexas.edu numIntRegReads++; 3512683Sktlim@umich.edu return thread->readMiscReg(misc_reg); 3522159SN/A } 353705SN/A 3543468Sgblack@eecs.umich.edu void setMiscReg(int misc_reg, const MiscReg &val) 3552159SN/A { 3567897Shestness@cs.utexas.edu numIntRegWrites++; 3572683Sktlim@umich.edu return thread->setMiscReg(misc_reg, val); 3582159SN/A } 3592159SN/A 3604185Ssaidi@eecs.umich.edu MiscReg readMiscRegOperand(const StaticInst *si, int idx) 3613792Sgblack@eecs.umich.edu { 3627897Shestness@cs.utexas.edu numIntRegReads++; 3633792Sgblack@eecs.umich.edu int reg_idx = si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag; 3643792Sgblack@eecs.umich.edu return thread->readMiscReg(reg_idx); 3653792Sgblack@eecs.umich.edu } 3663792Sgblack@eecs.umich.edu 3674185Ssaidi@eecs.umich.edu void setMiscRegOperand( 3683792Sgblack@eecs.umich.edu const StaticInst *si, int idx, const MiscReg &val) 3693792Sgblack@eecs.umich.edu { 3707897Shestness@cs.utexas.edu numIntRegWrites++; 3713792Sgblack@eecs.umich.edu int reg_idx = si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag; 3724172Ssaidi@eecs.umich.edu return thread->setMiscReg(reg_idx, val); 3733792Sgblack@eecs.umich.edu } 3743792Sgblack@eecs.umich.edu 3755358Sgblack@eecs.umich.edu void demapPage(Addr vaddr, uint64_t asn) 3765358Sgblack@eecs.umich.edu { 3775358Sgblack@eecs.umich.edu thread->demapPage(vaddr, asn); 3785358Sgblack@eecs.umich.edu } 3795358Sgblack@eecs.umich.edu 3805358Sgblack@eecs.umich.edu void demapInstPage(Addr vaddr, uint64_t asn) 3815358Sgblack@eecs.umich.edu { 3825358Sgblack@eecs.umich.edu thread->demapInstPage(vaddr, asn); 3835358Sgblack@eecs.umich.edu } 3845358Sgblack@eecs.umich.edu 3855358Sgblack@eecs.umich.edu void demapDataPage(Addr vaddr, uint64_t asn) 3865358Sgblack@eecs.umich.edu { 3875358Sgblack@eecs.umich.edu thread->demapDataPage(vaddr, asn); 3885358Sgblack@eecs.umich.edu } 3895358Sgblack@eecs.umich.edu 3904027Sstever@eecs.umich.edu unsigned readStCondFailures() { 3914027Sstever@eecs.umich.edu return thread->readStCondFailures(); 3924027Sstever@eecs.umich.edu } 3934027Sstever@eecs.umich.edu 3944027Sstever@eecs.umich.edu void setStCondFailures(unsigned sc_failures) { 3954027Sstever@eecs.umich.edu thread->setStCondFailures(sc_failures); 3964027Sstever@eecs.umich.edu } 3974027Sstever@eecs.umich.edu 3986221Snate@binkert.org MiscReg readRegOtherThread(int regIdx, ThreadID tid = InvalidThreadID) 3994661Sksewell@umich.edu { 4004661Sksewell@umich.edu panic("Simple CPU models do not support multithreaded " 4014661Sksewell@umich.edu "register access.\n"); 4024661Sksewell@umich.edu } 4034661Sksewell@umich.edu 4046221Snate@binkert.org void setRegOtherThread(int regIdx, const MiscReg &val, 4056221Snate@binkert.org ThreadID tid = InvalidThreadID) 4064661Sksewell@umich.edu { 4074661Sksewell@umich.edu panic("Simple CPU models do not support multithreaded " 4084661Sksewell@umich.edu "register access.\n"); 4094661Sksewell@umich.edu } 4104661Sksewell@umich.edu 4115250Sksewell@umich.edu //Fault CacheOp(uint8_t Op, Addr EA); 4125222Sksewell@umich.edu 4135702Ssaidi@eecs.umich.edu Fault hwrei() { return thread->hwrei(); } 4145702Ssaidi@eecs.umich.edu bool simPalCheck(int palFunc) { return thread->simPalCheck(palFunc); } 4158557Sgblack@eecs.umich.edu 4168557Sgblack@eecs.umich.edu void 4178557Sgblack@eecs.umich.edu syscall(int64_t callnum) 4188557Sgblack@eecs.umich.edu { 4198779Sgblack@eecs.umich.edu if (FullSystem) 4208779Sgblack@eecs.umich.edu panic("Syscall emulation isn't available in FS mode.\n"); 4218806Sgblack@eecs.umich.edu 4228557Sgblack@eecs.umich.edu thread->syscall(callnum); 4238557Sgblack@eecs.umich.edu } 424705SN/A 4252683Sktlim@umich.edu bool misspeculating() { return thread->misspeculating(); } 4262680Sktlim@umich.edu ThreadContext *tcBase() { return tc; } 4272SN/A}; 4282SN/A 4292623SN/A#endif // __CPU_SIMPLE_BASE_HH__ 430