base.hh revision 8276
12SN/A/* 21762SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 292665Ssaidi@eecs.umich.edu * Dave Greene 302665Ssaidi@eecs.umich.edu * Nathan Binkert 312SN/A */ 322SN/A 332623SN/A#ifndef __CPU_SIMPLE_BASE_HH__ 342623SN/A#define __CPU_SIMPLE_BASE_HH__ 352SN/A 364182Sgblack@eecs.umich.edu#include "arch/predecoder.hh" 371354SN/A#include "base/statistics.hh" 381858SN/A#include "config/full_system.hh" 396658Snate@binkert.org#include "config/the_isa.hh" 401717SN/A#include "cpu/base.hh" 418229Snate@binkert.org#include "cpu/pc_event.hh" 422683Sktlim@umich.edu#include "cpu/simple_thread.hh" 431354SN/A#include "cpu/static_inst.hh" 442387SN/A#include "mem/packet.hh" 452387SN/A#include "mem/port.hh" 462387SN/A#include "mem/request.hh" 4756SN/A#include "sim/eventq.hh" 485348Ssaidi@eecs.umich.edu#include "sim/system.hh" 492SN/A 502SN/A// forward declarations 511858SN/A#if FULL_SYSTEM 522SN/Aclass Processor; 533453Sgblack@eecs.umich.edunamespace TheISA 543453Sgblack@eecs.umich.edu{ 553453Sgblack@eecs.umich.edu class ITB; 563453Sgblack@eecs.umich.edu class DTB; 573453Sgblack@eecs.umich.edu} 582462SN/Aclass MemObject; 592SN/A 60715SN/A#else 61715SN/A 62715SN/Aclass Process; 63715SN/A 642SN/A#endif // FULL_SYSTEM 652SN/A 664182Sgblack@eecs.umich.edunamespace TheISA 674182Sgblack@eecs.umich.edu{ 684182Sgblack@eecs.umich.edu class Predecoder; 694182Sgblack@eecs.umich.edu} 702680Sktlim@umich.educlass ThreadContext; 71237SN/Aclass Checkpoint; 722SN/A 732SN/Anamespace Trace { 742SN/A class InstRecord; 752SN/A} 762SN/A 775529Snate@binkert.orgclass BaseSimpleCPUParams; 785529Snate@binkert.org 792420SN/A 802623SN/Aclass BaseSimpleCPU : public BaseCPU 812SN/A{ 822107SN/A protected: 832159SN/A typedef TheISA::MiscReg MiscReg; 842455SN/A typedef TheISA::FloatReg FloatReg; 852455SN/A typedef TheISA::FloatRegBits FloatRegBits; 862386SN/A 872623SN/A protected: 882SN/A Trace::InstRecord *traceData; 891371SN/A 905348Ssaidi@eecs.umich.edu inline void checkPcEventQueue() { 917720Sgblack@eecs.umich.edu Addr oldpc, pc = thread->instAddr(); 925348Ssaidi@eecs.umich.edu do { 937720Sgblack@eecs.umich.edu oldpc = pc; 945348Ssaidi@eecs.umich.edu system->pcEventQueue.service(tc); 957720Sgblack@eecs.umich.edu pc = thread->instAddr(); 967720Sgblack@eecs.umich.edu } while (oldpc != pc); 975348Ssaidi@eecs.umich.edu } 985348Ssaidi@eecs.umich.edu 992SN/A public: 1005807Snate@binkert.org void wakeup(); 1012SN/A 1022SN/A void zero_fill_64(Addr addr) { 1032SN/A static int warned = 0; 1042SN/A if (!warned) { 1052SN/A warn ("WH64 is not implemented"); 1062SN/A warned = 1; 1072SN/A } 1082SN/A }; 1092SN/A 1101400SN/A public: 1115529Snate@binkert.org BaseSimpleCPU(BaseSimpleCPUParams *params); 1122623SN/A virtual ~BaseSimpleCPU(); 1132SN/A 1141400SN/A public: 1152683Sktlim@umich.edu /** SimpleThread object, provides all the architectural state. */ 1162683Sktlim@umich.edu SimpleThread *thread; 1172190SN/A 1182683Sktlim@umich.edu /** ThreadContext object, provides an interface for external 1192683Sktlim@umich.edu * objects to modify this thread's state. 1202683Sktlim@umich.edu */ 1212680Sktlim@umich.edu ThreadContext *tc; 1225169Ssaidi@eecs.umich.edu protected: 1235169Ssaidi@eecs.umich.edu 1245496Ssaidi@eecs.umich.edu enum Status { 1255496Ssaidi@eecs.umich.edu Idle, 1265496Ssaidi@eecs.umich.edu Running, 1278276SAli.Saidi@ARM.com Faulting, 1285894Sgblack@eecs.umich.edu ITBWaitResponse, 1295496Ssaidi@eecs.umich.edu IcacheRetry, 1305496Ssaidi@eecs.umich.edu IcacheWaitResponse, 1315496Ssaidi@eecs.umich.edu IcacheWaitSwitch, 1325894Sgblack@eecs.umich.edu DTBWaitResponse, 1335496Ssaidi@eecs.umich.edu DcacheRetry, 1345496Ssaidi@eecs.umich.edu DcacheWaitResponse, 1355496Ssaidi@eecs.umich.edu DcacheWaitSwitch, 1365496Ssaidi@eecs.umich.edu SwitchedOut 1375496Ssaidi@eecs.umich.edu }; 1385496Ssaidi@eecs.umich.edu 1395496Ssaidi@eecs.umich.edu Status _status; 1405496Ssaidi@eecs.umich.edu 1415169Ssaidi@eecs.umich.edu public: 1422SN/A 1431858SN/A#if FULL_SYSTEM 1442SN/A Addr dbg_vtophys(Addr addr); 1452SN/A 1462SN/A bool interval_stats; 1472SN/A#endif 1482SN/A 1492SN/A // current instruction 1504181Sgblack@eecs.umich.edu TheISA::MachInst inst; 1514181Sgblack@eecs.umich.edu 1524182Sgblack@eecs.umich.edu // The predecoder 1534182Sgblack@eecs.umich.edu TheISA::Predecoder predecoder; 1542SN/A 1552107SN/A StaticInstPtr curStaticInst; 1563276Sgblack@eecs.umich.edu StaticInstPtr curMacroStaticInst; 1571469SN/A 1584377Sgblack@eecs.umich.edu //This is the offset from the current pc that fetch should be performed at 1594377Sgblack@eecs.umich.edu Addr fetchOffset; 1604377Sgblack@eecs.umich.edu //This flag says to stay at the current pc. This is useful for 1614377Sgblack@eecs.umich.edu //instructions which go beyond MachInst boundaries. 1624377Sgblack@eecs.umich.edu bool stayAtPC; 1634377Sgblack@eecs.umich.edu 1642623SN/A void checkForInterrupts(); 1655894Sgblack@eecs.umich.edu void setupFetchRequest(Request *req); 1662623SN/A void preExecute(); 1672623SN/A void postExecute(); 1682623SN/A void advancePC(Fault fault); 169180SN/A 170393SN/A virtual void deallocateContext(int thread_num); 171393SN/A virtual void haltContext(int thread_num); 1722SN/A 1732SN/A // statistics 174334SN/A virtual void regStats(); 175334SN/A virtual void resetStats(); 1762SN/A 1772SN/A // number of simulated instructions 1782SN/A Counter numInst; 179334SN/A Counter startNumInst; 1805999Snate@binkert.org Stats::Scalar numInsts; 181707SN/A 1824998Sgblack@eecs.umich.edu void countInst() 1834998Sgblack@eecs.umich.edu { 1844998Sgblack@eecs.umich.edu numInst++; 1854998Sgblack@eecs.umich.edu numInsts++; 1867897Shestness@cs.utexas.edu system->totalNumInsts++; 1874998Sgblack@eecs.umich.edu thread->funcExeInst++; 1884998Sgblack@eecs.umich.edu } 1894998Sgblack@eecs.umich.edu 190707SN/A virtual Counter totalInstructions() const 191707SN/A { 192707SN/A return numInst - startNumInst; 193707SN/A } 1942SN/A 1957897Shestness@cs.utexas.edu //number of integer alu accesses 1967897Shestness@cs.utexas.edu Stats::Scalar numIntAluAccesses; 1977897Shestness@cs.utexas.edu 1987897Shestness@cs.utexas.edu //number of float alu accesses 1997897Shestness@cs.utexas.edu Stats::Scalar numFpAluAccesses; 2007897Shestness@cs.utexas.edu 2017897Shestness@cs.utexas.edu //number of function calls/returns 2027897Shestness@cs.utexas.edu Stats::Scalar numCallsReturns; 2037897Shestness@cs.utexas.edu 2047897Shestness@cs.utexas.edu //conditional control instructions; 2057897Shestness@cs.utexas.edu Stats::Scalar numCondCtrlInsts; 2067897Shestness@cs.utexas.edu 2077897Shestness@cs.utexas.edu //number of int instructions 2087897Shestness@cs.utexas.edu Stats::Scalar numIntInsts; 2097897Shestness@cs.utexas.edu 2107897Shestness@cs.utexas.edu //number of float instructions 2117897Shestness@cs.utexas.edu Stats::Scalar numFpInsts; 2127897Shestness@cs.utexas.edu 2137897Shestness@cs.utexas.edu //number of integer register file accesses 2147897Shestness@cs.utexas.edu Stats::Scalar numIntRegReads; 2157897Shestness@cs.utexas.edu Stats::Scalar numIntRegWrites; 2167897Shestness@cs.utexas.edu 2177897Shestness@cs.utexas.edu //number of float register file accesses 2187897Shestness@cs.utexas.edu Stats::Scalar numFpRegReads; 2197897Shestness@cs.utexas.edu Stats::Scalar numFpRegWrites; 2207897Shestness@cs.utexas.edu 2212SN/A // number of simulated memory references 2225999Snate@binkert.org Stats::Scalar numMemRefs; 2237897Shestness@cs.utexas.edu Stats::Scalar numLoadInsts; 2247897Shestness@cs.utexas.edu Stats::Scalar numStoreInsts; 2257897Shestness@cs.utexas.edu 2267897Shestness@cs.utexas.edu // number of idle cycles 2277897Shestness@cs.utexas.edu Stats::Formula numIdleCycles; 2287897Shestness@cs.utexas.edu 2297897Shestness@cs.utexas.edu // number of busy cycles 2307897Shestness@cs.utexas.edu Stats::Formula numBusyCycles; 2312SN/A 232124SN/A // number of simulated loads 233124SN/A Counter numLoad; 234334SN/A Counter startNumLoad; 235124SN/A 2362SN/A // number of idle cycles 2375999Snate@binkert.org Stats::Average notIdleFraction; 238729SN/A Stats::Formula idleFraction; 2392SN/A 2402390SN/A // number of cycles stalled for I-cache responses 2415999Snate@binkert.org Stats::Scalar icacheStallCycles; 2422SN/A Counter lastIcacheStall; 2432SN/A 2442390SN/A // number of cycles stalled for I-cache retries 2455999Snate@binkert.org Stats::Scalar icacheRetryCycles; 2462390SN/A Counter lastIcacheRetry; 2472390SN/A 2482390SN/A // number of cycles stalled for D-cache responses 2495999Snate@binkert.org Stats::Scalar dcacheStallCycles; 2502SN/A Counter lastDcacheStall; 2512SN/A 2522390SN/A // number of cycles stalled for D-cache retries 2535999Snate@binkert.org Stats::Scalar dcacheRetryCycles; 2542390SN/A Counter lastDcacheRetry; 2552390SN/A 256217SN/A virtual void serialize(std::ostream &os); 257237SN/A virtual void unserialize(Checkpoint *cp, const std::string §ion); 2582SN/A 2591371SN/A // These functions are only used in CPU models that split 2601371SN/A // effective address computation from the actual memory access. 2612623SN/A void setEA(Addr EA) { panic("BaseSimpleCPU::setEA() not implemented\n"); } 2625543Ssaidi@eecs.umich.edu Addr getEA() { panic("BaseSimpleCPU::getEA() not implemented\n"); 2633918Ssaidi@eecs.umich.edu M5_DUMMY_RETURN} 2641371SN/A 265726SN/A // The register accessor methods provide the index of the 266726SN/A // instruction's operand (e.g., 0 or 1), not the architectural 267726SN/A // register index, to simplify the implementation of register 268726SN/A // renaming. We find the architectural register index by indexing 269726SN/A // into the instruction's own operand index table. Note that a 270726SN/A // raw pointer to the StaticInst is provided instead of a 271726SN/A // ref-counted StaticInstPtr to redice overhead. This is fine as 272726SN/A // long as these methods don't copy the pointer into any long-term 273726SN/A // storage (which is pretty hard to imagine they would have reason 274726SN/A // to do). 275705SN/A 2763735Sstever@eecs.umich.edu uint64_t readIntRegOperand(const StaticInst *si, int idx) 277726SN/A { 2787897Shestness@cs.utexas.edu numIntRegReads++; 2792683Sktlim@umich.edu return thread->readIntReg(si->srcRegIdx(idx)); 280726SN/A } 281705SN/A 2823735Sstever@eecs.umich.edu FloatReg readFloatRegOperand(const StaticInst *si, int idx) 283726SN/A { 2847897Shestness@cs.utexas.edu numFpRegReads++; 285726SN/A int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; 2862683Sktlim@umich.edu return thread->readFloatReg(reg_idx); 287726SN/A } 288705SN/A 2893735Sstever@eecs.umich.edu FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx) 2902455SN/A { 2917897Shestness@cs.utexas.edu numFpRegReads++; 2922455SN/A int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; 2932683Sktlim@umich.edu return thread->readFloatRegBits(reg_idx); 294726SN/A } 295705SN/A 2963735Sstever@eecs.umich.edu void setIntRegOperand(const StaticInst *si, int idx, uint64_t val) 297726SN/A { 2987897Shestness@cs.utexas.edu numIntRegWrites++; 2992683Sktlim@umich.edu thread->setIntReg(si->destRegIdx(idx), val); 300726SN/A } 301705SN/A 3023735Sstever@eecs.umich.edu void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val) 303726SN/A { 3047897Shestness@cs.utexas.edu numFpRegWrites++; 305726SN/A int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; 3062683Sktlim@umich.edu thread->setFloatReg(reg_idx, val); 307726SN/A } 308726SN/A 3093735Sstever@eecs.umich.edu void setFloatRegOperandBits(const StaticInst *si, int idx, 3103735Sstever@eecs.umich.edu FloatRegBits val) 3112455SN/A { 3127897Shestness@cs.utexas.edu numFpRegWrites++; 3132455SN/A int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; 3142683Sktlim@umich.edu thread->setFloatRegBits(reg_idx, val); 315726SN/A } 316705SN/A 3177597Sminkyu.jeong@arm.com bool readPredicate() { return thread->readPredicate(); } 3187597Sminkyu.jeong@arm.com void setPredicate(bool val) 3197600Sminkyu.jeong@arm.com { 3207600Sminkyu.jeong@arm.com thread->setPredicate(val); 3217600Sminkyu.jeong@arm.com if (traceData) { 3227600Sminkyu.jeong@arm.com traceData->setPredicate(val); 3237600Sminkyu.jeong@arm.com } 3247600Sminkyu.jeong@arm.com } 3257720Sgblack@eecs.umich.edu TheISA::PCState pcState() { return thread->pcState(); } 3267720Sgblack@eecs.umich.edu void pcState(const TheISA::PCState &val) { thread->pcState(val); } 3277720Sgblack@eecs.umich.edu Addr instAddr() { return thread->instAddr(); } 3287720Sgblack@eecs.umich.edu Addr nextInstAddr() { return thread->nextInstAddr(); } 3297720Sgblack@eecs.umich.edu MicroPC microPC() { return thread->microPC(); } 330705SN/A 3314172Ssaidi@eecs.umich.edu MiscReg readMiscRegNoEffect(int misc_reg) 3324172Ssaidi@eecs.umich.edu { 3334172Ssaidi@eecs.umich.edu return thread->readMiscRegNoEffect(misc_reg); 3344172Ssaidi@eecs.umich.edu } 3354172Ssaidi@eecs.umich.edu 3362159SN/A MiscReg readMiscReg(int misc_reg) 3372159SN/A { 3387897Shestness@cs.utexas.edu numIntRegReads++; 3392683Sktlim@umich.edu return thread->readMiscReg(misc_reg); 3402159SN/A } 341705SN/A 3423468Sgblack@eecs.umich.edu void setMiscReg(int misc_reg, const MiscReg &val) 3432159SN/A { 3447897Shestness@cs.utexas.edu numIntRegWrites++; 3452683Sktlim@umich.edu return thread->setMiscReg(misc_reg, val); 3462159SN/A } 3472159SN/A 3484185Ssaidi@eecs.umich.edu MiscReg readMiscRegOperand(const StaticInst *si, int idx) 3493792Sgblack@eecs.umich.edu { 3507897Shestness@cs.utexas.edu numIntRegReads++; 3513792Sgblack@eecs.umich.edu int reg_idx = si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag; 3523792Sgblack@eecs.umich.edu return thread->readMiscReg(reg_idx); 3533792Sgblack@eecs.umich.edu } 3543792Sgblack@eecs.umich.edu 3554185Ssaidi@eecs.umich.edu void setMiscRegOperand( 3563792Sgblack@eecs.umich.edu const StaticInst *si, int idx, const MiscReg &val) 3573792Sgblack@eecs.umich.edu { 3587897Shestness@cs.utexas.edu numIntRegWrites++; 3593792Sgblack@eecs.umich.edu int reg_idx = si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag; 3604172Ssaidi@eecs.umich.edu return thread->setMiscReg(reg_idx, val); 3613792Sgblack@eecs.umich.edu } 3623792Sgblack@eecs.umich.edu 3635358Sgblack@eecs.umich.edu void demapPage(Addr vaddr, uint64_t asn) 3645358Sgblack@eecs.umich.edu { 3655358Sgblack@eecs.umich.edu thread->demapPage(vaddr, asn); 3665358Sgblack@eecs.umich.edu } 3675358Sgblack@eecs.umich.edu 3685358Sgblack@eecs.umich.edu void demapInstPage(Addr vaddr, uint64_t asn) 3695358Sgblack@eecs.umich.edu { 3705358Sgblack@eecs.umich.edu thread->demapInstPage(vaddr, asn); 3715358Sgblack@eecs.umich.edu } 3725358Sgblack@eecs.umich.edu 3735358Sgblack@eecs.umich.edu void demapDataPage(Addr vaddr, uint64_t asn) 3745358Sgblack@eecs.umich.edu { 3755358Sgblack@eecs.umich.edu thread->demapDataPage(vaddr, asn); 3765358Sgblack@eecs.umich.edu } 3775358Sgblack@eecs.umich.edu 3784027Sstever@eecs.umich.edu unsigned readStCondFailures() { 3794027Sstever@eecs.umich.edu return thread->readStCondFailures(); 3804027Sstever@eecs.umich.edu } 3814027Sstever@eecs.umich.edu 3824027Sstever@eecs.umich.edu void setStCondFailures(unsigned sc_failures) { 3834027Sstever@eecs.umich.edu thread->setStCondFailures(sc_failures); 3844027Sstever@eecs.umich.edu } 3854027Sstever@eecs.umich.edu 3866221Snate@binkert.org MiscReg readRegOtherThread(int regIdx, ThreadID tid = InvalidThreadID) 3874661Sksewell@umich.edu { 3884661Sksewell@umich.edu panic("Simple CPU models do not support multithreaded " 3894661Sksewell@umich.edu "register access.\n"); 3904661Sksewell@umich.edu } 3914661Sksewell@umich.edu 3926221Snate@binkert.org void setRegOtherThread(int regIdx, const MiscReg &val, 3936221Snate@binkert.org ThreadID tid = InvalidThreadID) 3944661Sksewell@umich.edu { 3954661Sksewell@umich.edu panic("Simple CPU models do not support multithreaded " 3964661Sksewell@umich.edu "register access.\n"); 3974661Sksewell@umich.edu } 3984661Sksewell@umich.edu 3995250Sksewell@umich.edu //Fault CacheOp(uint8_t Op, Addr EA); 4005222Sksewell@umich.edu 4011858SN/A#if FULL_SYSTEM 4025702Ssaidi@eecs.umich.edu Fault hwrei() { return thread->hwrei(); } 4035702Ssaidi@eecs.umich.edu bool simPalCheck(int palFunc) { return thread->simPalCheck(palFunc); } 404705SN/A#else 4052683Sktlim@umich.edu void syscall(int64_t callnum) { thread->syscall(callnum); } 406705SN/A#endif 407705SN/A 4082683Sktlim@umich.edu bool misspeculating() { return thread->misspeculating(); } 4092680Sktlim@umich.edu ThreadContext *tcBase() { return tc; } 4102SN/A}; 4112SN/A 4122623SN/A#endif // __CPU_SIMPLE_BASE_HH__ 413