base.hh revision 7720
12SN/A/* 21762SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 292665Ssaidi@eecs.umich.edu * Dave Greene 302665Ssaidi@eecs.umich.edu * Nathan Binkert 312SN/A */ 322SN/A 332623SN/A#ifndef __CPU_SIMPLE_BASE_HH__ 342623SN/A#define __CPU_SIMPLE_BASE_HH__ 352SN/A 364182Sgblack@eecs.umich.edu#include "arch/predecoder.hh" 371354SN/A#include "base/statistics.hh" 381858SN/A#include "config/full_system.hh" 396658Snate@binkert.org#include "config/the_isa.hh" 401717SN/A#include "cpu/base.hh" 412683Sktlim@umich.edu#include "cpu/simple_thread.hh" 421354SN/A#include "cpu/pc_event.hh" 431354SN/A#include "cpu/static_inst.hh" 442387SN/A#include "mem/packet.hh" 452387SN/A#include "mem/port.hh" 462387SN/A#include "mem/request.hh" 4756SN/A#include "sim/eventq.hh" 485348Ssaidi@eecs.umich.edu#include "sim/system.hh" 492SN/A 502SN/A// forward declarations 511858SN/A#if FULL_SYSTEM 522SN/Aclass Processor; 533453Sgblack@eecs.umich.edunamespace TheISA 543453Sgblack@eecs.umich.edu{ 553453Sgblack@eecs.umich.edu class ITB; 563453Sgblack@eecs.umich.edu class DTB; 573453Sgblack@eecs.umich.edu} 582462SN/Aclass MemObject; 592SN/A 60715SN/A#else 61715SN/A 62715SN/Aclass Process; 63715SN/A 642SN/A#endif // FULL_SYSTEM 652SN/A 664182Sgblack@eecs.umich.edunamespace TheISA 674182Sgblack@eecs.umich.edu{ 684182Sgblack@eecs.umich.edu class Predecoder; 694182Sgblack@eecs.umich.edu} 702680Sktlim@umich.educlass ThreadContext; 71237SN/Aclass Checkpoint; 722SN/A 732SN/Anamespace Trace { 742SN/A class InstRecord; 752SN/A} 762SN/A 775529Snate@binkert.orgclass BaseSimpleCPUParams; 785529Snate@binkert.org 792420SN/A 802623SN/Aclass BaseSimpleCPU : public BaseCPU 812SN/A{ 822107SN/A protected: 832159SN/A typedef TheISA::MiscReg MiscReg; 842455SN/A typedef TheISA::FloatReg FloatReg; 852455SN/A typedef TheISA::FloatRegBits FloatRegBits; 862386SN/A 872623SN/A protected: 882SN/A Trace::InstRecord *traceData; 891371SN/A 905348Ssaidi@eecs.umich.edu inline void checkPcEventQueue() { 917720Sgblack@eecs.umich.edu Addr oldpc, pc = thread->instAddr(); 925348Ssaidi@eecs.umich.edu do { 937720Sgblack@eecs.umich.edu oldpc = pc; 945348Ssaidi@eecs.umich.edu system->pcEventQueue.service(tc); 957720Sgblack@eecs.umich.edu pc = thread->instAddr(); 967720Sgblack@eecs.umich.edu } while (oldpc != pc); 975348Ssaidi@eecs.umich.edu } 985348Ssaidi@eecs.umich.edu 992SN/A public: 1005807Snate@binkert.org void wakeup(); 1012SN/A 1022SN/A void zero_fill_64(Addr addr) { 1032SN/A static int warned = 0; 1042SN/A if (!warned) { 1052SN/A warn ("WH64 is not implemented"); 1062SN/A warned = 1; 1072SN/A } 1082SN/A }; 1092SN/A 1101400SN/A public: 1115529Snate@binkert.org BaseSimpleCPU(BaseSimpleCPUParams *params); 1122623SN/A virtual ~BaseSimpleCPU(); 1132SN/A 1141400SN/A public: 1152683Sktlim@umich.edu /** SimpleThread object, provides all the architectural state. */ 1162683Sktlim@umich.edu SimpleThread *thread; 1172190SN/A 1182683Sktlim@umich.edu /** ThreadContext object, provides an interface for external 1192683Sktlim@umich.edu * objects to modify this thread's state. 1202683Sktlim@umich.edu */ 1212680Sktlim@umich.edu ThreadContext *tc; 1225169Ssaidi@eecs.umich.edu protected: 1235169Ssaidi@eecs.umich.edu 1245496Ssaidi@eecs.umich.edu enum Status { 1255496Ssaidi@eecs.umich.edu Idle, 1265496Ssaidi@eecs.umich.edu Running, 1275894Sgblack@eecs.umich.edu ITBWaitResponse, 1285496Ssaidi@eecs.umich.edu IcacheRetry, 1295496Ssaidi@eecs.umich.edu IcacheWaitResponse, 1305496Ssaidi@eecs.umich.edu IcacheWaitSwitch, 1315894Sgblack@eecs.umich.edu DTBWaitResponse, 1325496Ssaidi@eecs.umich.edu DcacheRetry, 1335496Ssaidi@eecs.umich.edu DcacheWaitResponse, 1345496Ssaidi@eecs.umich.edu DcacheWaitSwitch, 1355496Ssaidi@eecs.umich.edu SwitchedOut 1365496Ssaidi@eecs.umich.edu }; 1375496Ssaidi@eecs.umich.edu 1385496Ssaidi@eecs.umich.edu Status _status; 1395496Ssaidi@eecs.umich.edu 1405169Ssaidi@eecs.umich.edu public: 1412SN/A 1421858SN/A#if FULL_SYSTEM 1432SN/A Addr dbg_vtophys(Addr addr); 1442SN/A 1452SN/A bool interval_stats; 1462SN/A#endif 1472SN/A 1482SN/A // current instruction 1494181Sgblack@eecs.umich.edu TheISA::MachInst inst; 1504181Sgblack@eecs.umich.edu 1514182Sgblack@eecs.umich.edu // The predecoder 1524182Sgblack@eecs.umich.edu TheISA::Predecoder predecoder; 1532SN/A 1542107SN/A StaticInstPtr curStaticInst; 1553276Sgblack@eecs.umich.edu StaticInstPtr curMacroStaticInst; 1561469SN/A 1574377Sgblack@eecs.umich.edu //This is the offset from the current pc that fetch should be performed at 1584377Sgblack@eecs.umich.edu Addr fetchOffset; 1594377Sgblack@eecs.umich.edu //This flag says to stay at the current pc. This is useful for 1604377Sgblack@eecs.umich.edu //instructions which go beyond MachInst boundaries. 1614377Sgblack@eecs.umich.edu bool stayAtPC; 1624377Sgblack@eecs.umich.edu 1632623SN/A void checkForInterrupts(); 1645894Sgblack@eecs.umich.edu void setupFetchRequest(Request *req); 1652623SN/A void preExecute(); 1662623SN/A void postExecute(); 1672623SN/A void advancePC(Fault fault); 168180SN/A 169393SN/A virtual void deallocateContext(int thread_num); 170393SN/A virtual void haltContext(int thread_num); 1712SN/A 1722SN/A // statistics 173334SN/A virtual void regStats(); 174334SN/A virtual void resetStats(); 1752SN/A 1762SN/A // number of simulated instructions 1772SN/A Counter numInst; 178334SN/A Counter startNumInst; 1795999Snate@binkert.org Stats::Scalar numInsts; 180707SN/A 1814998Sgblack@eecs.umich.edu void countInst() 1824998Sgblack@eecs.umich.edu { 1834998Sgblack@eecs.umich.edu numInst++; 1844998Sgblack@eecs.umich.edu numInsts++; 1854998Sgblack@eecs.umich.edu 1864998Sgblack@eecs.umich.edu thread->funcExeInst++; 1874998Sgblack@eecs.umich.edu } 1884998Sgblack@eecs.umich.edu 189707SN/A virtual Counter totalInstructions() const 190707SN/A { 191707SN/A return numInst - startNumInst; 192707SN/A } 1932SN/A 1944564Sgblack@eecs.umich.edu // Mask to align PCs to MachInst sized boundaries 1954564Sgblack@eecs.umich.edu static const Addr PCMask = ~((Addr)sizeof(TheISA::MachInst) - 1); 1964564Sgblack@eecs.umich.edu 1972SN/A // number of simulated memory references 1985999Snate@binkert.org Stats::Scalar numMemRefs; 1992SN/A 200124SN/A // number of simulated loads 201124SN/A Counter numLoad; 202334SN/A Counter startNumLoad; 203124SN/A 2042SN/A // number of idle cycles 2055999Snate@binkert.org Stats::Average notIdleFraction; 206729SN/A Stats::Formula idleFraction; 2072SN/A 2082390SN/A // number of cycles stalled for I-cache responses 2095999Snate@binkert.org Stats::Scalar icacheStallCycles; 2102SN/A Counter lastIcacheStall; 2112SN/A 2122390SN/A // number of cycles stalled for I-cache retries 2135999Snate@binkert.org Stats::Scalar icacheRetryCycles; 2142390SN/A Counter lastIcacheRetry; 2152390SN/A 2162390SN/A // number of cycles stalled for D-cache responses 2175999Snate@binkert.org Stats::Scalar dcacheStallCycles; 2182SN/A Counter lastDcacheStall; 2192SN/A 2202390SN/A // number of cycles stalled for D-cache retries 2215999Snate@binkert.org Stats::Scalar dcacheRetryCycles; 2222390SN/A Counter lastDcacheRetry; 2232390SN/A 224217SN/A virtual void serialize(std::ostream &os); 225237SN/A virtual void unserialize(Checkpoint *cp, const std::string §ion); 2262SN/A 2271371SN/A // These functions are only used in CPU models that split 2281371SN/A // effective address computation from the actual memory access. 2292623SN/A void setEA(Addr EA) { panic("BaseSimpleCPU::setEA() not implemented\n"); } 2305543Ssaidi@eecs.umich.edu Addr getEA() { panic("BaseSimpleCPU::getEA() not implemented\n"); 2313918Ssaidi@eecs.umich.edu M5_DUMMY_RETURN} 2321371SN/A 2337045Ssteve.reinhardt@amd.com void prefetch(Addr addr, unsigned flags); 2347045Ssteve.reinhardt@amd.com void writeHint(Addr addr, int size, unsigned flags); 2354661Sksewell@umich.edu 236595SN/A Fault copySrcTranslate(Addr src); 237594SN/A 238595SN/A Fault copy(Addr dest); 239705SN/A 240726SN/A // The register accessor methods provide the index of the 241726SN/A // instruction's operand (e.g., 0 or 1), not the architectural 242726SN/A // register index, to simplify the implementation of register 243726SN/A // renaming. We find the architectural register index by indexing 244726SN/A // into the instruction's own operand index table. Note that a 245726SN/A // raw pointer to the StaticInst is provided instead of a 246726SN/A // ref-counted StaticInstPtr to redice overhead. This is fine as 247726SN/A // long as these methods don't copy the pointer into any long-term 248726SN/A // storage (which is pretty hard to imagine they would have reason 249726SN/A // to do). 250705SN/A 2513735Sstever@eecs.umich.edu uint64_t readIntRegOperand(const StaticInst *si, int idx) 252726SN/A { 2532683Sktlim@umich.edu return thread->readIntReg(si->srcRegIdx(idx)); 254726SN/A } 255705SN/A 2563735Sstever@eecs.umich.edu FloatReg readFloatRegOperand(const StaticInst *si, int idx) 257726SN/A { 258726SN/A int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; 2592683Sktlim@umich.edu return thread->readFloatReg(reg_idx); 260726SN/A } 261705SN/A 2623735Sstever@eecs.umich.edu FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx) 2632455SN/A { 2642455SN/A int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; 2652683Sktlim@umich.edu return thread->readFloatRegBits(reg_idx); 266726SN/A } 267705SN/A 2683735Sstever@eecs.umich.edu void setIntRegOperand(const StaticInst *si, int idx, uint64_t val) 269726SN/A { 2702683Sktlim@umich.edu thread->setIntReg(si->destRegIdx(idx), val); 271726SN/A } 272705SN/A 2733735Sstever@eecs.umich.edu void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val) 274726SN/A { 275726SN/A int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; 2762683Sktlim@umich.edu thread->setFloatReg(reg_idx, val); 277726SN/A } 278726SN/A 2793735Sstever@eecs.umich.edu void setFloatRegOperandBits(const StaticInst *si, int idx, 2803735Sstever@eecs.umich.edu FloatRegBits val) 2812455SN/A { 2822455SN/A int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; 2832683Sktlim@umich.edu thread->setFloatRegBits(reg_idx, val); 284726SN/A } 285705SN/A 2867597Sminkyu.jeong@arm.com bool readPredicate() { return thread->readPredicate(); } 2877597Sminkyu.jeong@arm.com void setPredicate(bool val) 2887600Sminkyu.jeong@arm.com { 2897600Sminkyu.jeong@arm.com thread->setPredicate(val); 2907600Sminkyu.jeong@arm.com if (traceData) { 2917600Sminkyu.jeong@arm.com traceData->setPredicate(val); 2927600Sminkyu.jeong@arm.com } 2937600Sminkyu.jeong@arm.com } 2947720Sgblack@eecs.umich.edu TheISA::PCState pcState() { return thread->pcState(); } 2957720Sgblack@eecs.umich.edu void pcState(const TheISA::PCState &val) { thread->pcState(val); } 2967720Sgblack@eecs.umich.edu Addr instAddr() { return thread->instAddr(); } 2977720Sgblack@eecs.umich.edu Addr nextInstAddr() { return thread->nextInstAddr(); } 2987720Sgblack@eecs.umich.edu MicroPC microPC() { return thread->microPC(); } 299705SN/A 3004172Ssaidi@eecs.umich.edu MiscReg readMiscRegNoEffect(int misc_reg) 3014172Ssaidi@eecs.umich.edu { 3024172Ssaidi@eecs.umich.edu return thread->readMiscRegNoEffect(misc_reg); 3034172Ssaidi@eecs.umich.edu } 3044172Ssaidi@eecs.umich.edu 3052159SN/A MiscReg readMiscReg(int misc_reg) 3062159SN/A { 3072683Sktlim@umich.edu return thread->readMiscReg(misc_reg); 3082159SN/A } 309705SN/A 3104172Ssaidi@eecs.umich.edu void setMiscRegNoEffect(int misc_reg, const MiscReg &val) 3112159SN/A { 3124172Ssaidi@eecs.umich.edu return thread->setMiscRegNoEffect(misc_reg, val); 3132159SN/A } 3142159SN/A 3153468Sgblack@eecs.umich.edu void setMiscReg(int misc_reg, const MiscReg &val) 3162159SN/A { 3172683Sktlim@umich.edu return thread->setMiscReg(misc_reg, val); 3182159SN/A } 3192159SN/A 3204185Ssaidi@eecs.umich.edu MiscReg readMiscRegOperandNoEffect(const StaticInst *si, int idx) 3212159SN/A { 3224172Ssaidi@eecs.umich.edu int reg_idx = si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag; 3234172Ssaidi@eecs.umich.edu return thread->readMiscRegNoEffect(reg_idx); 3242159SN/A } 325705SN/A 3264185Ssaidi@eecs.umich.edu MiscReg readMiscRegOperand(const StaticInst *si, int idx) 3273792Sgblack@eecs.umich.edu { 3283792Sgblack@eecs.umich.edu int reg_idx = si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag; 3293792Sgblack@eecs.umich.edu return thread->readMiscReg(reg_idx); 3303792Sgblack@eecs.umich.edu } 3313792Sgblack@eecs.umich.edu 3324185Ssaidi@eecs.umich.edu void setMiscRegOperandNoEffect(const StaticInst *si, int idx, const MiscReg &val) 3333792Sgblack@eecs.umich.edu { 3343792Sgblack@eecs.umich.edu int reg_idx = si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag; 3354172Ssaidi@eecs.umich.edu return thread->setMiscRegNoEffect(reg_idx, val); 3363792Sgblack@eecs.umich.edu } 3373792Sgblack@eecs.umich.edu 3384185Ssaidi@eecs.umich.edu void setMiscRegOperand( 3393792Sgblack@eecs.umich.edu const StaticInst *si, int idx, const MiscReg &val) 3403792Sgblack@eecs.umich.edu { 3413792Sgblack@eecs.umich.edu int reg_idx = si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag; 3424172Ssaidi@eecs.umich.edu return thread->setMiscReg(reg_idx, val); 3433792Sgblack@eecs.umich.edu } 3443792Sgblack@eecs.umich.edu 3455358Sgblack@eecs.umich.edu void demapPage(Addr vaddr, uint64_t asn) 3465358Sgblack@eecs.umich.edu { 3475358Sgblack@eecs.umich.edu thread->demapPage(vaddr, asn); 3485358Sgblack@eecs.umich.edu } 3495358Sgblack@eecs.umich.edu 3505358Sgblack@eecs.umich.edu void demapInstPage(Addr vaddr, uint64_t asn) 3515358Sgblack@eecs.umich.edu { 3525358Sgblack@eecs.umich.edu thread->demapInstPage(vaddr, asn); 3535358Sgblack@eecs.umich.edu } 3545358Sgblack@eecs.umich.edu 3555358Sgblack@eecs.umich.edu void demapDataPage(Addr vaddr, uint64_t asn) 3565358Sgblack@eecs.umich.edu { 3575358Sgblack@eecs.umich.edu thread->demapDataPage(vaddr, asn); 3585358Sgblack@eecs.umich.edu } 3595358Sgblack@eecs.umich.edu 3604027Sstever@eecs.umich.edu unsigned readStCondFailures() { 3614027Sstever@eecs.umich.edu return thread->readStCondFailures(); 3624027Sstever@eecs.umich.edu } 3634027Sstever@eecs.umich.edu 3644027Sstever@eecs.umich.edu void setStCondFailures(unsigned sc_failures) { 3654027Sstever@eecs.umich.edu thread->setStCondFailures(sc_failures); 3664027Sstever@eecs.umich.edu } 3674027Sstever@eecs.umich.edu 3686221Snate@binkert.org MiscReg readRegOtherThread(int regIdx, ThreadID tid = InvalidThreadID) 3694661Sksewell@umich.edu { 3704661Sksewell@umich.edu panic("Simple CPU models do not support multithreaded " 3714661Sksewell@umich.edu "register access.\n"); 3724661Sksewell@umich.edu } 3734661Sksewell@umich.edu 3746221Snate@binkert.org void setRegOtherThread(int regIdx, const MiscReg &val, 3756221Snate@binkert.org ThreadID tid = InvalidThreadID) 3764661Sksewell@umich.edu { 3774661Sksewell@umich.edu panic("Simple CPU models do not support multithreaded " 3784661Sksewell@umich.edu "register access.\n"); 3794661Sksewell@umich.edu } 3804661Sksewell@umich.edu 3815250Sksewell@umich.edu //Fault CacheOp(uint8_t Op, Addr EA); 3825222Sksewell@umich.edu 3831858SN/A#if FULL_SYSTEM 3845702Ssaidi@eecs.umich.edu Fault hwrei() { return thread->hwrei(); } 3855702Ssaidi@eecs.umich.edu bool simPalCheck(int palFunc) { return thread->simPalCheck(palFunc); } 386705SN/A#else 3872683Sktlim@umich.edu void syscall(int64_t callnum) { thread->syscall(callnum); } 388705SN/A#endif 389705SN/A 3902683Sktlim@umich.edu bool misspeculating() { return thread->misspeculating(); } 3912680Sktlim@umich.edu ThreadContext *tcBase() { return tc; } 3922SN/A}; 3932SN/A 3942623SN/A#endif // __CPU_SIMPLE_BASE_HH__ 395