base.hh revision 7597
12SN/A/* 21762SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 292665Ssaidi@eecs.umich.edu * Dave Greene 302665Ssaidi@eecs.umich.edu * Nathan Binkert 312SN/A */ 322SN/A 332623SN/A#ifndef __CPU_SIMPLE_BASE_HH__ 342623SN/A#define __CPU_SIMPLE_BASE_HH__ 352SN/A 364182Sgblack@eecs.umich.edu#include "arch/predecoder.hh" 371354SN/A#include "base/statistics.hh" 381858SN/A#include "config/full_system.hh" 396658Snate@binkert.org#include "config/the_isa.hh" 401717SN/A#include "cpu/base.hh" 412683Sktlim@umich.edu#include "cpu/simple_thread.hh" 421354SN/A#include "cpu/pc_event.hh" 431354SN/A#include "cpu/static_inst.hh" 442387SN/A#include "mem/packet.hh" 452387SN/A#include "mem/port.hh" 462387SN/A#include "mem/request.hh" 4756SN/A#include "sim/eventq.hh" 485348Ssaidi@eecs.umich.edu#include "sim/system.hh" 492SN/A 502SN/A// forward declarations 511858SN/A#if FULL_SYSTEM 522SN/Aclass Processor; 533453Sgblack@eecs.umich.edunamespace TheISA 543453Sgblack@eecs.umich.edu{ 553453Sgblack@eecs.umich.edu class ITB; 563453Sgblack@eecs.umich.edu class DTB; 573453Sgblack@eecs.umich.edu} 582462SN/Aclass MemObject; 592SN/A 60715SN/A#else 61715SN/A 62715SN/Aclass Process; 63715SN/A 642SN/A#endif // FULL_SYSTEM 652SN/A 664182Sgblack@eecs.umich.edunamespace TheISA 674182Sgblack@eecs.umich.edu{ 684182Sgblack@eecs.umich.edu class Predecoder; 694182Sgblack@eecs.umich.edu} 702680Sktlim@umich.educlass ThreadContext; 71237SN/Aclass Checkpoint; 722SN/A 732SN/Anamespace Trace { 742SN/A class InstRecord; 752SN/A} 762SN/A 775529Snate@binkert.orgclass BaseSimpleCPUParams; 785529Snate@binkert.org 792420SN/A 802623SN/Aclass BaseSimpleCPU : public BaseCPU 812SN/A{ 822107SN/A protected: 832159SN/A typedef TheISA::MiscReg MiscReg; 842455SN/A typedef TheISA::FloatReg FloatReg; 852455SN/A typedef TheISA::FloatRegBits FloatRegBits; 862386SN/A 872623SN/A protected: 882SN/A Trace::InstRecord *traceData; 891371SN/A 905348Ssaidi@eecs.umich.edu inline void checkPcEventQueue() { 915348Ssaidi@eecs.umich.edu Addr oldpc; 925348Ssaidi@eecs.umich.edu do { 935348Ssaidi@eecs.umich.edu oldpc = thread->readPC(); 945348Ssaidi@eecs.umich.edu system->pcEventQueue.service(tc); 955348Ssaidi@eecs.umich.edu } while (oldpc != thread->readPC()); 965348Ssaidi@eecs.umich.edu } 975348Ssaidi@eecs.umich.edu 982SN/A public: 995807Snate@binkert.org void wakeup(); 1002SN/A 1012SN/A void zero_fill_64(Addr addr) { 1022SN/A static int warned = 0; 1032SN/A if (!warned) { 1042SN/A warn ("WH64 is not implemented"); 1052SN/A warned = 1; 1062SN/A } 1072SN/A }; 1082SN/A 1091400SN/A public: 1105529Snate@binkert.org BaseSimpleCPU(BaseSimpleCPUParams *params); 1112623SN/A virtual ~BaseSimpleCPU(); 1122SN/A 1131400SN/A public: 1142683Sktlim@umich.edu /** SimpleThread object, provides all the architectural state. */ 1152683Sktlim@umich.edu SimpleThread *thread; 1162190SN/A 1172683Sktlim@umich.edu /** ThreadContext object, provides an interface for external 1182683Sktlim@umich.edu * objects to modify this thread's state. 1192683Sktlim@umich.edu */ 1202680Sktlim@umich.edu ThreadContext *tc; 1215169Ssaidi@eecs.umich.edu protected: 1225169Ssaidi@eecs.umich.edu 1235496Ssaidi@eecs.umich.edu enum Status { 1245496Ssaidi@eecs.umich.edu Idle, 1255496Ssaidi@eecs.umich.edu Running, 1265894Sgblack@eecs.umich.edu ITBWaitResponse, 1275496Ssaidi@eecs.umich.edu IcacheRetry, 1285496Ssaidi@eecs.umich.edu IcacheWaitResponse, 1295496Ssaidi@eecs.umich.edu IcacheWaitSwitch, 1305894Sgblack@eecs.umich.edu DTBWaitResponse, 1315496Ssaidi@eecs.umich.edu DcacheRetry, 1325496Ssaidi@eecs.umich.edu DcacheWaitResponse, 1335496Ssaidi@eecs.umich.edu DcacheWaitSwitch, 1345496Ssaidi@eecs.umich.edu SwitchedOut 1355496Ssaidi@eecs.umich.edu }; 1365496Ssaidi@eecs.umich.edu 1375496Ssaidi@eecs.umich.edu Status _status; 1385496Ssaidi@eecs.umich.edu 1395169Ssaidi@eecs.umich.edu public: 1402SN/A 1411858SN/A#if FULL_SYSTEM 1422SN/A Addr dbg_vtophys(Addr addr); 1432SN/A 1442SN/A bool interval_stats; 1452SN/A#endif 1462SN/A 1472SN/A // current instruction 1484181Sgblack@eecs.umich.edu TheISA::MachInst inst; 1494181Sgblack@eecs.umich.edu 1504182Sgblack@eecs.umich.edu // The predecoder 1514182Sgblack@eecs.umich.edu TheISA::Predecoder predecoder; 1522SN/A 1532107SN/A StaticInstPtr curStaticInst; 1543276Sgblack@eecs.umich.edu StaticInstPtr curMacroStaticInst; 1551469SN/A 1564377Sgblack@eecs.umich.edu //This is the offset from the current pc that fetch should be performed at 1574377Sgblack@eecs.umich.edu Addr fetchOffset; 1584377Sgblack@eecs.umich.edu //This flag says to stay at the current pc. This is useful for 1594377Sgblack@eecs.umich.edu //instructions which go beyond MachInst boundaries. 1604377Sgblack@eecs.umich.edu bool stayAtPC; 1614377Sgblack@eecs.umich.edu 1622623SN/A void checkForInterrupts(); 1635894Sgblack@eecs.umich.edu void setupFetchRequest(Request *req); 1642623SN/A void preExecute(); 1652623SN/A void postExecute(); 1662623SN/A void advancePC(Fault fault); 167180SN/A 168393SN/A virtual void deallocateContext(int thread_num); 169393SN/A virtual void haltContext(int thread_num); 1702SN/A 1712SN/A // statistics 172334SN/A virtual void regStats(); 173334SN/A virtual void resetStats(); 1742SN/A 1752SN/A // number of simulated instructions 1762SN/A Counter numInst; 177334SN/A Counter startNumInst; 1785999Snate@binkert.org Stats::Scalar numInsts; 179707SN/A 1804998Sgblack@eecs.umich.edu void countInst() 1814998Sgblack@eecs.umich.edu { 1824998Sgblack@eecs.umich.edu numInst++; 1834998Sgblack@eecs.umich.edu numInsts++; 1844998Sgblack@eecs.umich.edu 1854998Sgblack@eecs.umich.edu thread->funcExeInst++; 1864998Sgblack@eecs.umich.edu } 1874998Sgblack@eecs.umich.edu 188707SN/A virtual Counter totalInstructions() const 189707SN/A { 190707SN/A return numInst - startNumInst; 191707SN/A } 1922SN/A 1934564Sgblack@eecs.umich.edu // Mask to align PCs to MachInst sized boundaries 1944564Sgblack@eecs.umich.edu static const Addr PCMask = ~((Addr)sizeof(TheISA::MachInst) - 1); 1954564Sgblack@eecs.umich.edu 1962SN/A // number of simulated memory references 1975999Snate@binkert.org Stats::Scalar numMemRefs; 1982SN/A 199124SN/A // number of simulated loads 200124SN/A Counter numLoad; 201334SN/A Counter startNumLoad; 202124SN/A 2032SN/A // number of idle cycles 2045999Snate@binkert.org Stats::Average notIdleFraction; 205729SN/A Stats::Formula idleFraction; 2062SN/A 2072390SN/A // number of cycles stalled for I-cache responses 2085999Snate@binkert.org Stats::Scalar icacheStallCycles; 2092SN/A Counter lastIcacheStall; 2102SN/A 2112390SN/A // number of cycles stalled for I-cache retries 2125999Snate@binkert.org Stats::Scalar icacheRetryCycles; 2132390SN/A Counter lastIcacheRetry; 2142390SN/A 2152390SN/A // number of cycles stalled for D-cache responses 2165999Snate@binkert.org Stats::Scalar dcacheStallCycles; 2172SN/A Counter lastDcacheStall; 2182SN/A 2192390SN/A // number of cycles stalled for D-cache retries 2205999Snate@binkert.org Stats::Scalar dcacheRetryCycles; 2212390SN/A Counter lastDcacheRetry; 2222390SN/A 223217SN/A virtual void serialize(std::ostream &os); 224237SN/A virtual void unserialize(Checkpoint *cp, const std::string §ion); 2252SN/A 2261371SN/A // These functions are only used in CPU models that split 2271371SN/A // effective address computation from the actual memory access. 2282623SN/A void setEA(Addr EA) { panic("BaseSimpleCPU::setEA() not implemented\n"); } 2295543Ssaidi@eecs.umich.edu Addr getEA() { panic("BaseSimpleCPU::getEA() not implemented\n"); 2303918Ssaidi@eecs.umich.edu M5_DUMMY_RETURN} 2311371SN/A 2327045Ssteve.reinhardt@amd.com void prefetch(Addr addr, unsigned flags); 2337045Ssteve.reinhardt@amd.com void writeHint(Addr addr, int size, unsigned flags); 2344661Sksewell@umich.edu 235595SN/A Fault copySrcTranslate(Addr src); 236594SN/A 237595SN/A Fault copy(Addr dest); 238705SN/A 239726SN/A // The register accessor methods provide the index of the 240726SN/A // instruction's operand (e.g., 0 or 1), not the architectural 241726SN/A // register index, to simplify the implementation of register 242726SN/A // renaming. We find the architectural register index by indexing 243726SN/A // into the instruction's own operand index table. Note that a 244726SN/A // raw pointer to the StaticInst is provided instead of a 245726SN/A // ref-counted StaticInstPtr to redice overhead. This is fine as 246726SN/A // long as these methods don't copy the pointer into any long-term 247726SN/A // storage (which is pretty hard to imagine they would have reason 248726SN/A // to do). 249705SN/A 2503735Sstever@eecs.umich.edu uint64_t readIntRegOperand(const StaticInst *si, int idx) 251726SN/A { 2522683Sktlim@umich.edu return thread->readIntReg(si->srcRegIdx(idx)); 253726SN/A } 254705SN/A 2553735Sstever@eecs.umich.edu FloatReg readFloatRegOperand(const StaticInst *si, int idx) 256726SN/A { 257726SN/A int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; 2582683Sktlim@umich.edu return thread->readFloatReg(reg_idx); 259726SN/A } 260705SN/A 2613735Sstever@eecs.umich.edu FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx) 2622455SN/A { 2632455SN/A int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; 2642683Sktlim@umich.edu return thread->readFloatRegBits(reg_idx); 265726SN/A } 266705SN/A 2673735Sstever@eecs.umich.edu void setIntRegOperand(const StaticInst *si, int idx, uint64_t val) 268726SN/A { 2692683Sktlim@umich.edu thread->setIntReg(si->destRegIdx(idx), val); 270726SN/A } 271705SN/A 2723735Sstever@eecs.umich.edu void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val) 273726SN/A { 274726SN/A int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; 2752683Sktlim@umich.edu thread->setFloatReg(reg_idx, val); 276726SN/A } 277726SN/A 2783735Sstever@eecs.umich.edu void setFloatRegOperandBits(const StaticInst *si, int idx, 2793735Sstever@eecs.umich.edu FloatRegBits val) 2802455SN/A { 2812455SN/A int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; 2822683Sktlim@umich.edu thread->setFloatRegBits(reg_idx, val); 283726SN/A } 284705SN/A 2852683Sktlim@umich.edu uint64_t readPC() { return thread->readPC(); } 2864950Sgblack@eecs.umich.edu uint64_t readMicroPC() { return thread->readMicroPC(); } 2872683Sktlim@umich.edu uint64_t readNextPC() { return thread->readNextPC(); } 2884950Sgblack@eecs.umich.edu uint64_t readNextMicroPC() { return thread->readNextMicroPC(); } 2892683Sktlim@umich.edu uint64_t readNextNPC() { return thread->readNextNPC(); } 2907597Sminkyu.jeong@arm.com bool readPredicate() { return thread->readPredicate(); } 2912447SN/A 2922683Sktlim@umich.edu void setPC(uint64_t val) { thread->setPC(val); } 2934950Sgblack@eecs.umich.edu void setMicroPC(uint64_t val) { thread->setMicroPC(val); } 2942683Sktlim@umich.edu void setNextPC(uint64_t val) { thread->setNextPC(val); } 2954950Sgblack@eecs.umich.edu void setNextMicroPC(uint64_t val) { thread->setNextMicroPC(val); } 2962683Sktlim@umich.edu void setNextNPC(uint64_t val) { thread->setNextNPC(val); } 2977597Sminkyu.jeong@arm.com void setPredicate(bool val) 2987597Sminkyu.jeong@arm.com { return thread->setPredicate(val); } 299705SN/A 3004172Ssaidi@eecs.umich.edu MiscReg readMiscRegNoEffect(int misc_reg) 3014172Ssaidi@eecs.umich.edu { 3024172Ssaidi@eecs.umich.edu return thread->readMiscRegNoEffect(misc_reg); 3034172Ssaidi@eecs.umich.edu } 3044172Ssaidi@eecs.umich.edu 3052159SN/A MiscReg readMiscReg(int misc_reg) 3062159SN/A { 3072683Sktlim@umich.edu return thread->readMiscReg(misc_reg); 3082159SN/A } 309705SN/A 3104172Ssaidi@eecs.umich.edu void setMiscRegNoEffect(int misc_reg, const MiscReg &val) 3112159SN/A { 3124172Ssaidi@eecs.umich.edu return thread->setMiscRegNoEffect(misc_reg, val); 3132159SN/A } 3142159SN/A 3153468Sgblack@eecs.umich.edu void setMiscReg(int misc_reg, const MiscReg &val) 3162159SN/A { 3172683Sktlim@umich.edu return thread->setMiscReg(misc_reg, val); 3182159SN/A } 3192159SN/A 3204185Ssaidi@eecs.umich.edu MiscReg readMiscRegOperandNoEffect(const StaticInst *si, int idx) 3212159SN/A { 3224172Ssaidi@eecs.umich.edu int reg_idx = si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag; 3234172Ssaidi@eecs.umich.edu return thread->readMiscRegNoEffect(reg_idx); 3242159SN/A } 325705SN/A 3264185Ssaidi@eecs.umich.edu MiscReg readMiscRegOperand(const StaticInst *si, int idx) 3273792Sgblack@eecs.umich.edu { 3283792Sgblack@eecs.umich.edu int reg_idx = si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag; 3293792Sgblack@eecs.umich.edu return thread->readMiscReg(reg_idx); 3303792Sgblack@eecs.umich.edu } 3313792Sgblack@eecs.umich.edu 3324185Ssaidi@eecs.umich.edu void setMiscRegOperandNoEffect(const StaticInst *si, int idx, const MiscReg &val) 3333792Sgblack@eecs.umich.edu { 3343792Sgblack@eecs.umich.edu int reg_idx = si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag; 3354172Ssaidi@eecs.umich.edu return thread->setMiscRegNoEffect(reg_idx, val); 3363792Sgblack@eecs.umich.edu } 3373792Sgblack@eecs.umich.edu 3384185Ssaidi@eecs.umich.edu void setMiscRegOperand( 3393792Sgblack@eecs.umich.edu const StaticInst *si, int idx, const MiscReg &val) 3403792Sgblack@eecs.umich.edu { 3413792Sgblack@eecs.umich.edu int reg_idx = si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag; 3424172Ssaidi@eecs.umich.edu return thread->setMiscReg(reg_idx, val); 3433792Sgblack@eecs.umich.edu } 3443792Sgblack@eecs.umich.edu 3455358Sgblack@eecs.umich.edu void demapPage(Addr vaddr, uint64_t asn) 3465358Sgblack@eecs.umich.edu { 3475358Sgblack@eecs.umich.edu thread->demapPage(vaddr, asn); 3485358Sgblack@eecs.umich.edu } 3495358Sgblack@eecs.umich.edu 3505358Sgblack@eecs.umich.edu void demapInstPage(Addr vaddr, uint64_t asn) 3515358Sgblack@eecs.umich.edu { 3525358Sgblack@eecs.umich.edu thread->demapInstPage(vaddr, asn); 3535358Sgblack@eecs.umich.edu } 3545358Sgblack@eecs.umich.edu 3555358Sgblack@eecs.umich.edu void demapDataPage(Addr vaddr, uint64_t asn) 3565358Sgblack@eecs.umich.edu { 3575358Sgblack@eecs.umich.edu thread->demapDataPage(vaddr, asn); 3585358Sgblack@eecs.umich.edu } 3595358Sgblack@eecs.umich.edu 3604027Sstever@eecs.umich.edu unsigned readStCondFailures() { 3614027Sstever@eecs.umich.edu return thread->readStCondFailures(); 3624027Sstever@eecs.umich.edu } 3634027Sstever@eecs.umich.edu 3644027Sstever@eecs.umich.edu void setStCondFailures(unsigned sc_failures) { 3654027Sstever@eecs.umich.edu thread->setStCondFailures(sc_failures); 3664027Sstever@eecs.umich.edu } 3674027Sstever@eecs.umich.edu 3686221Snate@binkert.org MiscReg readRegOtherThread(int regIdx, ThreadID tid = InvalidThreadID) 3694661Sksewell@umich.edu { 3704661Sksewell@umich.edu panic("Simple CPU models do not support multithreaded " 3714661Sksewell@umich.edu "register access.\n"); 3724661Sksewell@umich.edu } 3734661Sksewell@umich.edu 3746221Snate@binkert.org void setRegOtherThread(int regIdx, const MiscReg &val, 3756221Snate@binkert.org ThreadID tid = InvalidThreadID) 3764661Sksewell@umich.edu { 3774661Sksewell@umich.edu panic("Simple CPU models do not support multithreaded " 3784661Sksewell@umich.edu "register access.\n"); 3794661Sksewell@umich.edu } 3804661Sksewell@umich.edu 3815250Sksewell@umich.edu //Fault CacheOp(uint8_t Op, Addr EA); 3825222Sksewell@umich.edu 3831858SN/A#if FULL_SYSTEM 3845702Ssaidi@eecs.umich.edu Fault hwrei() { return thread->hwrei(); } 3852680Sktlim@umich.edu void ev5_trap(Fault fault) { fault->invoke(tc); } 3865702Ssaidi@eecs.umich.edu bool simPalCheck(int palFunc) { return thread->simPalCheck(palFunc); } 387705SN/A#else 3882683Sktlim@umich.edu void syscall(int64_t callnum) { thread->syscall(callnum); } 389705SN/A#endif 390705SN/A 3912683Sktlim@umich.edu bool misspeculating() { return thread->misspeculating(); } 3922680Sktlim@umich.edu ThreadContext *tcBase() { return tc; } 3932SN/A}; 3942SN/A 3952623SN/A#endif // __CPU_SIMPLE_BASE_HH__ 396