base.hh revision 753
12SN/A/* 28733Sgeoffrey.blake@arm.com * Copyright (c) 2003 The Regents of The University of Michigan 37338SAli.Saidi@ARM.com * All rights reserved. 47338SAli.Saidi@ARM.com * 57338SAli.Saidi@ARM.com * Redistribution and use in source and binary forms, with or without 67338SAli.Saidi@ARM.com * modification, are permitted provided that the following conditions are 77338SAli.Saidi@ARM.com * met: redistributions of source code must retain the above copyright 87338SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer; 97338SAli.Saidi@ARM.com * redistributions in binary form must reproduce the above copyright 107338SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer in the 117338SAli.Saidi@ARM.com * documentation and/or other materials provided with the distribution; 127338SAli.Saidi@ARM.com * neither the name of the copyright holders nor the names of its 137338SAli.Saidi@ARM.com * contributors may be used to endorse or promote products derived from 141762SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272SN/A */ 282SN/A 292SN/A#ifndef __SIMPLE_CPU_HH__ 302SN/A#define __SIMPLE_CPU_HH__ 312SN/A 322SN/A#include "cpu/base_cpu.hh" 332SN/A#include "sim/eventq.hh" 342SN/A#include "base/loader/symtab.hh" 352SN/A#include "cpu/pc_event.hh" 362SN/A#include "base/statistics.hh" 372SN/A#include "cpu/exec_context.hh" 382SN/A#include "cpu/static_inst.hh" 392665Ssaidi@eecs.umich.edu 402665Ssaidi@eecs.umich.edu// forward declarations 412SN/A#ifdef FULL_SYSTEM 422SN/Aclass Processor; 438779Sgblack@eecs.umich.educlass Kernel; 448779Sgblack@eecs.umich.educlass AlphaITB; 458779Sgblack@eecs.umich.educlass AlphaDTB; 462439SN/Aclass PhysicalMemory; 478779Sgblack@eecs.umich.edu 488229Snate@binkert.orgclass RemoteGDB; 496216Snate@binkert.orgclass GDBListener; 50146SN/A 51146SN/A#else 52146SN/A 53146SN/Aclass Process; 54146SN/A 556216Snate@binkert.org#endif // FULL_SYSTEM 566658Snate@binkert.org 578229Snate@binkert.orgclass MemInterface; 581717SN/Aclass Checkpoint; 598887Sgeoffrey.blake@arm.com 608887Sgeoffrey.blake@arm.comnamespace Trace { 61146SN/A class InstRecord; 621977SN/A} 632683Sktlim@umich.edu 641717SN/Aclass SimpleCPU : public BaseCPU 65146SN/A{ 662683Sktlim@umich.edu public: 678232Snate@binkert.org // main simulation loop (one cycle) 688232Snate@binkert.org void tick(); 698232Snate@binkert.org 708779Sgblack@eecs.umich.edu private: 713348Sbinkertn@umich.edu class TickEvent : public Event 726105Ssteve.reinhardt@amd.com { 736216Snate@binkert.org private: 742036SN/A SimpleCPU *cpu; 75146SN/A 768817Sgblack@eecs.umich.edu public: 778793Sgblack@eecs.umich.edu TickEvent(SimpleCPU *c); 7856SN/A void process(); 7956SN/A const char *description(); 80695SN/A }; 812901Ssaidi@eecs.umich.edu 822SN/A TickEvent tickEvent; 832SN/A 842449SN/A /// Schedule tick event, regardless of its current state. 851355SN/A void scheduleTickEvent(int delay) 865529Snate@binkert.org { 879023Sgblack@eecs.umich.edu if (tickEvent.squashed()) 88224SN/A tickEvent.reschedule(curTick + delay); 898793Sgblack@eecs.umich.edu else if (!tickEvent.scheduled()) 908793Sgblack@eecs.umich.edu tickEvent.schedule(curTick + delay); 918793Sgblack@eecs.umich.edu } 928820Sgblack@eecs.umich.edu 938820Sgblack@eecs.umich.edu /// Unschedule tick event, regardless of its current state. 942SN/A void unscheduleTickEvent() 956029Ssteve.reinhardt@amd.com { 962672Sktlim@umich.edu if (tickEvent.scheduled()) 972683Sktlim@umich.edu tickEvent.squash(); 982SN/A } 998733Sgeoffrey.blake@arm.com 1008733Sgeoffrey.blake@arm.com private: 1018733Sgeoffrey.blake@arm.com Trace::InstRecord *traceData; 1028733Sgeoffrey.blake@arm.com template<typename T> 1038733Sgeoffrey.blake@arm.com void trace_data(T data) { 1048733Sgeoffrey.blake@arm.com if (traceData) { 1058733Sgeoffrey.blake@arm.com traceData->setData(data); 1068733Sgeoffrey.blake@arm.com } 1078733Sgeoffrey.blake@arm.com }; 1088733Sgeoffrey.blake@arm.com 1098733Sgeoffrey.blake@arm.com public: 1102SN/A // 111334SN/A enum Status { 1128834Satgutier@umich.edu Running, 1138834Satgutier@umich.edu Idle, 114140SN/A IcacheMissStall, 115334SN/A IcacheMissComplete, 1162SN/A DcacheMissStall, 1172SN/A SwitchedOut 1182SN/A }; 1192680Sktlim@umich.edu 1204377Sgblack@eecs.umich.edu private: 1215169Ssaidi@eecs.umich.edu Status _status; 1224377Sgblack@eecs.umich.edu 1234377Sgblack@eecs.umich.edu public: 1242SN/A void post_interrupt(int int_num, int index); 1252SN/A 1262623SN/A void zero_fill_64(Addr addr) { 1272SN/A static int warned = 0; 1282SN/A if (!warned) { 1292SN/A warn ("WH64 is not implemented"); 130180SN/A warned = 1; 1318737Skoansin.tan@gmail.com } 132393SN/A }; 133393SN/A 134393SN/A#ifdef FULL_SYSTEM 135393SN/A 136384SN/A SimpleCPU(const std::string &_name, 137384SN/A System *_system, 138393SN/A Counter max_insts_any_thread, Counter max_insts_all_threads, 1398737Skoansin.tan@gmail.com Counter max_loads_any_thread, Counter max_loads_all_threads, 140393SN/A AlphaITB *itb, AlphaDTB *dtb, FunctionalMemory *mem, 141393SN/A MemInterface *icache_interface, MemInterface *dcache_interface, 142393SN/A bool _def_reg, Tick freq); 143393SN/A 144384SN/A#else 145189SN/A 146189SN/A SimpleCPU(const std::string &_name, Process *_process, 1472623SN/A Counter max_insts_any_thread, 1482SN/A Counter max_insts_all_threads, 149729SN/A Counter max_loads_any_thread, 150334SN/A Counter max_loads_all_threads, 1512SN/A MemInterface *icache_interface, MemInterface *dcache_interface, 1522SN/A bool _def_reg); 1532SN/A 1548834Satgutier@umich.edu#endif 1558834Satgutier@umich.edu 1568834Satgutier@umich.edu virtual ~SimpleCPU(); 1578834Satgutier@umich.edu virtual void init(); 1588834Satgutier@umich.edu 1598834Satgutier@umich.edu // execution context 1608834Satgutier@umich.edu ExecContext *xc; 1612SN/A 1622SN/A void switchOut(); 1637897Shestness@cs.utexas.edu void takeOverFrom(BaseCPU *oldCPU); 1647897Shestness@cs.utexas.edu 1657897Shestness@cs.utexas.edu#ifdef FULL_SYSTEM 1667897Shestness@cs.utexas.edu Addr dbg_vtophys(Addr addr); 1677897Shestness@cs.utexas.edu 1687897Shestness@cs.utexas.edu bool interval_stats; 1697897Shestness@cs.utexas.edu#endif 1707897Shestness@cs.utexas.edu 1717897Shestness@cs.utexas.edu // L1 instruction cache 1727897Shestness@cs.utexas.edu MemInterface *icacheInterface; 1737897Shestness@cs.utexas.edu 1747897Shestness@cs.utexas.edu // L1 data cache 1757897Shestness@cs.utexas.edu MemInterface *dcacheInterface; 1767897Shestness@cs.utexas.edu 1777897Shestness@cs.utexas.edu bool defer_registration; 1787897Shestness@cs.utexas.edu 1797897Shestness@cs.utexas.edu // current instruction 1807897Shestness@cs.utexas.edu MachInst inst; 1817897Shestness@cs.utexas.edu 1827897Shestness@cs.utexas.edu // Refcounted pointer to the one memory request. 1837897Shestness@cs.utexas.edu MemReqPtr memReq; 1847897Shestness@cs.utexas.edu 1857897Shestness@cs.utexas.edu class CacheCompletionEvent : public Event 1867897Shestness@cs.utexas.edu { 1877897Shestness@cs.utexas.edu private: 1887897Shestness@cs.utexas.edu SimpleCPU *cpu; 1897897Shestness@cs.utexas.edu 1907897Shestness@cs.utexas.edu public: 1917897Shestness@cs.utexas.edu CacheCompletionEvent(SimpleCPU *_cpu); 1927897Shestness@cs.utexas.edu 1937897Shestness@cs.utexas.edu virtual void process(); 1947897Shestness@cs.utexas.edu virtual const char *description(); 1957897Shestness@cs.utexas.edu }; 1967897Shestness@cs.utexas.edu 1977897Shestness@cs.utexas.edu CacheCompletionEvent cacheCompletionEvent; 1987897Shestness@cs.utexas.edu 1997897Shestness@cs.utexas.edu Status status() const { return _status; } 2007897Shestness@cs.utexas.edu 2017897Shestness@cs.utexas.edu virtual void activateContext(int thread_num, int delay); 2027897Shestness@cs.utexas.edu virtual void suspendContext(int thread_num); 2037897Shestness@cs.utexas.edu virtual void deallocateContext(int thread_num); 2047897Shestness@cs.utexas.edu virtual void haltContext(int thread_num); 2057897Shestness@cs.utexas.edu 2067897Shestness@cs.utexas.edu // statistics 2077897Shestness@cs.utexas.edu virtual void regStats(); 2087897Shestness@cs.utexas.edu virtual void resetStats(); 2097897Shestness@cs.utexas.edu 2107897Shestness@cs.utexas.edu // number of simulated instructions 2117897Shestness@cs.utexas.edu Counter numInst; 2127897Shestness@cs.utexas.edu Counter startNumInst; 2132SN/A Stats::Scalar<> numInsts; 2147897Shestness@cs.utexas.edu 2157897Shestness@cs.utexas.edu virtual Counter totalInstructions() const 2167897Shestness@cs.utexas.edu { 2177897Shestness@cs.utexas.edu return numInst - startNumInst; 2187897Shestness@cs.utexas.edu } 2197897Shestness@cs.utexas.edu 2207897Shestness@cs.utexas.edu // number of simulated memory references 2217897Shestness@cs.utexas.edu Stats::Scalar<> numMemRefs; 2227897Shestness@cs.utexas.edu 2237897Shestness@cs.utexas.edu // number of simulated loads 2247897Shestness@cs.utexas.edu Counter numLoad; 2257897Shestness@cs.utexas.edu Counter startNumLoad; 2262SN/A 2272SN/A // number of idle cycles 2281001SN/A Stats::Average<> notIdleFraction; 2291001SN/A Stats::Formula idleFraction; 2301001SN/A 2311001SN/A // number of cycles stalled for I-cache misses 2321001SN/A Stats::Scalar<> icacheStallCycles; 2332SN/A Counter lastIcacheStall; 2342SN/A 2352SN/A // number of cycles stalled for D-cache misses 2362SN/A Stats::Scalar<> dcacheStallCycles; 2372SN/A Counter lastDcacheStall; 2387897Shestness@cs.utexas.edu 2397897Shestness@cs.utexas.edu void processCacheCompletion(); 2407897Shestness@cs.utexas.edu 2417897Shestness@cs.utexas.edu virtual void serialize(std::ostream &os); 2427897Shestness@cs.utexas.edu virtual void unserialize(Checkpoint *cp, const std::string §ion); 2437897Shestness@cs.utexas.edu 2447897Shestness@cs.utexas.edu template <class T> 2457897Shestness@cs.utexas.edu Fault read(Addr addr, T &data, unsigned flags); 2467897Shestness@cs.utexas.edu 2477897Shestness@cs.utexas.edu template <class T> 2482SN/A Fault write(T data, Addr addr, unsigned flags, 2492SN/A uint64_t *res); 2502SN/A 2512SN/A void prefetch(Addr addr, unsigned flags) 2522SN/A { 2532SN/A // need to do this... 2542SN/A } 2552SN/A 2562SN/A void writeHint(Addr addr, int size, unsigned flags) 2572SN/A { 2582SN/A // need to do this... 2592SN/A } 2602390SN/A 2612390SN/A Fault copySrcTranslate(Addr src); 2622390SN/A 2632390SN/A Fault copy(Addr dest); 2642390SN/A 2652390SN/A // The register accessor methods provide the index of the 2662390SN/A // instruction's operand (e.g., 0 or 1), not the architectural 2672390SN/A // register index, to simplify the implementation of register 2682390SN/A // renaming. We find the architectural register index by indexing 2692390SN/A // into the instruction's own operand index table. Note that a 2702390SN/A // raw pointer to the StaticInst is provided instead of a 2712390SN/A // ref-counted StaticInstPtr to redice overhead. This is fine as 272385SN/A // long as these methods don't copy the pointer into any long-term 2737897Shestness@cs.utexas.edu // storage (which is pretty hard to imagine they would have reason 2747897Shestness@cs.utexas.edu // to do). 2752SN/A 2762SN/A uint64_t readIntReg(StaticInst<TheISA> *si, int idx) 2772SN/A { 2782623SN/A return xc->readIntReg(si->srcRegIdx(idx)); 279334SN/A } 2802361SN/A 2815496Ssaidi@eecs.umich.edu float readFloatRegSingle(StaticInst<TheISA> *si, int idx) 282334SN/A { 283334SN/A int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; 284334SN/A return xc->readFloatRegSingle(reg_idx); 2852623SN/A } 2862SN/A 2875496Ssaidi@eecs.umich.edu double readFloatRegDouble(StaticInst<TheISA> *si, int idx) 288921SN/A { 2892915Sktlim@umich.edu int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; 2902915Sktlim@umich.edu return xc->readFloatRegDouble(reg_idx); 2912683Sktlim@umich.edu } 2922SN/A 2932SN/A uint64_t readFloatRegInt(StaticInst<TheISA> *si, int idx) 2942SN/A { 2952623SN/A int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; 2962SN/A return xc->readFloatRegInt(reg_idx); 2975496Ssaidi@eecs.umich.edu } 298921SN/A 2992915Sktlim@umich.edu void setIntReg(StaticInst<TheISA> *si, int idx, uint64_t val) 3002915Sktlim@umich.edu { 3012SN/A xc->setIntReg(si->destRegIdx(idx), val); 3022SN/A } 3032SN/A 3046221Snate@binkert.org void setFloatRegSingle(StaticInst<TheISA> *si, int idx, float val) 3052SN/A { 3062SN/A int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; 3072SN/A xc->setFloatRegSingle(reg_idx, val); 3082SN/A } 3092623SN/A 3102SN/A void setFloatRegDouble(StaticInst<TheISA> *si, int idx, double val) 3112680Sktlim@umich.edu { 3122SN/A int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; 3132SN/A xc->setFloatRegDouble(reg_idx, val); 3142SN/A } 3155807Snate@binkert.org 3162SN/A void setFloatRegInt(StaticInst<TheISA> *si, int idx, uint64_t val) 3175807Snate@binkert.org { 3185807Snate@binkert.org int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; 3192SN/A xc->setFloatRegInt(reg_idx, val); 3205807Snate@binkert.org } 3215807Snate@binkert.org 3222SN/A uint64_t readPC() { return xc->readPC(); } 3232SN/A void setNextPC(uint64_t val) { xc->setNextPC(val); } 3242SN/A 3252623SN/A uint64_t readUniq() { return xc->readUniq(); } 3262SN/A void setUniq(uint64_t val) { xc->setUniq(val); } 3275704Snate@binkert.org 3285647Sgblack@eecs.umich.edu uint64_t readFpcr() { return xc->readFpcr(); } 3292SN/A void setFpcr(uint64_t val) { xc->setFpcr(val); } 3303520Sgblack@eecs.umich.edu 3317338SAli.Saidi@ARM.com#ifdef FULL_SYSTEM 3325647Sgblack@eecs.umich.edu uint64_t readIpr(int idx, Fault &fault) { return xc->readIpr(idx, fault); } 3333520Sgblack@eecs.umich.edu Fault setIpr(int idx, uint64_t val) { return xc->setIpr(idx, val); } 3349023Sgblack@eecs.umich.edu Fault hwrei() { return xc->hwrei(); } 3352SN/A int readIntrFlag() { return xc->readIntrFlag(); } 3362SN/A void setIntrFlag(int val) { xc->setIntrFlag(val); } 3372623SN/A bool inPalMode() { return xc->inPalMode(); } 3382SN/A void ev5_trap(Fault fault) { xc->ev5_trap(fault); } 3392623SN/A bool simPalCheck(int palFunc) { return xc->simPalCheck(palFunc); } 3405894Sgblack@eecs.umich.edu#else 3412662Sstever@eecs.umich.edu void syscall() { xc->syscall(); } 3422623SN/A#endif 3437720Sgblack@eecs.umich.edu 3444495Sacolyte@umich.edu bool misspeculating() { return xc->misspeculating(); } 3452623SN/A ExecContext *xcBase() { return xc; } 3467720Sgblack@eecs.umich.edu}; 3472623SN/A 3487720Sgblack@eecs.umich.edu#endif // __SIMPLE_CPU_HH__ 3498832SAli.Saidi@ARM.com