base.hh revision 7045
12SN/A/* 21762SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 292665Ssaidi@eecs.umich.edu * Dave Greene 302665Ssaidi@eecs.umich.edu * Nathan Binkert 312SN/A */ 322SN/A 332623SN/A#ifndef __CPU_SIMPLE_BASE_HH__ 342623SN/A#define __CPU_SIMPLE_BASE_HH__ 352SN/A 364182Sgblack@eecs.umich.edu#include "arch/predecoder.hh" 371354SN/A#include "base/statistics.hh" 381858SN/A#include "config/full_system.hh" 396658Snate@binkert.org#include "config/the_isa.hh" 401717SN/A#include "cpu/base.hh" 412683Sktlim@umich.edu#include "cpu/simple_thread.hh" 421354SN/A#include "cpu/pc_event.hh" 431354SN/A#include "cpu/static_inst.hh" 442387SN/A#include "mem/packet.hh" 452387SN/A#include "mem/port.hh" 462387SN/A#include "mem/request.hh" 4756SN/A#include "sim/eventq.hh" 485348Ssaidi@eecs.umich.edu#include "sim/system.hh" 492SN/A 502SN/A// forward declarations 511858SN/A#if FULL_SYSTEM 522SN/Aclass Processor; 533453Sgblack@eecs.umich.edunamespace TheISA 543453Sgblack@eecs.umich.edu{ 553453Sgblack@eecs.umich.edu class ITB; 563453Sgblack@eecs.umich.edu class DTB; 573453Sgblack@eecs.umich.edu} 582462SN/Aclass MemObject; 592SN/A 60715SN/A#else 61715SN/A 62715SN/Aclass Process; 63715SN/A 642SN/A#endif // FULL_SYSTEM 652SN/A 663960Sgblack@eecs.umich.educlass RemoteGDB; 673960Sgblack@eecs.umich.educlass GDBListener; 683960Sgblack@eecs.umich.edu 694182Sgblack@eecs.umich.edunamespace TheISA 704182Sgblack@eecs.umich.edu{ 714182Sgblack@eecs.umich.edu class Predecoder; 724182Sgblack@eecs.umich.edu} 732680Sktlim@umich.educlass ThreadContext; 74237SN/Aclass Checkpoint; 752SN/A 762SN/Anamespace Trace { 772SN/A class InstRecord; 782SN/A} 792SN/A 805529Snate@binkert.orgclass BaseSimpleCPUParams; 815529Snate@binkert.org 822420SN/A 832623SN/Aclass BaseSimpleCPU : public BaseCPU 842SN/A{ 852107SN/A protected: 862159SN/A typedef TheISA::MiscReg MiscReg; 872455SN/A typedef TheISA::FloatReg FloatReg; 882455SN/A typedef TheISA::FloatRegBits FloatRegBits; 892386SN/A 902623SN/A protected: 912SN/A Trace::InstRecord *traceData; 921371SN/A 935348Ssaidi@eecs.umich.edu inline void checkPcEventQueue() { 945348Ssaidi@eecs.umich.edu Addr oldpc; 955348Ssaidi@eecs.umich.edu do { 965348Ssaidi@eecs.umich.edu oldpc = thread->readPC(); 975348Ssaidi@eecs.umich.edu system->pcEventQueue.service(tc); 985348Ssaidi@eecs.umich.edu } while (oldpc != thread->readPC()); 995348Ssaidi@eecs.umich.edu } 1005348Ssaidi@eecs.umich.edu 1012SN/A public: 1025807Snate@binkert.org void wakeup(); 1032SN/A 1042SN/A void zero_fill_64(Addr addr) { 1052SN/A static int warned = 0; 1062SN/A if (!warned) { 1072SN/A warn ("WH64 is not implemented"); 1082SN/A warned = 1; 1092SN/A } 1102SN/A }; 1112SN/A 1121400SN/A public: 1135529Snate@binkert.org BaseSimpleCPU(BaseSimpleCPUParams *params); 1142623SN/A virtual ~BaseSimpleCPU(); 1152SN/A 1161400SN/A public: 1172683Sktlim@umich.edu /** SimpleThread object, provides all the architectural state. */ 1182683Sktlim@umich.edu SimpleThread *thread; 1192190SN/A 1202683Sktlim@umich.edu /** ThreadContext object, provides an interface for external 1212683Sktlim@umich.edu * objects to modify this thread's state. 1222683Sktlim@umich.edu */ 1232680Sktlim@umich.edu ThreadContext *tc; 1245169Ssaidi@eecs.umich.edu protected: 1255169Ssaidi@eecs.umich.edu 1265496Ssaidi@eecs.umich.edu enum Status { 1275496Ssaidi@eecs.umich.edu Idle, 1285496Ssaidi@eecs.umich.edu Running, 1295894Sgblack@eecs.umich.edu ITBWaitResponse, 1305496Ssaidi@eecs.umich.edu IcacheRetry, 1315496Ssaidi@eecs.umich.edu IcacheWaitResponse, 1325496Ssaidi@eecs.umich.edu IcacheWaitSwitch, 1335894Sgblack@eecs.umich.edu DTBWaitResponse, 1345496Ssaidi@eecs.umich.edu DcacheRetry, 1355496Ssaidi@eecs.umich.edu DcacheWaitResponse, 1365496Ssaidi@eecs.umich.edu DcacheWaitSwitch, 1375496Ssaidi@eecs.umich.edu SwitchedOut 1385496Ssaidi@eecs.umich.edu }; 1395496Ssaidi@eecs.umich.edu 1405496Ssaidi@eecs.umich.edu Status _status; 1415496Ssaidi@eecs.umich.edu 1425169Ssaidi@eecs.umich.edu public: 1432SN/A 1441858SN/A#if FULL_SYSTEM 1452SN/A Addr dbg_vtophys(Addr addr); 1462SN/A 1472SN/A bool interval_stats; 1482SN/A#endif 1492SN/A 1502SN/A // current instruction 1514181Sgblack@eecs.umich.edu TheISA::MachInst inst; 1524181Sgblack@eecs.umich.edu 1534182Sgblack@eecs.umich.edu // The predecoder 1544182Sgblack@eecs.umich.edu TheISA::Predecoder predecoder; 1552SN/A 1562107SN/A StaticInstPtr curStaticInst; 1573276Sgblack@eecs.umich.edu StaticInstPtr curMacroStaticInst; 1581469SN/A 1594377Sgblack@eecs.umich.edu //This is the offset from the current pc that fetch should be performed at 1604377Sgblack@eecs.umich.edu Addr fetchOffset; 1614377Sgblack@eecs.umich.edu //This flag says to stay at the current pc. This is useful for 1624377Sgblack@eecs.umich.edu //instructions which go beyond MachInst boundaries. 1634377Sgblack@eecs.umich.edu bool stayAtPC; 1644377Sgblack@eecs.umich.edu 1652623SN/A void checkForInterrupts(); 1665894Sgblack@eecs.umich.edu void setupFetchRequest(Request *req); 1672623SN/A void preExecute(); 1682623SN/A void postExecute(); 1692623SN/A void advancePC(Fault fault); 170180SN/A 171393SN/A virtual void deallocateContext(int thread_num); 172393SN/A virtual void haltContext(int thread_num); 1732SN/A 1742SN/A // statistics 175334SN/A virtual void regStats(); 176334SN/A virtual void resetStats(); 1772SN/A 1782SN/A // number of simulated instructions 1792SN/A Counter numInst; 180334SN/A Counter startNumInst; 1815999Snate@binkert.org Stats::Scalar numInsts; 182707SN/A 1834998Sgblack@eecs.umich.edu void countInst() 1844998Sgblack@eecs.umich.edu { 1854998Sgblack@eecs.umich.edu numInst++; 1864998Sgblack@eecs.umich.edu numInsts++; 1874998Sgblack@eecs.umich.edu 1884998Sgblack@eecs.umich.edu thread->funcExeInst++; 1894998Sgblack@eecs.umich.edu } 1904998Sgblack@eecs.umich.edu 191707SN/A virtual Counter totalInstructions() const 192707SN/A { 193707SN/A return numInst - startNumInst; 194707SN/A } 1952SN/A 1964564Sgblack@eecs.umich.edu // Mask to align PCs to MachInst sized boundaries 1974564Sgblack@eecs.umich.edu static const Addr PCMask = ~((Addr)sizeof(TheISA::MachInst) - 1); 1984564Sgblack@eecs.umich.edu 1992SN/A // number of simulated memory references 2005999Snate@binkert.org Stats::Scalar numMemRefs; 2012SN/A 202124SN/A // number of simulated loads 203124SN/A Counter numLoad; 204334SN/A Counter startNumLoad; 205124SN/A 2062SN/A // number of idle cycles 2075999Snate@binkert.org Stats::Average notIdleFraction; 208729SN/A Stats::Formula idleFraction; 2092SN/A 2102390SN/A // number of cycles stalled for I-cache responses 2115999Snate@binkert.org Stats::Scalar icacheStallCycles; 2122SN/A Counter lastIcacheStall; 2132SN/A 2142390SN/A // number of cycles stalled for I-cache retries 2155999Snate@binkert.org Stats::Scalar icacheRetryCycles; 2162390SN/A Counter lastIcacheRetry; 2172390SN/A 2182390SN/A // number of cycles stalled for D-cache responses 2195999Snate@binkert.org Stats::Scalar dcacheStallCycles; 2202SN/A Counter lastDcacheStall; 2212SN/A 2222390SN/A // number of cycles stalled for D-cache retries 2235999Snate@binkert.org Stats::Scalar dcacheRetryCycles; 2242390SN/A Counter lastDcacheRetry; 2252390SN/A 226217SN/A virtual void serialize(std::ostream &os); 227237SN/A virtual void unserialize(Checkpoint *cp, const std::string §ion); 2282SN/A 2291371SN/A // These functions are only used in CPU models that split 2301371SN/A // effective address computation from the actual memory access. 2312623SN/A void setEA(Addr EA) { panic("BaseSimpleCPU::setEA() not implemented\n"); } 2325543Ssaidi@eecs.umich.edu Addr getEA() { panic("BaseSimpleCPU::getEA() not implemented\n"); 2333918Ssaidi@eecs.umich.edu M5_DUMMY_RETURN} 2341371SN/A 2357045Ssteve.reinhardt@amd.com void prefetch(Addr addr, unsigned flags); 2367045Ssteve.reinhardt@amd.com void writeHint(Addr addr, int size, unsigned flags); 2374661Sksewell@umich.edu 238595SN/A Fault copySrcTranslate(Addr src); 239594SN/A 240595SN/A Fault copy(Addr dest); 241705SN/A 242726SN/A // The register accessor methods provide the index of the 243726SN/A // instruction's operand (e.g., 0 or 1), not the architectural 244726SN/A // register index, to simplify the implementation of register 245726SN/A // renaming. We find the architectural register index by indexing 246726SN/A // into the instruction's own operand index table. Note that a 247726SN/A // raw pointer to the StaticInst is provided instead of a 248726SN/A // ref-counted StaticInstPtr to redice overhead. This is fine as 249726SN/A // long as these methods don't copy the pointer into any long-term 250726SN/A // storage (which is pretty hard to imagine they would have reason 251726SN/A // to do). 252705SN/A 2533735Sstever@eecs.umich.edu uint64_t readIntRegOperand(const StaticInst *si, int idx) 254726SN/A { 2552683Sktlim@umich.edu return thread->readIntReg(si->srcRegIdx(idx)); 256726SN/A } 257705SN/A 2583735Sstever@eecs.umich.edu FloatReg readFloatRegOperand(const StaticInst *si, int idx) 259726SN/A { 260726SN/A int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; 2612683Sktlim@umich.edu return thread->readFloatReg(reg_idx); 262726SN/A } 263705SN/A 2643735Sstever@eecs.umich.edu FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx) 2652455SN/A { 2662455SN/A int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; 2672683Sktlim@umich.edu return thread->readFloatRegBits(reg_idx); 268726SN/A } 269705SN/A 2703735Sstever@eecs.umich.edu void setIntRegOperand(const StaticInst *si, int idx, uint64_t val) 271726SN/A { 2722683Sktlim@umich.edu thread->setIntReg(si->destRegIdx(idx), val); 273726SN/A } 274705SN/A 2753735Sstever@eecs.umich.edu void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val) 276726SN/A { 277726SN/A int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; 2782683Sktlim@umich.edu thread->setFloatReg(reg_idx, val); 279726SN/A } 280726SN/A 2813735Sstever@eecs.umich.edu void setFloatRegOperandBits(const StaticInst *si, int idx, 2823735Sstever@eecs.umich.edu FloatRegBits val) 2832455SN/A { 2842455SN/A int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; 2852683Sktlim@umich.edu thread->setFloatRegBits(reg_idx, val); 286726SN/A } 287705SN/A 2882683Sktlim@umich.edu uint64_t readPC() { return thread->readPC(); } 2894950Sgblack@eecs.umich.edu uint64_t readMicroPC() { return thread->readMicroPC(); } 2902683Sktlim@umich.edu uint64_t readNextPC() { return thread->readNextPC(); } 2914950Sgblack@eecs.umich.edu uint64_t readNextMicroPC() { return thread->readNextMicroPC(); } 2922683Sktlim@umich.edu uint64_t readNextNPC() { return thread->readNextNPC(); } 2932447SN/A 2942683Sktlim@umich.edu void setPC(uint64_t val) { thread->setPC(val); } 2954950Sgblack@eecs.umich.edu void setMicroPC(uint64_t val) { thread->setMicroPC(val); } 2962683Sktlim@umich.edu void setNextPC(uint64_t val) { thread->setNextPC(val); } 2974950Sgblack@eecs.umich.edu void setNextMicroPC(uint64_t val) { thread->setNextMicroPC(val); } 2982683Sktlim@umich.edu void setNextNPC(uint64_t val) { thread->setNextNPC(val); } 299705SN/A 3004172Ssaidi@eecs.umich.edu MiscReg readMiscRegNoEffect(int misc_reg) 3014172Ssaidi@eecs.umich.edu { 3024172Ssaidi@eecs.umich.edu return thread->readMiscRegNoEffect(misc_reg); 3034172Ssaidi@eecs.umich.edu } 3044172Ssaidi@eecs.umich.edu 3052159SN/A MiscReg readMiscReg(int misc_reg) 3062159SN/A { 3072683Sktlim@umich.edu return thread->readMiscReg(misc_reg); 3082159SN/A } 309705SN/A 3104172Ssaidi@eecs.umich.edu void setMiscRegNoEffect(int misc_reg, const MiscReg &val) 3112159SN/A { 3124172Ssaidi@eecs.umich.edu return thread->setMiscRegNoEffect(misc_reg, val); 3132159SN/A } 3142159SN/A 3153468Sgblack@eecs.umich.edu void setMiscReg(int misc_reg, const MiscReg &val) 3162159SN/A { 3172683Sktlim@umich.edu return thread->setMiscReg(misc_reg, val); 3182159SN/A } 3192159SN/A 3204185Ssaidi@eecs.umich.edu MiscReg readMiscRegOperandNoEffect(const StaticInst *si, int idx) 3212159SN/A { 3224172Ssaidi@eecs.umich.edu int reg_idx = si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag; 3234172Ssaidi@eecs.umich.edu return thread->readMiscRegNoEffect(reg_idx); 3242159SN/A } 325705SN/A 3264185Ssaidi@eecs.umich.edu MiscReg readMiscRegOperand(const StaticInst *si, int idx) 3273792Sgblack@eecs.umich.edu { 3283792Sgblack@eecs.umich.edu int reg_idx = si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag; 3293792Sgblack@eecs.umich.edu return thread->readMiscReg(reg_idx); 3303792Sgblack@eecs.umich.edu } 3313792Sgblack@eecs.umich.edu 3324185Ssaidi@eecs.umich.edu void setMiscRegOperandNoEffect(const StaticInst *si, int idx, const MiscReg &val) 3333792Sgblack@eecs.umich.edu { 3343792Sgblack@eecs.umich.edu int reg_idx = si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag; 3354172Ssaidi@eecs.umich.edu return thread->setMiscRegNoEffect(reg_idx, val); 3363792Sgblack@eecs.umich.edu } 3373792Sgblack@eecs.umich.edu 3384185Ssaidi@eecs.umich.edu void setMiscRegOperand( 3393792Sgblack@eecs.umich.edu const StaticInst *si, int idx, const MiscReg &val) 3403792Sgblack@eecs.umich.edu { 3413792Sgblack@eecs.umich.edu int reg_idx = si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag; 3424172Ssaidi@eecs.umich.edu return thread->setMiscReg(reg_idx, val); 3433792Sgblack@eecs.umich.edu } 3443792Sgblack@eecs.umich.edu 3455358Sgblack@eecs.umich.edu void demapPage(Addr vaddr, uint64_t asn) 3465358Sgblack@eecs.umich.edu { 3475358Sgblack@eecs.umich.edu thread->demapPage(vaddr, asn); 3485358Sgblack@eecs.umich.edu } 3495358Sgblack@eecs.umich.edu 3505358Sgblack@eecs.umich.edu void demapInstPage(Addr vaddr, uint64_t asn) 3515358Sgblack@eecs.umich.edu { 3525358Sgblack@eecs.umich.edu thread->demapInstPage(vaddr, asn); 3535358Sgblack@eecs.umich.edu } 3545358Sgblack@eecs.umich.edu 3555358Sgblack@eecs.umich.edu void demapDataPage(Addr vaddr, uint64_t asn) 3565358Sgblack@eecs.umich.edu { 3575358Sgblack@eecs.umich.edu thread->demapDataPage(vaddr, asn); 3585358Sgblack@eecs.umich.edu } 3595358Sgblack@eecs.umich.edu 3604027Sstever@eecs.umich.edu unsigned readStCondFailures() { 3614027Sstever@eecs.umich.edu return thread->readStCondFailures(); 3624027Sstever@eecs.umich.edu } 3634027Sstever@eecs.umich.edu 3644027Sstever@eecs.umich.edu void setStCondFailures(unsigned sc_failures) { 3654027Sstever@eecs.umich.edu thread->setStCondFailures(sc_failures); 3664027Sstever@eecs.umich.edu } 3674027Sstever@eecs.umich.edu 3686221Snate@binkert.org MiscReg readRegOtherThread(int regIdx, ThreadID tid = InvalidThreadID) 3694661Sksewell@umich.edu { 3704661Sksewell@umich.edu panic("Simple CPU models do not support multithreaded " 3714661Sksewell@umich.edu "register access.\n"); 3724661Sksewell@umich.edu } 3734661Sksewell@umich.edu 3746221Snate@binkert.org void setRegOtherThread(int regIdx, const MiscReg &val, 3756221Snate@binkert.org ThreadID tid = InvalidThreadID) 3764661Sksewell@umich.edu { 3774661Sksewell@umich.edu panic("Simple CPU models do not support multithreaded " 3784661Sksewell@umich.edu "register access.\n"); 3794661Sksewell@umich.edu } 3804661Sksewell@umich.edu 3815250Sksewell@umich.edu //Fault CacheOp(uint8_t Op, Addr EA); 3825222Sksewell@umich.edu 3831858SN/A#if FULL_SYSTEM 3845702Ssaidi@eecs.umich.edu Fault hwrei() { return thread->hwrei(); } 3852680Sktlim@umich.edu void ev5_trap(Fault fault) { fault->invoke(tc); } 3865702Ssaidi@eecs.umich.edu bool simPalCheck(int palFunc) { return thread->simPalCheck(palFunc); } 387705SN/A#else 3882683Sktlim@umich.edu void syscall(int64_t callnum) { thread->syscall(callnum); } 389705SN/A#endif 390705SN/A 3912683Sktlim@umich.edu bool misspeculating() { return thread->misspeculating(); } 3922680Sktlim@umich.edu ThreadContext *tcBase() { return tc; } 3932SN/A}; 3942SN/A 3952623SN/A#endif // __CPU_SIMPLE_BASE_HH__ 396