base.hh revision 6221
12SN/A/* 21762SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 292665Ssaidi@eecs.umich.edu * Dave Greene 302665Ssaidi@eecs.umich.edu * Nathan Binkert 312SN/A */ 322SN/A 332623SN/A#ifndef __CPU_SIMPLE_BASE_HH__ 342623SN/A#define __CPU_SIMPLE_BASE_HH__ 352SN/A 364182Sgblack@eecs.umich.edu#include "arch/predecoder.hh" 371354SN/A#include "base/statistics.hh" 381858SN/A#include "config/full_system.hh" 391717SN/A#include "cpu/base.hh" 402683Sktlim@umich.edu#include "cpu/simple_thread.hh" 411354SN/A#include "cpu/pc_event.hh" 421354SN/A#include "cpu/static_inst.hh" 432387SN/A#include "mem/packet.hh" 442387SN/A#include "mem/port.hh" 452387SN/A#include "mem/request.hh" 4656SN/A#include "sim/eventq.hh" 475348Ssaidi@eecs.umich.edu#include "sim/system.hh" 482SN/A 492SN/A// forward declarations 501858SN/A#if FULL_SYSTEM 512SN/Aclass Processor; 523453Sgblack@eecs.umich.edunamespace TheISA 533453Sgblack@eecs.umich.edu{ 543453Sgblack@eecs.umich.edu class ITB; 553453Sgblack@eecs.umich.edu class DTB; 563453Sgblack@eecs.umich.edu} 572462SN/Aclass MemObject; 582SN/A 59715SN/A#else 60715SN/A 61715SN/Aclass Process; 62715SN/A 632SN/A#endif // FULL_SYSTEM 642SN/A 653960Sgblack@eecs.umich.educlass RemoteGDB; 663960Sgblack@eecs.umich.educlass GDBListener; 673960Sgblack@eecs.umich.edu 684182Sgblack@eecs.umich.edunamespace TheISA 694182Sgblack@eecs.umich.edu{ 704182Sgblack@eecs.umich.edu class Predecoder; 714182Sgblack@eecs.umich.edu} 722680Sktlim@umich.educlass ThreadContext; 73237SN/Aclass Checkpoint; 742SN/A 752SN/Anamespace Trace { 762SN/A class InstRecord; 772SN/A} 782SN/A 795529Snate@binkert.orgclass BaseSimpleCPUParams; 805529Snate@binkert.org 812420SN/A 822623SN/Aclass BaseSimpleCPU : public BaseCPU 832SN/A{ 842107SN/A protected: 852159SN/A typedef TheISA::MiscReg MiscReg; 862455SN/A typedef TheISA::FloatReg FloatReg; 872455SN/A typedef TheISA::FloatRegBits FloatRegBits; 882386SN/A 892623SN/A protected: 902SN/A Trace::InstRecord *traceData; 911371SN/A 925348Ssaidi@eecs.umich.edu inline void checkPcEventQueue() { 935348Ssaidi@eecs.umich.edu Addr oldpc; 945348Ssaidi@eecs.umich.edu do { 955348Ssaidi@eecs.umich.edu oldpc = thread->readPC(); 965348Ssaidi@eecs.umich.edu system->pcEventQueue.service(tc); 975348Ssaidi@eecs.umich.edu } while (oldpc != thread->readPC()); 985348Ssaidi@eecs.umich.edu } 995348Ssaidi@eecs.umich.edu 1002SN/A public: 1015807Snate@binkert.org void wakeup(); 1022SN/A 1032SN/A void zero_fill_64(Addr addr) { 1042SN/A static int warned = 0; 1052SN/A if (!warned) { 1062SN/A warn ("WH64 is not implemented"); 1072SN/A warned = 1; 1082SN/A } 1092SN/A }; 1102SN/A 1111400SN/A public: 1125529Snate@binkert.org BaseSimpleCPU(BaseSimpleCPUParams *params); 1132623SN/A virtual ~BaseSimpleCPU(); 1142SN/A 1151400SN/A public: 1162683Sktlim@umich.edu /** SimpleThread object, provides all the architectural state. */ 1172683Sktlim@umich.edu SimpleThread *thread; 1182190SN/A 1192683Sktlim@umich.edu /** ThreadContext object, provides an interface for external 1202683Sktlim@umich.edu * objects to modify this thread's state. 1212683Sktlim@umich.edu */ 1222680Sktlim@umich.edu ThreadContext *tc; 1235169Ssaidi@eecs.umich.edu protected: 1245169Ssaidi@eecs.umich.edu 1255496Ssaidi@eecs.umich.edu enum Status { 1265496Ssaidi@eecs.umich.edu Idle, 1275496Ssaidi@eecs.umich.edu Running, 1285894Sgblack@eecs.umich.edu ITBWaitResponse, 1295496Ssaidi@eecs.umich.edu IcacheRetry, 1305496Ssaidi@eecs.umich.edu IcacheWaitResponse, 1315496Ssaidi@eecs.umich.edu IcacheWaitSwitch, 1325894Sgblack@eecs.umich.edu DTBWaitResponse, 1335496Ssaidi@eecs.umich.edu DcacheRetry, 1345496Ssaidi@eecs.umich.edu DcacheWaitResponse, 1355496Ssaidi@eecs.umich.edu DcacheWaitSwitch, 1365496Ssaidi@eecs.umich.edu SwitchedOut 1375496Ssaidi@eecs.umich.edu }; 1385496Ssaidi@eecs.umich.edu 1395496Ssaidi@eecs.umich.edu Status _status; 1405496Ssaidi@eecs.umich.edu 1415169Ssaidi@eecs.umich.edu public: 1422SN/A 1431858SN/A#if FULL_SYSTEM 1442SN/A Addr dbg_vtophys(Addr addr); 1452SN/A 1462SN/A bool interval_stats; 1472SN/A#endif 1482SN/A 1492SN/A // current instruction 1504181Sgblack@eecs.umich.edu TheISA::MachInst inst; 1514181Sgblack@eecs.umich.edu 1524182Sgblack@eecs.umich.edu // The predecoder 1534182Sgblack@eecs.umich.edu TheISA::Predecoder predecoder; 1542SN/A 1552107SN/A StaticInstPtr curStaticInst; 1563276Sgblack@eecs.umich.edu StaticInstPtr curMacroStaticInst; 1571469SN/A 1584377Sgblack@eecs.umich.edu //This is the offset from the current pc that fetch should be performed at 1594377Sgblack@eecs.umich.edu Addr fetchOffset; 1604377Sgblack@eecs.umich.edu //This flag says to stay at the current pc. This is useful for 1614377Sgblack@eecs.umich.edu //instructions which go beyond MachInst boundaries. 1624377Sgblack@eecs.umich.edu bool stayAtPC; 1634377Sgblack@eecs.umich.edu 1642623SN/A void checkForInterrupts(); 1655894Sgblack@eecs.umich.edu void setupFetchRequest(Request *req); 1662623SN/A void preExecute(); 1672623SN/A void postExecute(); 1682623SN/A void advancePC(Fault fault); 169180SN/A 170393SN/A virtual void deallocateContext(int thread_num); 171393SN/A virtual void haltContext(int thread_num); 1722SN/A 1732SN/A // statistics 174334SN/A virtual void regStats(); 175334SN/A virtual void resetStats(); 1762SN/A 1772SN/A // number of simulated instructions 1782SN/A Counter numInst; 179334SN/A Counter startNumInst; 1805999Snate@binkert.org Stats::Scalar numInsts; 181707SN/A 1824998Sgblack@eecs.umich.edu void countInst() 1834998Sgblack@eecs.umich.edu { 1844998Sgblack@eecs.umich.edu numInst++; 1854998Sgblack@eecs.umich.edu numInsts++; 1864998Sgblack@eecs.umich.edu 1874998Sgblack@eecs.umich.edu thread->funcExeInst++; 1884998Sgblack@eecs.umich.edu } 1894998Sgblack@eecs.umich.edu 190707SN/A virtual Counter totalInstructions() const 191707SN/A { 192707SN/A return numInst - startNumInst; 193707SN/A } 1942SN/A 1954564Sgblack@eecs.umich.edu // Mask to align PCs to MachInst sized boundaries 1964564Sgblack@eecs.umich.edu static const Addr PCMask = ~((Addr)sizeof(TheISA::MachInst) - 1); 1974564Sgblack@eecs.umich.edu 1982SN/A // number of simulated memory references 1995999Snate@binkert.org Stats::Scalar numMemRefs; 2002SN/A 201124SN/A // number of simulated loads 202124SN/A Counter numLoad; 203334SN/A Counter startNumLoad; 204124SN/A 2052SN/A // number of idle cycles 2065999Snate@binkert.org Stats::Average notIdleFraction; 207729SN/A Stats::Formula idleFraction; 2082SN/A 2092390SN/A // number of cycles stalled for I-cache responses 2105999Snate@binkert.org Stats::Scalar icacheStallCycles; 2112SN/A Counter lastIcacheStall; 2122SN/A 2132390SN/A // number of cycles stalled for I-cache retries 2145999Snate@binkert.org Stats::Scalar icacheRetryCycles; 2152390SN/A Counter lastIcacheRetry; 2162390SN/A 2172390SN/A // number of cycles stalled for D-cache responses 2185999Snate@binkert.org Stats::Scalar dcacheStallCycles; 2192SN/A Counter lastDcacheStall; 2202SN/A 2212390SN/A // number of cycles stalled for D-cache retries 2225999Snate@binkert.org Stats::Scalar dcacheRetryCycles; 2232390SN/A Counter lastDcacheRetry; 2242390SN/A 225217SN/A virtual void serialize(std::ostream &os); 226237SN/A virtual void unserialize(Checkpoint *cp, const std::string §ion); 2272SN/A 2281371SN/A // These functions are only used in CPU models that split 2291371SN/A // effective address computation from the actual memory access. 2302623SN/A void setEA(Addr EA) { panic("BaseSimpleCPU::setEA() not implemented\n"); } 2315543Ssaidi@eecs.umich.edu Addr getEA() { panic("BaseSimpleCPU::getEA() not implemented\n"); 2323918Ssaidi@eecs.umich.edu M5_DUMMY_RETURN} 2331371SN/A 234581SN/A void prefetch(Addr addr, unsigned flags) 2352SN/A { 2362SN/A // need to do this... 2372SN/A } 2382SN/A 239753SN/A void writeHint(Addr addr, int size, unsigned flags) 2402SN/A { 2412SN/A // need to do this... 2422SN/A } 243594SN/A 2444661Sksewell@umich.edu 245595SN/A Fault copySrcTranslate(Addr src); 246594SN/A 247595SN/A Fault copy(Addr dest); 248705SN/A 249726SN/A // The register accessor methods provide the index of the 250726SN/A // instruction's operand (e.g., 0 or 1), not the architectural 251726SN/A // register index, to simplify the implementation of register 252726SN/A // renaming. We find the architectural register index by indexing 253726SN/A // into the instruction's own operand index table. Note that a 254726SN/A // raw pointer to the StaticInst is provided instead of a 255726SN/A // ref-counted StaticInstPtr to redice overhead. This is fine as 256726SN/A // long as these methods don't copy the pointer into any long-term 257726SN/A // storage (which is pretty hard to imagine they would have reason 258726SN/A // to do). 259705SN/A 2603735Sstever@eecs.umich.edu uint64_t readIntRegOperand(const StaticInst *si, int idx) 261726SN/A { 2622683Sktlim@umich.edu return thread->readIntReg(si->srcRegIdx(idx)); 263726SN/A } 264705SN/A 2653735Sstever@eecs.umich.edu FloatReg readFloatRegOperand(const StaticInst *si, int idx, int width) 266726SN/A { 267726SN/A int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; 2682683Sktlim@umich.edu return thread->readFloatReg(reg_idx, width); 269726SN/A } 270705SN/A 2713735Sstever@eecs.umich.edu FloatReg readFloatRegOperand(const StaticInst *si, int idx) 272726SN/A { 273726SN/A int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; 2742683Sktlim@umich.edu return thread->readFloatReg(reg_idx); 275726SN/A } 276705SN/A 2773735Sstever@eecs.umich.edu FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx, 2783735Sstever@eecs.umich.edu int width) 279726SN/A { 280726SN/A int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; 2812683Sktlim@umich.edu return thread->readFloatRegBits(reg_idx, width); 2822455SN/A } 2832455SN/A 2843735Sstever@eecs.umich.edu FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx) 2852455SN/A { 2862455SN/A int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; 2872683Sktlim@umich.edu return thread->readFloatRegBits(reg_idx); 288726SN/A } 289705SN/A 2903735Sstever@eecs.umich.edu void setIntRegOperand(const StaticInst *si, int idx, uint64_t val) 291726SN/A { 2922683Sktlim@umich.edu thread->setIntReg(si->destRegIdx(idx), val); 293726SN/A } 294705SN/A 2953735Sstever@eecs.umich.edu void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val, 2963735Sstever@eecs.umich.edu int width) 297726SN/A { 298726SN/A int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; 2992683Sktlim@umich.edu thread->setFloatReg(reg_idx, val, width); 300726SN/A } 301705SN/A 3023735Sstever@eecs.umich.edu void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val) 303726SN/A { 304726SN/A int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; 3052683Sktlim@umich.edu thread->setFloatReg(reg_idx, val); 306726SN/A } 307726SN/A 3083735Sstever@eecs.umich.edu void setFloatRegOperandBits(const StaticInst *si, int idx, 3093735Sstever@eecs.umich.edu FloatRegBits val, int width) 310726SN/A { 311726SN/A int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; 3122683Sktlim@umich.edu thread->setFloatRegBits(reg_idx, val, width); 3132455SN/A } 3142455SN/A 3153735Sstever@eecs.umich.edu void setFloatRegOperandBits(const StaticInst *si, int idx, 3163735Sstever@eecs.umich.edu FloatRegBits val) 3172455SN/A { 3182455SN/A int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; 3192683Sktlim@umich.edu thread->setFloatRegBits(reg_idx, val); 320726SN/A } 321705SN/A 3222683Sktlim@umich.edu uint64_t readPC() { return thread->readPC(); } 3234950Sgblack@eecs.umich.edu uint64_t readMicroPC() { return thread->readMicroPC(); } 3242683Sktlim@umich.edu uint64_t readNextPC() { return thread->readNextPC(); } 3254950Sgblack@eecs.umich.edu uint64_t readNextMicroPC() { return thread->readNextMicroPC(); } 3262683Sktlim@umich.edu uint64_t readNextNPC() { return thread->readNextNPC(); } 3272447SN/A 3282683Sktlim@umich.edu void setPC(uint64_t val) { thread->setPC(val); } 3294950Sgblack@eecs.umich.edu void setMicroPC(uint64_t val) { thread->setMicroPC(val); } 3302683Sktlim@umich.edu void setNextPC(uint64_t val) { thread->setNextPC(val); } 3314950Sgblack@eecs.umich.edu void setNextMicroPC(uint64_t val) { thread->setNextMicroPC(val); } 3322683Sktlim@umich.edu void setNextNPC(uint64_t val) { thread->setNextNPC(val); } 333705SN/A 3344172Ssaidi@eecs.umich.edu MiscReg readMiscRegNoEffect(int misc_reg) 3354172Ssaidi@eecs.umich.edu { 3364172Ssaidi@eecs.umich.edu return thread->readMiscRegNoEffect(misc_reg); 3374172Ssaidi@eecs.umich.edu } 3384172Ssaidi@eecs.umich.edu 3392159SN/A MiscReg readMiscReg(int misc_reg) 3402159SN/A { 3412683Sktlim@umich.edu return thread->readMiscReg(misc_reg); 3422159SN/A } 343705SN/A 3444172Ssaidi@eecs.umich.edu void setMiscRegNoEffect(int misc_reg, const MiscReg &val) 3452159SN/A { 3464172Ssaidi@eecs.umich.edu return thread->setMiscRegNoEffect(misc_reg, val); 3472159SN/A } 3482159SN/A 3493468Sgblack@eecs.umich.edu void setMiscReg(int misc_reg, const MiscReg &val) 3502159SN/A { 3512683Sktlim@umich.edu return thread->setMiscReg(misc_reg, val); 3522159SN/A } 3532159SN/A 3544185Ssaidi@eecs.umich.edu MiscReg readMiscRegOperandNoEffect(const StaticInst *si, int idx) 3552159SN/A { 3564172Ssaidi@eecs.umich.edu int reg_idx = si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag; 3574172Ssaidi@eecs.umich.edu return thread->readMiscRegNoEffect(reg_idx); 3582159SN/A } 359705SN/A 3604185Ssaidi@eecs.umich.edu MiscReg readMiscRegOperand(const StaticInst *si, int idx) 3613792Sgblack@eecs.umich.edu { 3623792Sgblack@eecs.umich.edu int reg_idx = si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag; 3633792Sgblack@eecs.umich.edu return thread->readMiscReg(reg_idx); 3643792Sgblack@eecs.umich.edu } 3653792Sgblack@eecs.umich.edu 3664185Ssaidi@eecs.umich.edu void setMiscRegOperandNoEffect(const StaticInst *si, int idx, const MiscReg &val) 3673792Sgblack@eecs.umich.edu { 3683792Sgblack@eecs.umich.edu int reg_idx = si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag; 3694172Ssaidi@eecs.umich.edu return thread->setMiscRegNoEffect(reg_idx, val); 3703792Sgblack@eecs.umich.edu } 3713792Sgblack@eecs.umich.edu 3724185Ssaidi@eecs.umich.edu void setMiscRegOperand( 3733792Sgblack@eecs.umich.edu const StaticInst *si, int idx, const MiscReg &val) 3743792Sgblack@eecs.umich.edu { 3753792Sgblack@eecs.umich.edu int reg_idx = si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag; 3764172Ssaidi@eecs.umich.edu return thread->setMiscReg(reg_idx, val); 3773792Sgblack@eecs.umich.edu } 3783792Sgblack@eecs.umich.edu 3795358Sgblack@eecs.umich.edu void demapPage(Addr vaddr, uint64_t asn) 3805358Sgblack@eecs.umich.edu { 3815358Sgblack@eecs.umich.edu thread->demapPage(vaddr, asn); 3825358Sgblack@eecs.umich.edu } 3835358Sgblack@eecs.umich.edu 3845358Sgblack@eecs.umich.edu void demapInstPage(Addr vaddr, uint64_t asn) 3855358Sgblack@eecs.umich.edu { 3865358Sgblack@eecs.umich.edu thread->demapInstPage(vaddr, asn); 3875358Sgblack@eecs.umich.edu } 3885358Sgblack@eecs.umich.edu 3895358Sgblack@eecs.umich.edu void demapDataPage(Addr vaddr, uint64_t asn) 3905358Sgblack@eecs.umich.edu { 3915358Sgblack@eecs.umich.edu thread->demapDataPage(vaddr, asn); 3925358Sgblack@eecs.umich.edu } 3935358Sgblack@eecs.umich.edu 3944027Sstever@eecs.umich.edu unsigned readStCondFailures() { 3954027Sstever@eecs.umich.edu return thread->readStCondFailures(); 3964027Sstever@eecs.umich.edu } 3974027Sstever@eecs.umich.edu 3984027Sstever@eecs.umich.edu void setStCondFailures(unsigned sc_failures) { 3994027Sstever@eecs.umich.edu thread->setStCondFailures(sc_failures); 4004027Sstever@eecs.umich.edu } 4014027Sstever@eecs.umich.edu 4026221Snate@binkert.org MiscReg readRegOtherThread(int regIdx, ThreadID tid = InvalidThreadID) 4034661Sksewell@umich.edu { 4044661Sksewell@umich.edu panic("Simple CPU models do not support multithreaded " 4054661Sksewell@umich.edu "register access.\n"); 4064661Sksewell@umich.edu } 4074661Sksewell@umich.edu 4086221Snate@binkert.org void setRegOtherThread(int regIdx, const MiscReg &val, 4096221Snate@binkert.org ThreadID tid = InvalidThreadID) 4104661Sksewell@umich.edu { 4114661Sksewell@umich.edu panic("Simple CPU models do not support multithreaded " 4124661Sksewell@umich.edu "register access.\n"); 4134661Sksewell@umich.edu } 4144661Sksewell@umich.edu 4155250Sksewell@umich.edu //Fault CacheOp(uint8_t Op, Addr EA); 4165222Sksewell@umich.edu 4171858SN/A#if FULL_SYSTEM 4185702Ssaidi@eecs.umich.edu Fault hwrei() { return thread->hwrei(); } 4192680Sktlim@umich.edu void ev5_trap(Fault fault) { fault->invoke(tc); } 4205702Ssaidi@eecs.umich.edu bool simPalCheck(int palFunc) { return thread->simPalCheck(palFunc); } 421705SN/A#else 4222683Sktlim@umich.edu void syscall(int64_t callnum) { thread->syscall(callnum); } 423705SN/A#endif 424705SN/A 4252683Sktlim@umich.edu bool misspeculating() { return thread->misspeculating(); } 4262680Sktlim@umich.edu ThreadContext *tcBase() { return tc; } 4272SN/A}; 4282SN/A 4292623SN/A#endif // __CPU_SIMPLE_BASE_HH__ 430