base.hh revision 595
12SN/A/* 28733Sgeoffrey.blake@arm.com * Copyright (c) 2003 The Regents of The University of Michigan 37338SAli.Saidi@ARM.com * All rights reserved. 47338SAli.Saidi@ARM.com * 57338SAli.Saidi@ARM.com * Redistribution and use in source and binary forms, with or without 67338SAli.Saidi@ARM.com * modification, are permitted provided that the following conditions are 77338SAli.Saidi@ARM.com * met: redistributions of source code must retain the above copyright 87338SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer; 97338SAli.Saidi@ARM.com * redistributions in binary form must reproduce the above copyright 107338SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer in the 117338SAli.Saidi@ARM.com * documentation and/or other materials provided with the distribution; 127338SAli.Saidi@ARM.com * neither the name of the copyright holders nor the names of its 137338SAli.Saidi@ARM.com * contributors may be used to endorse or promote products derived from 141762SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272SN/A */ 282SN/A 292SN/A#ifndef __SIMPLE_CPU_HH__ 302SN/A#define __SIMPLE_CPU_HH__ 312SN/A 322SN/A#include "cpu/base_cpu.hh" 332SN/A#include "sim/eventq.hh" 342SN/A#include "base/loader/symtab.hh" 352SN/A#include "cpu/pc_event.hh" 362SN/A#include "base/statistics.hh" 372SN/A 382SN/A 392665Ssaidi@eecs.umich.edu// forward declarations 402665Ssaidi@eecs.umich.edu#ifdef FULL_SYSTEM 412SN/Aclass Processor; 422SN/Aclass Kernel; 438779Sgblack@eecs.umich.educlass AlphaItb; 448779Sgblack@eecs.umich.educlass AlphaDtb; 458779Sgblack@eecs.umich.educlass PhysicalMemory; 462439SN/A 478779Sgblack@eecs.umich.educlass RemoteGDB; 488229Snate@binkert.orgclass GDBListener; 496216Snate@binkert.org#endif // FULL_SYSTEM 50146SN/A 51146SN/Aclass MemInterface; 52146SN/Aclass Checkpoint; 53146SN/A 54146SN/Anamespace Trace { 55146SN/A class InstRecord; 566216Snate@binkert.org} 576658Snate@binkert.org 588733Sgeoffrey.blake@arm.comclass SimpleCPU : public BaseCPU 598229Snate@binkert.org{ 601717SN/A public: 61146SN/A // main simulation loop (one cycle) 621977SN/A void tick(); 632683Sktlim@umich.edu 641717SN/A private: 65146SN/A class TickEvent : public Event 662683Sktlim@umich.edu { 678232Snate@binkert.org private: 688232Snate@binkert.org SimpleCPU *cpu; 698232Snate@binkert.org 708779Sgblack@eecs.umich.edu public: 713348Sbinkertn@umich.edu TickEvent(SimpleCPU *c); 726105Ssteve.reinhardt@amd.com void process(); 736216Snate@binkert.org const char *description(); 742036SN/A }; 75146SN/A 768817Sgblack@eecs.umich.edu TickEvent tickEvent; 778793Sgblack@eecs.umich.edu 7856SN/A /// Schedule tick event, regardless of its current state. 7956SN/A void scheduleTickEvent(int delay) 80695SN/A { 812901Ssaidi@eecs.umich.edu if (tickEvent.squashed()) 822SN/A tickEvent.reschedule(curTick + delay); 838733Sgeoffrey.blake@arm.com else if (!tickEvent.scheduled()) 848733Sgeoffrey.blake@arm.com tickEvent.schedule(curTick + delay); 858733Sgeoffrey.blake@arm.com } 868733Sgeoffrey.blake@arm.com 878733Sgeoffrey.blake@arm.com /// Unschedule tick event, regardless of its current state. 882SN/A void unscheduleTickEvent() 892449SN/A { 901355SN/A if (tickEvent.scheduled()) 915529Snate@binkert.org tickEvent.squash(); 924495Sacolyte@umich.edu } 93224SN/A 948793Sgblack@eecs.umich.edu private: 958793Sgblack@eecs.umich.edu Trace::InstRecord *traceData; 968793Sgblack@eecs.umich.edu template<typename T> 978820Sgblack@eecs.umich.edu void trace_data(T data) { 988820Sgblack@eecs.umich.edu if (traceData) { 992SN/A traceData->setData(data); 1006029Ssteve.reinhardt@amd.com } 1012672Sktlim@umich.edu }; 1022683Sktlim@umich.edu 1032SN/A public: 1048733Sgeoffrey.blake@arm.com // 1058733Sgeoffrey.blake@arm.com enum Status { 1068733Sgeoffrey.blake@arm.com Running, 1078733Sgeoffrey.blake@arm.com Idle, 1088733Sgeoffrey.blake@arm.com IcacheMissStall, 1098733Sgeoffrey.blake@arm.com IcacheMissComplete, 1108733Sgeoffrey.blake@arm.com DcacheMissStall, 1118733Sgeoffrey.blake@arm.com SwitchedOut 1128733Sgeoffrey.blake@arm.com }; 1138733Sgeoffrey.blake@arm.com 1148733Sgeoffrey.blake@arm.com private: 1158733Sgeoffrey.blake@arm.com Status _status; 1168733Sgeoffrey.blake@arm.com 1172SN/A public: 118334SN/A void post_interrupt(int int_num, int index); 119140SN/A 120334SN/A void zero_fill_64(Addr addr) { 1212SN/A static int warned = 0; 1222SN/A if (!warned) { 1232SN/A warn ("WH64 is not implemented"); 1242680Sktlim@umich.edu warned = 1; 1254377Sgblack@eecs.umich.edu } 1265169Ssaidi@eecs.umich.edu }; 1274377Sgblack@eecs.umich.edu 1284377Sgblack@eecs.umich.edu#ifdef FULL_SYSTEM 1292SN/A 1302SN/A SimpleCPU(const std::string &_name, 1312623SN/A System *_system, 1322SN/A Counter max_insts_any_thread, Counter max_insts_all_threads, 1332SN/A Counter max_loads_any_thread, Counter max_loads_all_threads, 1342SN/A AlphaItb *itb, AlphaDtb *dtb, FunctionalMemory *mem, 135180SN/A MemInterface *icache_interface, MemInterface *dcache_interface, 1368737Skoansin.tan@gmail.com bool _def_reg, Tick freq); 137393SN/A 138393SN/A#else 139393SN/A 140393SN/A SimpleCPU(const std::string &_name, Process *_process, 141384SN/A Counter max_insts_any_thread, 142384SN/A Counter max_insts_all_threads, 143393SN/A Counter max_loads_any_thread, 1448737Skoansin.tan@gmail.com Counter max_loads_all_threads, 145393SN/A MemInterface *icache_interface, MemInterface *dcache_interface, 146393SN/A bool _def_reg); 147393SN/A 148393SN/A#endif 149384SN/A 150189SN/A virtual ~SimpleCPU(); 151189SN/A virtual void init(); 1522623SN/A 1532SN/A // execution context 154729SN/A ExecContext *xc; 155334SN/A 1562SN/A void switchOut(); 1572SN/A void takeOverFrom(BaseCPU *oldCPU); 1582SN/A 1592SN/A#ifdef FULL_SYSTEM 1602SN/A Addr dbg_vtophys(Addr addr); 1612SN/A 1622SN/A bool interval_stats; 1637897Shestness@cs.utexas.edu#endif 1647897Shestness@cs.utexas.edu 1657897Shestness@cs.utexas.edu // L1 instruction cache 1667897Shestness@cs.utexas.edu MemInterface *icacheInterface; 1677897Shestness@cs.utexas.edu 1687897Shestness@cs.utexas.edu // L1 data cache 1697897Shestness@cs.utexas.edu MemInterface *dcacheInterface; 1707897Shestness@cs.utexas.edu 1717897Shestness@cs.utexas.edu bool defer_registration; 1727897Shestness@cs.utexas.edu 1737897Shestness@cs.utexas.edu // current instruction 1747897Shestness@cs.utexas.edu MachInst inst; 1757897Shestness@cs.utexas.edu 1767897Shestness@cs.utexas.edu // Refcounted pointer to the one memory request. 1777897Shestness@cs.utexas.edu MemReqPtr memReq; 1787897Shestness@cs.utexas.edu 1797897Shestness@cs.utexas.edu class CacheCompletionEvent : public Event 1807897Shestness@cs.utexas.edu { 1817897Shestness@cs.utexas.edu private: 1827897Shestness@cs.utexas.edu SimpleCPU *cpu; 1837897Shestness@cs.utexas.edu 1847897Shestness@cs.utexas.edu public: 1857897Shestness@cs.utexas.edu CacheCompletionEvent(SimpleCPU *_cpu); 1867897Shestness@cs.utexas.edu 1877897Shestness@cs.utexas.edu virtual void process(); 1887897Shestness@cs.utexas.edu virtual const char *description(); 1897897Shestness@cs.utexas.edu }; 1907897Shestness@cs.utexas.edu 1917897Shestness@cs.utexas.edu CacheCompletionEvent cacheCompletionEvent; 1927897Shestness@cs.utexas.edu 1937897Shestness@cs.utexas.edu Status status() const { return _status; } 1947897Shestness@cs.utexas.edu 1957897Shestness@cs.utexas.edu virtual void activateContext(int thread_num, int delay); 1967897Shestness@cs.utexas.edu virtual void suspendContext(int thread_num); 1977897Shestness@cs.utexas.edu virtual void deallocateContext(int thread_num); 1987897Shestness@cs.utexas.edu virtual void haltContext(int thread_num); 1997897Shestness@cs.utexas.edu 2007897Shestness@cs.utexas.edu // statistics 2017897Shestness@cs.utexas.edu virtual void regStats(); 2027897Shestness@cs.utexas.edu virtual void resetStats(); 2037897Shestness@cs.utexas.edu 2047897Shestness@cs.utexas.edu // number of simulated instructions 2057897Shestness@cs.utexas.edu Counter numInst; 2067897Shestness@cs.utexas.edu Counter startNumInst; 2077897Shestness@cs.utexas.edu Statistics::Formula numInsts; 2087897Shestness@cs.utexas.edu 2097897Shestness@cs.utexas.edu // number of simulated memory references 2107897Shestness@cs.utexas.edu Statistics::Scalar<> numMemRefs; 2117897Shestness@cs.utexas.edu 2127897Shestness@cs.utexas.edu // number of simulated loads 2132SN/A Counter numLoad; 2147897Shestness@cs.utexas.edu Counter startNumLoad; 2157897Shestness@cs.utexas.edu 2167897Shestness@cs.utexas.edu // number of idle cycles 2177897Shestness@cs.utexas.edu Statistics::Average<> notIdleFraction; 2187897Shestness@cs.utexas.edu Statistics::Formula idleFraction; 2197897Shestness@cs.utexas.edu 2207897Shestness@cs.utexas.edu // number of cycles stalled for I-cache misses 2217897Shestness@cs.utexas.edu Statistics::Scalar<> icacheStallCycles; 2227897Shestness@cs.utexas.edu Counter lastIcacheStall; 2237897Shestness@cs.utexas.edu 2247897Shestness@cs.utexas.edu // number of cycles stalled for D-cache misses 2257897Shestness@cs.utexas.edu Statistics::Scalar<> dcacheStallCycles; 2262SN/A Counter lastDcacheStall; 2272SN/A 2281001SN/A void processCacheCompletion(); 2291001SN/A 2301001SN/A virtual void serialize(std::ostream &os); 2311001SN/A virtual void unserialize(Checkpoint *cp, const std::string §ion); 2321001SN/A 2332SN/A template <class T> 2342SN/A Fault read(Addr addr, T &data, unsigned flags); 2352SN/A 2362SN/A template <class T> 2372SN/A Fault write(T data, Addr addr, unsigned flags, 2387897Shestness@cs.utexas.edu uint64_t *res); 2397897Shestness@cs.utexas.edu 2407897Shestness@cs.utexas.edu void prefetch(Addr addr, unsigned flags) 2417897Shestness@cs.utexas.edu { 2427897Shestness@cs.utexas.edu // need to do this... 2437897Shestness@cs.utexas.edu } 2447897Shestness@cs.utexas.edu 2457897Shestness@cs.utexas.edu void writeHint(Addr addr, int size) 2467897Shestness@cs.utexas.edu { 2477897Shestness@cs.utexas.edu // need to do this... 2482SN/A } 2492SN/A 2502SN/A Fault copySrcTranslate(Addr src); 2512SN/A 2522SN/A Fault copy(Addr dest); 2532SN/A}; 2542SN/A 2552SN/A#endif // __SIMPLE_CPU_HH__ 2562SN/A