base.hh revision 5543
12SN/A/* 211147Smitch.hayenga@arm.com * Copyright (c) 2002-2005 The Regents of The University of Michigan 39920Syasuko.eckert@amd.com * All rights reserved. 47338SAli.Saidi@ARM.com * 57338SAli.Saidi@ARM.com * Redistribution and use in source and binary forms, with or without 67338SAli.Saidi@ARM.com * modification, are permitted provided that the following conditions are 77338SAli.Saidi@ARM.com * met: redistributions of source code must retain the above copyright 87338SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer; 97338SAli.Saidi@ARM.com * redistributions in binary form must reproduce the above copyright 107338SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer in the 117338SAli.Saidi@ARM.com * documentation and/or other materials provided with the distribution; 127338SAli.Saidi@ARM.com * neither the name of the copyright holders nor the names of its 137338SAli.Saidi@ARM.com * contributors may be used to endorse or promote products derived from 147338SAli.Saidi@ARM.com * this software without specific prior written permission. 151762SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272SN/A * 282SN/A * Authors: Steve Reinhardt 292SN/A * Dave Greene 302SN/A * Nathan Binkert 312SN/A */ 322SN/A 332SN/A#ifndef __CPU_SIMPLE_BASE_HH__ 342SN/A#define __CPU_SIMPLE_BASE_HH__ 352SN/A 362SN/A#include "arch/predecoder.hh" 372SN/A#include "base/statistics.hh" 382SN/A#include "config/full_system.hh" 392SN/A#include "cpu/base.hh" 402665Ssaidi@eecs.umich.edu#include "cpu/simple_thread.hh" 412665Ssaidi@eecs.umich.edu#include "cpu/pc_event.hh" 422SN/A#include "cpu/static_inst.hh" 432SN/A#include "mem/packet.hh" 448779Sgblack@eecs.umich.edu#include "mem/port.hh" 458779Sgblack@eecs.umich.edu#include "mem/request.hh" 468779Sgblack@eecs.umich.edu#include "sim/eventq.hh" 472439SN/A#include "sim/system.hh" 488779Sgblack@eecs.umich.edu 498229Snate@binkert.org// forward declarations 506216Snate@binkert.org#if FULL_SYSTEM 51146SN/Aclass Processor; 52146SN/Anamespace TheISA 53146SN/A{ 54146SN/A class ITB; 55146SN/A class DTB; 566216Snate@binkert.org} 576658Snate@binkert.orgclass MemObject; 588229Snate@binkert.org 591717SN/A#else 608887Sgeoffrey.blake@arm.com 618887Sgeoffrey.blake@arm.comclass Process; 62146SN/A 6310061Sandreas@sandberg.pp.se#endif // FULL_SYSTEM 641977SN/A 6511147Smitch.hayenga@arm.comclass RemoteGDB; 662683Sktlim@umich.educlass GDBListener; 671717SN/A 68146SN/Anamespace TheISA 692683Sktlim@umich.edu{ 708232Snate@binkert.org class Predecoder; 718232Snate@binkert.org} 728232Snate@binkert.orgclass ThreadContext; 738779Sgblack@eecs.umich.educlass Checkpoint; 743348Sbinkertn@umich.edu 756105Ssteve.reinhardt@amd.comnamespace Trace { 766216Snate@binkert.org class InstRecord; 772036SN/A} 78146SN/A 798817Sgblack@eecs.umich.educlass BaseSimpleCPUParams; 808793Sgblack@eecs.umich.edu 8156SN/A 8256SN/Aclass BaseSimpleCPU : public BaseCPU 83695SN/A{ 842901Ssaidi@eecs.umich.edu protected: 852SN/A typedef TheISA::MiscReg MiscReg; 862SN/A typedef TheISA::FloatReg FloatReg; 872449SN/A typedef TheISA::FloatRegBits FloatRegBits; 881355SN/A 895529Snate@binkert.org protected: 9010061Sandreas@sandberg.pp.se Trace::InstRecord *traceData; 9111147Smitch.hayenga@arm.com 9210061Sandreas@sandberg.pp.se inline void checkPcEventQueue() { 9311147Smitch.hayenga@arm.com Addr oldpc; 9411147Smitch.hayenga@arm.com do { 9511147Smitch.hayenga@arm.com oldpc = thread->readPC(); 96224SN/A system->pcEventQueue.service(tc); 9711147Smitch.hayenga@arm.com } while (oldpc != thread->readPC()); 982SN/A } 9911147Smitch.hayenga@arm.com 10011147Smitch.hayenga@arm.com public: 10111147Smitch.hayenga@arm.com void post_interrupt(int int_num, int index); 10211147Smitch.hayenga@arm.com 10311147Smitch.hayenga@arm.com void zero_fill_64(Addr addr) { 10411147Smitch.hayenga@arm.com static int warned = 0; 10511147Smitch.hayenga@arm.com if (!warned) { 10611147Smitch.hayenga@arm.com warn ("WH64 is not implemented"); 10711147Smitch.hayenga@arm.com warned = 1; 10811147Smitch.hayenga@arm.com } 10911147Smitch.hayenga@arm.com }; 11011147Smitch.hayenga@arm.com 1112SN/A public: 1128733Sgeoffrey.blake@arm.com BaseSimpleCPU(BaseSimpleCPUParams *params); 11311147Smitch.hayenga@arm.com virtual ~BaseSimpleCPU(); 11411147Smitch.hayenga@arm.com 11511147Smitch.hayenga@arm.com public: 1168733Sgeoffrey.blake@arm.com /** SimpleThread object, provides all the architectural state. */ 1178733Sgeoffrey.blake@arm.com SimpleThread *thread; 1188733Sgeoffrey.blake@arm.com 1198733Sgeoffrey.blake@arm.com /** ThreadContext object, provides an interface for external 12011147Smitch.hayenga@arm.com * objects to modify this thread's state. 12111147Smitch.hayenga@arm.com */ 1228733Sgeoffrey.blake@arm.com ThreadContext *tc; 1238733Sgeoffrey.blake@arm.com protected: 1248733Sgeoffrey.blake@arm.com int cpuId; 12511147Smitch.hayenga@arm.com 1268733Sgeoffrey.blake@arm.com enum Status { 12711147Smitch.hayenga@arm.com Idle, 12811147Smitch.hayenga@arm.com Running, 12911147Smitch.hayenga@arm.com IcacheRetry, 13011147Smitch.hayenga@arm.com IcacheWaitResponse, 1312SN/A IcacheWaitSwitch, 13211147Smitch.hayenga@arm.com DcacheRetry, 13311147Smitch.hayenga@arm.com DcacheWaitResponse, 13411147Smitch.hayenga@arm.com DcacheWaitSwitch, 1354377Sgblack@eecs.umich.edu SwitchedOut 13611147Smitch.hayenga@arm.com }; 13711147Smitch.hayenga@arm.com 13811147Smitch.hayenga@arm.com Status _status; 13911147Smitch.hayenga@arm.com 14011147Smitch.hayenga@arm.com public: 14111147Smitch.hayenga@arm.com 1425169Ssaidi@eecs.umich.edu#if FULL_SYSTEM 14311147Smitch.hayenga@arm.com Addr dbg_vtophys(Addr addr); 14411147Smitch.hayenga@arm.com 14511147Smitch.hayenga@arm.com bool interval_stats; 14611147Smitch.hayenga@arm.com#endif 14711147Smitch.hayenga@arm.com 14811147Smitch.hayenga@arm.com // current instruction 14911147Smitch.hayenga@arm.com TheISA::MachInst inst; 15011147Smitch.hayenga@arm.com 15111147Smitch.hayenga@arm.com // The predecoder 15211147Smitch.hayenga@arm.com TheISA::Predecoder predecoder; 15311147Smitch.hayenga@arm.com 15411147Smitch.hayenga@arm.com StaticInstPtr curStaticInst; 15511147Smitch.hayenga@arm.com StaticInstPtr curMacroStaticInst; 15611147Smitch.hayenga@arm.com 15711147Smitch.hayenga@arm.com //This is the offset from the current pc that fetch should be performed at 15811147Smitch.hayenga@arm.com Addr fetchOffset; 15911147Smitch.hayenga@arm.com //This flag says to stay at the current pc. This is useful for 16011147Smitch.hayenga@arm.com //instructions which go beyond MachInst boundaries. 16111147Smitch.hayenga@arm.com bool stayAtPC; 16211147Smitch.hayenga@arm.com 16311147Smitch.hayenga@arm.com void checkForInterrupts(); 16411147Smitch.hayenga@arm.com Fault setupFetchRequest(Request *req); 16511147Smitch.hayenga@arm.com void preExecute(); 16611147Smitch.hayenga@arm.com void postExecute(); 16711147Smitch.hayenga@arm.com void advancePC(Fault fault); 16811147Smitch.hayenga@arm.com 16911147Smitch.hayenga@arm.com virtual void deallocateContext(int thread_num); 17011147Smitch.hayenga@arm.com virtual void haltContext(int thread_num); 17111147Smitch.hayenga@arm.com 17211147Smitch.hayenga@arm.com // statistics 17311147Smitch.hayenga@arm.com virtual void regStats(); 17411147Smitch.hayenga@arm.com virtual void resetStats(); 17511147Smitch.hayenga@arm.com 17611147Smitch.hayenga@arm.com // number of simulated instructions 17711147Smitch.hayenga@arm.com Counter numInst; 17811147Smitch.hayenga@arm.com Counter startNumInst; 17911147Smitch.hayenga@arm.com Stats::Scalar<> numInsts; 18011147Smitch.hayenga@arm.com 18111147Smitch.hayenga@arm.com void countInst() 18211147Smitch.hayenga@arm.com { 18311147Smitch.hayenga@arm.com numInst++; 18411147Smitch.hayenga@arm.com numInsts++; 18511147Smitch.hayenga@arm.com 18611147Smitch.hayenga@arm.com thread->funcExeInst++; 18711147Smitch.hayenga@arm.com } 18811147Smitch.hayenga@arm.com 18911147Smitch.hayenga@arm.com virtual Counter totalInstructions() const 19011147Smitch.hayenga@arm.com { 19111147Smitch.hayenga@arm.com return numInst - startNumInst; 19211147Smitch.hayenga@arm.com } 19311147Smitch.hayenga@arm.com 19411147Smitch.hayenga@arm.com // Mask to align PCs to MachInst sized boundaries 19511147Smitch.hayenga@arm.com static const Addr PCMask = ~((Addr)sizeof(TheISA::MachInst) - 1); 19611147Smitch.hayenga@arm.com 19711147Smitch.hayenga@arm.com // number of simulated memory references 19811147Smitch.hayenga@arm.com Stats::Scalar<> numMemRefs; 19911147Smitch.hayenga@arm.com 20011147Smitch.hayenga@arm.com // number of simulated loads 20111147Smitch.hayenga@arm.com Counter numLoad; 20211147Smitch.hayenga@arm.com Counter startNumLoad; 20311147Smitch.hayenga@arm.com 20411147Smitch.hayenga@arm.com // number of idle cycles 20511147Smitch.hayenga@arm.com Stats::Average<> notIdleFraction; 2062SN/A Stats::Formula idleFraction; 2072SN/A 2082623SN/A // number of cycles stalled for I-cache responses 2092SN/A Stats::Scalar<> icacheStallCycles; 2102SN/A Counter lastIcacheStall; 2112SN/A 212180SN/A // number of cycles stalled for I-cache retries 2138737Skoansin.tan@gmail.com Stats::Scalar<> icacheRetryCycles; 214393SN/A Counter lastIcacheRetry; 215393SN/A 216393SN/A // number of cycles stalled for D-cache responses 217393SN/A Stats::Scalar<> dcacheStallCycles; 218384SN/A Counter lastDcacheStall; 219189SN/A 220189SN/A // number of cycles stalled for D-cache retries 2212623SN/A Stats::Scalar<> dcacheRetryCycles; 2222SN/A Counter lastDcacheRetry; 223729SN/A 224334SN/A virtual void serialize(std::ostream &os); 2252SN/A virtual void unserialize(Checkpoint *cp, const std::string §ion); 2262SN/A 22711147Smitch.hayenga@arm.com // These functions are only used in CPU models that split 22811147Smitch.hayenga@arm.com // effective address computation from the actual memory access. 2298834Satgutier@umich.edu void setEA(Addr EA) { panic("BaseSimpleCPU::setEA() not implemented\n"); } 23011147Smitch.hayenga@arm.com Addr getEA() { panic("BaseSimpleCPU::getEA() not implemented\n"); 23111147Smitch.hayenga@arm.com M5_DUMMY_RETURN} 23211147Smitch.hayenga@arm.com 2332SN/A void prefetch(Addr addr, unsigned flags) 23411147Smitch.hayenga@arm.com { 23511147Smitch.hayenga@arm.com // need to do this... 23611147Smitch.hayenga@arm.com } 23711147Smitch.hayenga@arm.com 2387897Shestness@cs.utexas.edu void writeHint(Addr addr, int size, unsigned flags) 23911147Smitch.hayenga@arm.com { 24011147Smitch.hayenga@arm.com // need to do this... 24111147Smitch.hayenga@arm.com } 24211147Smitch.hayenga@arm.com 2437897Shestness@cs.utexas.edu 24411147Smitch.hayenga@arm.com Fault copySrcTranslate(Addr src); 24511147Smitch.hayenga@arm.com 24611147Smitch.hayenga@arm.com Fault copy(Addr dest); 24711147Smitch.hayenga@arm.com 2487897Shestness@cs.utexas.edu // The register accessor methods provide the index of the 24911147Smitch.hayenga@arm.com // instruction's operand (e.g., 0 or 1), not the architectural 25011147Smitch.hayenga@arm.com // register index, to simplify the implementation of register 25111147Smitch.hayenga@arm.com // renaming. We find the architectural register index by indexing 25211147Smitch.hayenga@arm.com // into the instruction's own operand index table. Note that a 2537897Shestness@cs.utexas.edu // raw pointer to the StaticInst is provided instead of a 25411147Smitch.hayenga@arm.com // ref-counted StaticInstPtr to redice overhead. This is fine as 25511147Smitch.hayenga@arm.com // long as these methods don't copy the pointer into any long-term 25611147Smitch.hayenga@arm.com // storage (which is pretty hard to imagine they would have reason 25711147Smitch.hayenga@arm.com // to do). 2587897Shestness@cs.utexas.edu 25911147Smitch.hayenga@arm.com uint64_t readIntRegOperand(const StaticInst *si, int idx) 26011147Smitch.hayenga@arm.com { 26111147Smitch.hayenga@arm.com return thread->readIntReg(si->srcRegIdx(idx)); 26211147Smitch.hayenga@arm.com } 2637897Shestness@cs.utexas.edu 26411147Smitch.hayenga@arm.com FloatReg readFloatRegOperand(const StaticInst *si, int idx, int width) 26511147Smitch.hayenga@arm.com { 26611147Smitch.hayenga@arm.com int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; 26711147Smitch.hayenga@arm.com return thread->readFloatReg(reg_idx, width); 2687897Shestness@cs.utexas.edu } 26911147Smitch.hayenga@arm.com 27011147Smitch.hayenga@arm.com FloatReg readFloatRegOperand(const StaticInst *si, int idx) 27111147Smitch.hayenga@arm.com { 27211147Smitch.hayenga@arm.com int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; 2737897Shestness@cs.utexas.edu return thread->readFloatReg(reg_idx); 27411147Smitch.hayenga@arm.com } 27511147Smitch.hayenga@arm.com 27611147Smitch.hayenga@arm.com FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx, 27711147Smitch.hayenga@arm.com int width) 2787897Shestness@cs.utexas.edu { 27911147Smitch.hayenga@arm.com int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; 28011147Smitch.hayenga@arm.com return thread->readFloatRegBits(reg_idx, width); 28111147Smitch.hayenga@arm.com } 28211147Smitch.hayenga@arm.com 2837897Shestness@cs.utexas.edu FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx) 28411147Smitch.hayenga@arm.com { 28511147Smitch.hayenga@arm.com int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; 28611147Smitch.hayenga@arm.com return thread->readFloatRegBits(reg_idx); 28711147Smitch.hayenga@arm.com } 2889920Syasuko.eckert@amd.com 28911147Smitch.hayenga@arm.com void setIntRegOperand(const StaticInst *si, int idx, uint64_t val) 29011147Smitch.hayenga@arm.com { 29111147Smitch.hayenga@arm.com thread->setIntReg(si->destRegIdx(idx), val); 29211147Smitch.hayenga@arm.com } 2939920Syasuko.eckert@amd.com 29411147Smitch.hayenga@arm.com void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val, 29511147Smitch.hayenga@arm.com int width) 29611147Smitch.hayenga@arm.com { 29711147Smitch.hayenga@arm.com int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; 29811147Smitch.hayenga@arm.com thread->setFloatReg(reg_idx, val, width); 2997897Shestness@cs.utexas.edu } 30011147Smitch.hayenga@arm.com 30111147Smitch.hayenga@arm.com void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val) 30211147Smitch.hayenga@arm.com { 30311147Smitch.hayenga@arm.com int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; 30411147Smitch.hayenga@arm.com thread->setFloatReg(reg_idx, val); 3057897Shestness@cs.utexas.edu } 30611147Smitch.hayenga@arm.com 30711147Smitch.hayenga@arm.com void setFloatRegOperandBits(const StaticInst *si, int idx, 30811147Smitch.hayenga@arm.com FloatRegBits val, int width) 30911147Smitch.hayenga@arm.com { 3102SN/A int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; 31111147Smitch.hayenga@arm.com thread->setFloatRegBits(reg_idx, val, width); 31211147Smitch.hayenga@arm.com } 31311147Smitch.hayenga@arm.com 31411147Smitch.hayenga@arm.com void setFloatRegOperandBits(const StaticInst *si, int idx, 3151001SN/A FloatRegBits val) 31611147Smitch.hayenga@arm.com { 31711147Smitch.hayenga@arm.com int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; 31811147Smitch.hayenga@arm.com thread->setFloatRegBits(reg_idx, val); 31911147Smitch.hayenga@arm.com } 3202SN/A 32111147Smitch.hayenga@arm.com uint64_t readPC() { return thread->readPC(); } 32211147Smitch.hayenga@arm.com uint64_t readMicroPC() { return thread->readMicroPC(); } 32311147Smitch.hayenga@arm.com uint64_t readNextPC() { return thread->readNextPC(); } 32411147Smitch.hayenga@arm.com uint64_t readNextMicroPC() { return thread->readNextMicroPC(); } 3257897Shestness@cs.utexas.edu uint64_t readNextNPC() { return thread->readNextNPC(); } 32611147Smitch.hayenga@arm.com 32711147Smitch.hayenga@arm.com void setPC(uint64_t val) { thread->setPC(val); } 32811147Smitch.hayenga@arm.com void setMicroPC(uint64_t val) { thread->setMicroPC(val); } 32911147Smitch.hayenga@arm.com void setNextPC(uint64_t val) { thread->setNextPC(val); } 3307897Shestness@cs.utexas.edu void setNextMicroPC(uint64_t val) { thread->setNextMicroPC(val); } 33111147Smitch.hayenga@arm.com void setNextNPC(uint64_t val) { thread->setNextNPC(val); } 33211147Smitch.hayenga@arm.com 33311147Smitch.hayenga@arm.com MiscReg readMiscRegNoEffect(int misc_reg) 33411147Smitch.hayenga@arm.com { 3352SN/A return thread->readMiscRegNoEffect(misc_reg); 33611147Smitch.hayenga@arm.com } 33711147Smitch.hayenga@arm.com 33811147Smitch.hayenga@arm.com MiscReg readMiscReg(int misc_reg) 33911147Smitch.hayenga@arm.com { 3402SN/A return thread->readMiscReg(misc_reg); 34111147Smitch.hayenga@arm.com } 34211147Smitch.hayenga@arm.com 34311147Smitch.hayenga@arm.com void setMiscRegNoEffect(int misc_reg, const MiscReg &val) 34411147Smitch.hayenga@arm.com { 34511147Smitch.hayenga@arm.com return thread->setMiscRegNoEffect(misc_reg, val); 34611147Smitch.hayenga@arm.com } 34711147Smitch.hayenga@arm.com 34811147Smitch.hayenga@arm.com void setMiscReg(int misc_reg, const MiscReg &val) 34911147Smitch.hayenga@arm.com { 35011147Smitch.hayenga@arm.com return thread->setMiscReg(misc_reg, val); 35111147Smitch.hayenga@arm.com } 35211147Smitch.hayenga@arm.com 35311147Smitch.hayenga@arm.com MiscReg readMiscRegOperandNoEffect(const StaticInst *si, int idx) 35411147Smitch.hayenga@arm.com { 35511147Smitch.hayenga@arm.com int reg_idx = si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag; 35611147Smitch.hayenga@arm.com return thread->readMiscRegNoEffect(reg_idx); 35711147Smitch.hayenga@arm.com } 35811147Smitch.hayenga@arm.com 35911147Smitch.hayenga@arm.com MiscReg readMiscRegOperand(const StaticInst *si, int idx) 36011147Smitch.hayenga@arm.com { 36111147Smitch.hayenga@arm.com int reg_idx = si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag; 36211147Smitch.hayenga@arm.com return thread->readMiscReg(reg_idx); 36311147Smitch.hayenga@arm.com } 36411147Smitch.hayenga@arm.com 36511147Smitch.hayenga@arm.com void setMiscRegOperandNoEffect(const StaticInst *si, int idx, const MiscReg &val) 36611147Smitch.hayenga@arm.com { 36711147Smitch.hayenga@arm.com int reg_idx = si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag; 36811147Smitch.hayenga@arm.com return thread->setMiscRegNoEffect(reg_idx, val); 36911147Smitch.hayenga@arm.com } 37011147Smitch.hayenga@arm.com 37111147Smitch.hayenga@arm.com void setMiscRegOperand( 37211147Smitch.hayenga@arm.com const StaticInst *si, int idx, const MiscReg &val) 37311147Smitch.hayenga@arm.com { 37411147Smitch.hayenga@arm.com int reg_idx = si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag; 37511147Smitch.hayenga@arm.com return thread->setMiscReg(reg_idx, val); 37611147Smitch.hayenga@arm.com } 37711147Smitch.hayenga@arm.com 37811147Smitch.hayenga@arm.com void demapPage(Addr vaddr, uint64_t asn) 37911147Smitch.hayenga@arm.com { 38011147Smitch.hayenga@arm.com thread->demapPage(vaddr, asn); 38111147Smitch.hayenga@arm.com } 38210193SCurtis.Dunham@arm.com 3832SN/A void demapInstPage(Addr vaddr, uint64_t asn) 3842SN/A { 3852SN/A thread->demapInstPage(vaddr, asn); 3862623SN/A } 387334SN/A 38811147Smitch.hayenga@arm.com void demapDataPage(Addr vaddr, uint64_t asn) 38911147Smitch.hayenga@arm.com { 39011147Smitch.hayenga@arm.com thread->demapDataPage(vaddr, asn); 391334SN/A } 392334SN/A 393334SN/A unsigned readStCondFailures() { 39410905Sandreas.sandberg@arm.com return thread->readStCondFailures(); 3952SN/A } 3969448SAndreas.Sandberg@ARM.com 3979448SAndreas.Sandberg@ARM.com void setStCondFailures(unsigned sc_failures) { 39811147Smitch.hayenga@arm.com thread->setStCondFailures(sc_failures); 3992SN/A } 4002SN/A 4012SN/A MiscReg readRegOtherThread(int regIdx, int tid = -1) 40210905Sandreas.sandberg@arm.com { 4032SN/A panic("Simple CPU models do not support multithreaded " 40411147Smitch.hayenga@arm.com "register access.\n"); 4052SN/A } 4062SN/A 4072SN/A void setRegOtherThread(int regIdx, const MiscReg &val, int tid = -1) 4086221Snate@binkert.org { 4092SN/A panic("Simple CPU models do not support multithreaded " 4102SN/A "register access.\n"); 4112SN/A } 4122SN/A 4132623SN/A //Fault CacheOp(uint8_t Op, Addr EA); 4142SN/A 41511147Smitch.hayenga@arm.com#if FULL_SYSTEM 4162SN/A Fault hwrei() { return thread->hwrei(); } 4172SN/A void ev5_trap(Fault fault) { fault->invoke(tc); } 4182SN/A bool simPalCheck(int palFunc) { return thread->simPalCheck(palFunc); } 41911151Smitch.hayenga@arm.com#else 4202SN/A void syscall(int64_t callnum) { thread->syscall(callnum); } 42111151Smitch.hayenga@arm.com#endif 42211151Smitch.hayenga@arm.com 42311151Smitch.hayenga@arm.com bool misspeculating() { return thread->misspeculating(); } 42411151Smitch.hayenga@arm.com ThreadContext *tcBase() { return tc; } 42511151Smitch.hayenga@arm.com}; 42611147Smitch.hayenga@arm.com 4272SN/A#endif // __CPU_SIMPLE_BASE_HH__ 4282SN/A