base.hh revision 4181
12SN/A/* 21762SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 292665Ssaidi@eecs.umich.edu * Dave Greene 302665Ssaidi@eecs.umich.edu * Nathan Binkert 312SN/A */ 322SN/A 332623SN/A#ifndef __CPU_SIMPLE_BASE_HH__ 342623SN/A#define __CPU_SIMPLE_BASE_HH__ 352SN/A 361354SN/A#include "base/statistics.hh" 371858SN/A#include "config/full_system.hh" 381717SN/A#include "cpu/base.hh" 392683Sktlim@umich.edu#include "cpu/simple_thread.hh" 401354SN/A#include "cpu/pc_event.hh" 411354SN/A#include "cpu/static_inst.hh" 422387SN/A#include "mem/packet.hh" 432387SN/A#include "mem/port.hh" 442387SN/A#include "mem/request.hh" 4556SN/A#include "sim/eventq.hh" 462SN/A 472SN/A// forward declarations 481858SN/A#if FULL_SYSTEM 492SN/Aclass Processor; 503453Sgblack@eecs.umich.edunamespace TheISA 513453Sgblack@eecs.umich.edu{ 523453Sgblack@eecs.umich.edu class ITB; 533453Sgblack@eecs.umich.edu class DTB; 543453Sgblack@eecs.umich.edu} 552462SN/Aclass MemObject; 562SN/A 57715SN/A#else 58715SN/A 59715SN/Aclass Process; 60715SN/A 612SN/A#endif // FULL_SYSTEM 622SN/A 633960Sgblack@eecs.umich.educlass RemoteGDB; 643960Sgblack@eecs.umich.educlass GDBListener; 653960Sgblack@eecs.umich.edu 662680Sktlim@umich.educlass ThreadContext; 67237SN/Aclass Checkpoint; 682SN/A 692SN/Anamespace Trace { 702SN/A class InstRecord; 712SN/A} 722SN/A 732420SN/A 742623SN/Aclass BaseSimpleCPU : public BaseCPU 752SN/A{ 762107SN/A protected: 772159SN/A typedef TheISA::MiscReg MiscReg; 782455SN/A typedef TheISA::FloatReg FloatReg; 792455SN/A typedef TheISA::FloatRegBits FloatRegBits; 802386SN/A 812623SN/A protected: 822SN/A Trace::InstRecord *traceData; 831371SN/A 842SN/A public: 852SN/A void post_interrupt(int int_num, int index); 862SN/A 872SN/A void zero_fill_64(Addr addr) { 882SN/A static int warned = 0; 892SN/A if (!warned) { 902SN/A warn ("WH64 is not implemented"); 912SN/A warned = 1; 922SN/A } 932SN/A }; 942SN/A 951400SN/A public: 961400SN/A struct Params : public BaseCPU::Params 971400SN/A { 981858SN/A#if FULL_SYSTEM 993453Sgblack@eecs.umich.edu TheISA::ITB *itb; 1003453Sgblack@eecs.umich.edu TheISA::DTB *dtb; 1012SN/A#else 1021400SN/A Process *process; 1032SN/A#endif 1041400SN/A }; 1052623SN/A BaseSimpleCPU(Params *params); 1062623SN/A virtual ~BaseSimpleCPU(); 1072SN/A 1081400SN/A public: 1092683Sktlim@umich.edu /** SimpleThread object, provides all the architectural state. */ 1102683Sktlim@umich.edu SimpleThread *thread; 1112190SN/A 1122683Sktlim@umich.edu /** ThreadContext object, provides an interface for external 1132683Sktlim@umich.edu * objects to modify this thread's state. 1142683Sktlim@umich.edu */ 1152680Sktlim@umich.edu ThreadContext *tc; 1162SN/A 1171858SN/A#if FULL_SYSTEM 1182SN/A Addr dbg_vtophys(Addr addr); 1192SN/A 1202SN/A bool interval_stats; 1212SN/A#endif 1222SN/A 1232SN/A // current instruction 1244181Sgblack@eecs.umich.edu TheISA::MachInst inst; 1254181Sgblack@eecs.umich.edu 1264181Sgblack@eecs.umich.edu // current extended machine instruction 1274181Sgblack@eecs.umich.edu TheISA::ExtMachInst extMachInst; 1282SN/A 1292566SN/A // Static data storage 1304040Ssaidi@eecs.umich.edu TheISA::LargestRead dataReg; 1312566SN/A 1322107SN/A StaticInstPtr curStaticInst; 1333276Sgblack@eecs.umich.edu StaticInstPtr curMacroStaticInst; 1341469SN/A 1352623SN/A void checkForInterrupts(); 1362662Sstever@eecs.umich.edu Fault setupFetchRequest(Request *req); 1372623SN/A void preExecute(); 1382623SN/A void postExecute(); 1392623SN/A void advancePC(Fault fault); 140180SN/A 141393SN/A virtual void deallocateContext(int thread_num); 142393SN/A virtual void haltContext(int thread_num); 1432SN/A 1442SN/A // statistics 145334SN/A virtual void regStats(); 146334SN/A virtual void resetStats(); 1472SN/A 1482SN/A // number of simulated instructions 1492SN/A Counter numInst; 150334SN/A Counter startNumInst; 151729SN/A Stats::Scalar<> numInsts; 152707SN/A 153707SN/A virtual Counter totalInstructions() const 154707SN/A { 155707SN/A return numInst - startNumInst; 156707SN/A } 1572SN/A 1582SN/A // number of simulated memory references 159729SN/A Stats::Scalar<> numMemRefs; 1602SN/A 161124SN/A // number of simulated loads 162124SN/A Counter numLoad; 163334SN/A Counter startNumLoad; 164124SN/A 1652SN/A // number of idle cycles 166729SN/A Stats::Average<> notIdleFraction; 167729SN/A Stats::Formula idleFraction; 1682SN/A 1692390SN/A // number of cycles stalled for I-cache responses 170729SN/A Stats::Scalar<> icacheStallCycles; 1712SN/A Counter lastIcacheStall; 1722SN/A 1732390SN/A // number of cycles stalled for I-cache retries 1742390SN/A Stats::Scalar<> icacheRetryCycles; 1752390SN/A Counter lastIcacheRetry; 1762390SN/A 1772390SN/A // number of cycles stalled for D-cache responses 178729SN/A Stats::Scalar<> dcacheStallCycles; 1792SN/A Counter lastDcacheStall; 1802SN/A 1812390SN/A // number of cycles stalled for D-cache retries 1822390SN/A Stats::Scalar<> dcacheRetryCycles; 1832390SN/A Counter lastDcacheRetry; 1842390SN/A 185217SN/A virtual void serialize(std::ostream &os); 186237SN/A virtual void unserialize(Checkpoint *cp, const std::string §ion); 1872SN/A 1881371SN/A // These functions are only used in CPU models that split 1891371SN/A // effective address computation from the actual memory access. 1902623SN/A void setEA(Addr EA) { panic("BaseSimpleCPU::setEA() not implemented\n"); } 1913918Ssaidi@eecs.umich.edu Addr getEA() { panic("BaseSimpleCPU::getEA() not implemented\n"); 1923918Ssaidi@eecs.umich.edu M5_DUMMY_RETURN} 1931371SN/A 194581SN/A void prefetch(Addr addr, unsigned flags) 1952SN/A { 1962SN/A // need to do this... 1972SN/A } 1982SN/A 199753SN/A void writeHint(Addr addr, int size, unsigned flags) 2002SN/A { 2012SN/A // need to do this... 2022SN/A } 203594SN/A 204595SN/A Fault copySrcTranslate(Addr src); 205594SN/A 206595SN/A Fault copy(Addr dest); 207705SN/A 208726SN/A // The register accessor methods provide the index of the 209726SN/A // instruction's operand (e.g., 0 or 1), not the architectural 210726SN/A // register index, to simplify the implementation of register 211726SN/A // renaming. We find the architectural register index by indexing 212726SN/A // into the instruction's own operand index table. Note that a 213726SN/A // raw pointer to the StaticInst is provided instead of a 214726SN/A // ref-counted StaticInstPtr to redice overhead. This is fine as 215726SN/A // long as these methods don't copy the pointer into any long-term 216726SN/A // storage (which is pretty hard to imagine they would have reason 217726SN/A // to do). 218705SN/A 2193735Sstever@eecs.umich.edu uint64_t readIntRegOperand(const StaticInst *si, int idx) 220726SN/A { 2212683Sktlim@umich.edu return thread->readIntReg(si->srcRegIdx(idx)); 222726SN/A } 223705SN/A 2243735Sstever@eecs.umich.edu FloatReg readFloatRegOperand(const StaticInst *si, int idx, int width) 225726SN/A { 226726SN/A int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; 2272683Sktlim@umich.edu return thread->readFloatReg(reg_idx, width); 228726SN/A } 229705SN/A 2303735Sstever@eecs.umich.edu FloatReg readFloatRegOperand(const StaticInst *si, int idx) 231726SN/A { 232726SN/A int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; 2332683Sktlim@umich.edu return thread->readFloatReg(reg_idx); 234726SN/A } 235705SN/A 2363735Sstever@eecs.umich.edu FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx, 2373735Sstever@eecs.umich.edu int width) 238726SN/A { 239726SN/A int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; 2402683Sktlim@umich.edu return thread->readFloatRegBits(reg_idx, width); 2412455SN/A } 2422455SN/A 2433735Sstever@eecs.umich.edu FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx) 2442455SN/A { 2452455SN/A int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; 2462683Sktlim@umich.edu return thread->readFloatRegBits(reg_idx); 247726SN/A } 248705SN/A 2493735Sstever@eecs.umich.edu void setIntRegOperand(const StaticInst *si, int idx, uint64_t val) 250726SN/A { 2512683Sktlim@umich.edu thread->setIntReg(si->destRegIdx(idx), val); 252726SN/A } 253705SN/A 2543735Sstever@eecs.umich.edu void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val, 2553735Sstever@eecs.umich.edu int width) 256726SN/A { 257726SN/A int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; 2582683Sktlim@umich.edu thread->setFloatReg(reg_idx, val, width); 259726SN/A } 260705SN/A 2613735Sstever@eecs.umich.edu void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val) 262726SN/A { 263726SN/A int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; 2642683Sktlim@umich.edu thread->setFloatReg(reg_idx, val); 265726SN/A } 266726SN/A 2673735Sstever@eecs.umich.edu void setFloatRegOperandBits(const StaticInst *si, int idx, 2683735Sstever@eecs.umich.edu FloatRegBits val, int width) 269726SN/A { 270726SN/A int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; 2712683Sktlim@umich.edu thread->setFloatRegBits(reg_idx, val, width); 2722455SN/A } 2732455SN/A 2743735Sstever@eecs.umich.edu void setFloatRegOperandBits(const StaticInst *si, int idx, 2753735Sstever@eecs.umich.edu FloatRegBits val) 2762455SN/A { 2772455SN/A int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; 2782683Sktlim@umich.edu thread->setFloatRegBits(reg_idx, val); 279726SN/A } 280705SN/A 2812683Sktlim@umich.edu uint64_t readPC() { return thread->readPC(); } 2822683Sktlim@umich.edu uint64_t readNextPC() { return thread->readNextPC(); } 2832683Sktlim@umich.edu uint64_t readNextNPC() { return thread->readNextNPC(); } 2842447SN/A 2852683Sktlim@umich.edu void setPC(uint64_t val) { thread->setPC(val); } 2862683Sktlim@umich.edu void setNextPC(uint64_t val) { thread->setNextPC(val); } 2872683Sktlim@umich.edu void setNextNPC(uint64_t val) { thread->setNextNPC(val); } 288705SN/A 2894172Ssaidi@eecs.umich.edu MiscReg readMiscRegNoEffect(int misc_reg) 2904172Ssaidi@eecs.umich.edu { 2914172Ssaidi@eecs.umich.edu return thread->readMiscRegNoEffect(misc_reg); 2924172Ssaidi@eecs.umich.edu } 2934172Ssaidi@eecs.umich.edu 2942159SN/A MiscReg readMiscReg(int misc_reg) 2952159SN/A { 2962683Sktlim@umich.edu return thread->readMiscReg(misc_reg); 2972159SN/A } 298705SN/A 2994172Ssaidi@eecs.umich.edu void setMiscRegNoEffect(int misc_reg, const MiscReg &val) 3002159SN/A { 3014172Ssaidi@eecs.umich.edu return thread->setMiscRegNoEffect(misc_reg, val); 3022159SN/A } 3032159SN/A 3043468Sgblack@eecs.umich.edu void setMiscReg(int misc_reg, const MiscReg &val) 3052159SN/A { 3062683Sktlim@umich.edu return thread->setMiscReg(misc_reg, val); 3072159SN/A } 3082159SN/A 3094172Ssaidi@eecs.umich.edu MiscReg readMiscRegOperand(const StaticInst *si, int idx) 3102159SN/A { 3114172Ssaidi@eecs.umich.edu int reg_idx = si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag; 3124172Ssaidi@eecs.umich.edu return thread->readMiscRegNoEffect(reg_idx); 3132159SN/A } 314705SN/A 3154172Ssaidi@eecs.umich.edu MiscReg readMiscRegOperandWithEffect(const StaticInst *si, int idx) 3163792Sgblack@eecs.umich.edu { 3173792Sgblack@eecs.umich.edu int reg_idx = si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag; 3183792Sgblack@eecs.umich.edu return thread->readMiscReg(reg_idx); 3193792Sgblack@eecs.umich.edu } 3203792Sgblack@eecs.umich.edu 3213792Sgblack@eecs.umich.edu void setMiscRegOperand(const StaticInst *si, int idx, const MiscReg &val) 3223792Sgblack@eecs.umich.edu { 3233792Sgblack@eecs.umich.edu int reg_idx = si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag; 3244172Ssaidi@eecs.umich.edu return thread->setMiscRegNoEffect(reg_idx, val); 3253792Sgblack@eecs.umich.edu } 3263792Sgblack@eecs.umich.edu 3273792Sgblack@eecs.umich.edu void setMiscRegOperandWithEffect( 3283792Sgblack@eecs.umich.edu const StaticInst *si, int idx, const MiscReg &val) 3293792Sgblack@eecs.umich.edu { 3303792Sgblack@eecs.umich.edu int reg_idx = si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag; 3314172Ssaidi@eecs.umich.edu return thread->setMiscReg(reg_idx, val); 3323792Sgblack@eecs.umich.edu } 3333792Sgblack@eecs.umich.edu 3344027Sstever@eecs.umich.edu unsigned readStCondFailures() { 3354027Sstever@eecs.umich.edu return thread->readStCondFailures(); 3364027Sstever@eecs.umich.edu } 3374027Sstever@eecs.umich.edu 3384027Sstever@eecs.umich.edu void setStCondFailures(unsigned sc_failures) { 3394027Sstever@eecs.umich.edu thread->setStCondFailures(sc_failures); 3404027Sstever@eecs.umich.edu } 3414027Sstever@eecs.umich.edu 3421858SN/A#if FULL_SYSTEM 3432683Sktlim@umich.edu Fault hwrei() { return thread->hwrei(); } 3442680Sktlim@umich.edu void ev5_trap(Fault fault) { fault->invoke(tc); } 3452683Sktlim@umich.edu bool simPalCheck(int palFunc) { return thread->simPalCheck(palFunc); } 346705SN/A#else 3472683Sktlim@umich.edu void syscall(int64_t callnum) { thread->syscall(callnum); } 348705SN/A#endif 349705SN/A 3502683Sktlim@umich.edu bool misspeculating() { return thread->misspeculating(); } 3512680Sktlim@umich.edu ThreadContext *tcBase() { return tc; } 3522SN/A}; 3532SN/A 3542623SN/A#endif // __CPU_SIMPLE_BASE_HH__ 355