base.hh revision 393
16019Shines@cs.fsu.edu/* 26019Shines@cs.fsu.edu * Copyright (c) 2003 The Regents of The University of Michigan 36019Shines@cs.fsu.edu * All rights reserved. 46019Shines@cs.fsu.edu * 56019Shines@cs.fsu.edu * Redistribution and use in source and binary forms, with or without 66019Shines@cs.fsu.edu * modification, are permitted provided that the following conditions are 76019Shines@cs.fsu.edu * met: redistributions of source code must retain the above copyright 86019Shines@cs.fsu.edu * notice, this list of conditions and the following disclaimer; 96019Shines@cs.fsu.edu * redistributions in binary form must reproduce the above copyright 106019Shines@cs.fsu.edu * notice, this list of conditions and the following disclaimer in the 116019Shines@cs.fsu.edu * documentation and/or other materials provided with the distribution; 126019Shines@cs.fsu.edu * neither the name of the copyright holders nor the names of its 136019Shines@cs.fsu.edu * contributors may be used to endorse or promote products derived from 146019Shines@cs.fsu.edu * this software without specific prior written permission. 156019Shines@cs.fsu.edu * 166019Shines@cs.fsu.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 176019Shines@cs.fsu.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 186019Shines@cs.fsu.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 196019Shines@cs.fsu.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 206019Shines@cs.fsu.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 216019Shines@cs.fsu.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 226019Shines@cs.fsu.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 236019Shines@cs.fsu.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 246019Shines@cs.fsu.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 256019Shines@cs.fsu.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 266019Shines@cs.fsu.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 276019Shines@cs.fsu.edu */ 286019Shines@cs.fsu.edu 296019Shines@cs.fsu.edu#ifndef __SIMPLE_CPU_HH__ 306019Shines@cs.fsu.edu#define __SIMPLE_CPU_HH__ 316019Shines@cs.fsu.edu 326019Shines@cs.fsu.edu#include "cpu/base_cpu.hh" 336019Shines@cs.fsu.edu#include "sim/eventq.hh" 346019Shines@cs.fsu.edu#include "base/loader/symtab.hh" 356019Shines@cs.fsu.edu#include "cpu/pc_event.hh" 366019Shines@cs.fsu.edu#include "base/statistics.hh" 376019Shines@cs.fsu.edu 386019Shines@cs.fsu.edu 396019Shines@cs.fsu.edu// forward declarations 406019Shines@cs.fsu.edu#ifdef FULL_SYSTEM 416019Shines@cs.fsu.educlass Processor; 426019Shines@cs.fsu.educlass Kernel; 436019Shines@cs.fsu.educlass AlphaItb; 446019Shines@cs.fsu.educlass AlphaDtb; 456019Shines@cs.fsu.educlass PhysicalMemory; 466019Shines@cs.fsu.edu 476019Shines@cs.fsu.educlass RemoteGDB; 486019Shines@cs.fsu.educlass GDBListener; 496019Shines@cs.fsu.edu#endif // FULL_SYSTEM 506019Shines@cs.fsu.edu 516019Shines@cs.fsu.educlass MemInterface; 526019Shines@cs.fsu.educlass Checkpoint; 536019Shines@cs.fsu.edu 546019Shines@cs.fsu.edunamespace Trace { 556019Shines@cs.fsu.edu class InstRecord; 566019Shines@cs.fsu.edu} 576019Shines@cs.fsu.edu 586019Shines@cs.fsu.educlass SimpleCPU : public BaseCPU 596019Shines@cs.fsu.edu{ 606019Shines@cs.fsu.edu public: 616019Shines@cs.fsu.edu // main simulation loop (one cycle) 626019Shines@cs.fsu.edu void tick(); 636019Shines@cs.fsu.edu 646019Shines@cs.fsu.edu private: 656019Shines@cs.fsu.edu class TickEvent : public Event 666019Shines@cs.fsu.edu { 676019Shines@cs.fsu.edu private: 686019Shines@cs.fsu.edu SimpleCPU *cpu; 696019Shines@cs.fsu.edu 706019Shines@cs.fsu.edu public: 716019Shines@cs.fsu.edu TickEvent(SimpleCPU *c); 726019Shines@cs.fsu.edu void process(); 736019Shines@cs.fsu.edu const char *description(); 746019Shines@cs.fsu.edu }; 756019Shines@cs.fsu.edu 766019Shines@cs.fsu.edu TickEvent tickEvent; 776019Shines@cs.fsu.edu 786019Shines@cs.fsu.edu /// Schedule tick event, regardless of its current state. 796019Shines@cs.fsu.edu void scheduleTickEvent(int delay) 806019Shines@cs.fsu.edu { 816019Shines@cs.fsu.edu if (tickEvent.squashed()) 826019Shines@cs.fsu.edu tickEvent.reschedule(curTick + delay); 836019Shines@cs.fsu.edu else if (!tickEvent.scheduled()) 846019Shines@cs.fsu.edu tickEvent.schedule(curTick + delay); 856019Shines@cs.fsu.edu } 866019Shines@cs.fsu.edu 876019Shines@cs.fsu.edu /// Unschedule tick event, regardless of its current state. 886019Shines@cs.fsu.edu void unscheduleTickEvent() 896019Shines@cs.fsu.edu { 906019Shines@cs.fsu.edu if (tickEvent.scheduled()) 916019Shines@cs.fsu.edu tickEvent.squash(); 926019Shines@cs.fsu.edu } 936019Shines@cs.fsu.edu 946019Shines@cs.fsu.edu private: 956019Shines@cs.fsu.edu Trace::InstRecord *traceData; 966019Shines@cs.fsu.edu template<typename T> 976019Shines@cs.fsu.edu void trace_data(T data) { 986019Shines@cs.fsu.edu if (traceData) { 996019Shines@cs.fsu.edu traceData->setData(data); 1006019Shines@cs.fsu.edu } 1016019Shines@cs.fsu.edu }; 1026019Shines@cs.fsu.edu 1036019Shines@cs.fsu.edu public: 1046019Shines@cs.fsu.edu // 1056019Shines@cs.fsu.edu enum Status { 1066019Shines@cs.fsu.edu Running, 1076019Shines@cs.fsu.edu Idle, 1086019Shines@cs.fsu.edu IcacheMissStall, 1096019Shines@cs.fsu.edu IcacheMissComplete, 1106019Shines@cs.fsu.edu DcacheMissStall, 1116019Shines@cs.fsu.edu SwitchedOut 1126019Shines@cs.fsu.edu }; 1136019Shines@cs.fsu.edu 1146019Shines@cs.fsu.edu private: 1156019Shines@cs.fsu.edu Status _status; 1166019Shines@cs.fsu.edu 1176019Shines@cs.fsu.edu public: 1186019Shines@cs.fsu.edu void post_interrupt(int int_num, int index); 1196019Shines@cs.fsu.edu 1206019Shines@cs.fsu.edu void zero_fill_64(Addr addr) { 1216019Shines@cs.fsu.edu static int warned = 0; 1226019Shines@cs.fsu.edu if (!warned) { 1236019Shines@cs.fsu.edu warn ("WH64 is not implemented"); 1246019Shines@cs.fsu.edu warned = 1; 1256019Shines@cs.fsu.edu } 1266019Shines@cs.fsu.edu }; 1276019Shines@cs.fsu.edu 1286019Shines@cs.fsu.edu#ifdef FULL_SYSTEM 1296019Shines@cs.fsu.edu 1306019Shines@cs.fsu.edu SimpleCPU(const std::string &_name, 1316019Shines@cs.fsu.edu System *_system, 1326019Shines@cs.fsu.edu Counter max_insts_any_thread, Counter max_insts_all_threads, 1336019Shines@cs.fsu.edu Counter max_loads_any_thread, Counter max_loads_all_threads, 1346019Shines@cs.fsu.edu AlphaItb *itb, AlphaDtb *dtb, FunctionalMemory *mem, 1356019Shines@cs.fsu.edu MemInterface *icache_interface, MemInterface *dcache_interface, 1366019Shines@cs.fsu.edu Tick freq); 1376019Shines@cs.fsu.edu 1386019Shines@cs.fsu.edu#else 1396019Shines@cs.fsu.edu 1406019Shines@cs.fsu.edu SimpleCPU(const std::string &_name, Process *_process, 1416019Shines@cs.fsu.edu Counter max_insts_any_thread, 1426019Shines@cs.fsu.edu Counter max_insts_all_threads, 1436019Shines@cs.fsu.edu Counter max_loads_any_thread, 1446019Shines@cs.fsu.edu Counter max_loads_all_threads, 1456019Shines@cs.fsu.edu MemInterface *icache_interface, MemInterface *dcache_interface); 1466019Shines@cs.fsu.edu 1476019Shines@cs.fsu.edu#endif 1486019Shines@cs.fsu.edu 1496019Shines@cs.fsu.edu virtual ~SimpleCPU(); 1506019Shines@cs.fsu.edu 1516019Shines@cs.fsu.edu // execution context 1526019Shines@cs.fsu.edu ExecContext *xc; 1536019Shines@cs.fsu.edu 1546019Shines@cs.fsu.edu void switchOut(); 1556019Shines@cs.fsu.edu void takeOverFrom(BaseCPU *oldCPU); 1566019Shines@cs.fsu.edu 1576019Shines@cs.fsu.edu#ifdef FULL_SYSTEM 1586019Shines@cs.fsu.edu Addr dbg_vtophys(Addr addr); 1596019Shines@cs.fsu.edu 1606019Shines@cs.fsu.edu bool interval_stats; 1616019Shines@cs.fsu.edu#endif 1626019Shines@cs.fsu.edu 1636019Shines@cs.fsu.edu // L1 instruction cache 1646019Shines@cs.fsu.edu MemInterface *icacheInterface; 1656019Shines@cs.fsu.edu 1666019Shines@cs.fsu.edu // L1 data cache 1676019Shines@cs.fsu.edu MemInterface *dcacheInterface; 1686019Shines@cs.fsu.edu 1696019Shines@cs.fsu.edu // current instruction 1706019Shines@cs.fsu.edu MachInst inst; 1716019Shines@cs.fsu.edu 1726019Shines@cs.fsu.edu // Refcounted pointer to the one memory request. 1736019Shines@cs.fsu.edu MemReqPtr memReq; 1746019Shines@cs.fsu.edu 1756019Shines@cs.fsu.edu class CacheCompletionEvent : public Event 1766019Shines@cs.fsu.edu { 1776019Shines@cs.fsu.edu private: 1786019Shines@cs.fsu.edu SimpleCPU *cpu; 1796019Shines@cs.fsu.edu 1806019Shines@cs.fsu.edu public: 1816019Shines@cs.fsu.edu CacheCompletionEvent(SimpleCPU *_cpu); 1826019Shines@cs.fsu.edu 1836019Shines@cs.fsu.edu virtual void process(); 1846019Shines@cs.fsu.edu virtual const char *description(); 1856019Shines@cs.fsu.edu }; 1866019Shines@cs.fsu.edu 1876019Shines@cs.fsu.edu CacheCompletionEvent cacheCompletionEvent; 1886019Shines@cs.fsu.edu 1896019Shines@cs.fsu.edu Status status() const { return _status; } 1906019Shines@cs.fsu.edu 1916019Shines@cs.fsu.edu virtual void activateContext(int thread_num, int delay); 1926019Shines@cs.fsu.edu virtual void suspendContext(int thread_num); 1936019Shines@cs.fsu.edu virtual void deallocateContext(int thread_num); 1946019Shines@cs.fsu.edu virtual void haltContext(int thread_num); 1956019Shines@cs.fsu.edu 1966019Shines@cs.fsu.edu // statistics 1976019Shines@cs.fsu.edu virtual void regStats(); 1986019Shines@cs.fsu.edu virtual void resetStats(); 1996019Shines@cs.fsu.edu 2006019Shines@cs.fsu.edu // number of simulated instructions 2016019Shines@cs.fsu.edu Counter numInst; 2026019Shines@cs.fsu.edu Counter startNumInst; 2036019Shines@cs.fsu.edu Statistics::Formula numInsts; 2046019Shines@cs.fsu.edu 2056019Shines@cs.fsu.edu // number of simulated memory references 2066019Shines@cs.fsu.edu Statistics::Scalar<> numMemRefs; 2076019Shines@cs.fsu.edu 2086019Shines@cs.fsu.edu // number of simulated loads 2096019Shines@cs.fsu.edu Counter numLoad; 2106019Shines@cs.fsu.edu Counter startNumLoad; 2116019Shines@cs.fsu.edu 2126019Shines@cs.fsu.edu // number of idle cycles 2136019Shines@cs.fsu.edu Statistics::Average<> notIdleFraction; 2146019Shines@cs.fsu.edu Statistics::Formula idleFraction; 2156019Shines@cs.fsu.edu 2166019Shines@cs.fsu.edu // number of cycles stalled for I-cache misses 2176019Shines@cs.fsu.edu Statistics::Scalar<> icacheStallCycles; 2186019Shines@cs.fsu.edu Counter lastIcacheStall; 2196019Shines@cs.fsu.edu 2206019Shines@cs.fsu.edu // number of cycles stalled for D-cache misses 2216019Shines@cs.fsu.edu Statistics::Scalar<> dcacheStallCycles; 2226019Shines@cs.fsu.edu Counter lastDcacheStall; 2236019Shines@cs.fsu.edu 2246019Shines@cs.fsu.edu void processCacheCompletion(); 2256019Shines@cs.fsu.edu 2266019Shines@cs.fsu.edu virtual void serialize(std::ostream &os); 2276019Shines@cs.fsu.edu virtual void unserialize(Checkpoint *cp, const std::string §ion); 2286019Shines@cs.fsu.edu 2296019Shines@cs.fsu.edu template <class T> 2306019Shines@cs.fsu.edu Fault read(Addr addr, T& data, unsigned flags); 2316019Shines@cs.fsu.edu 2326019Shines@cs.fsu.edu template <class T> 2336019Shines@cs.fsu.edu Fault write(T data, Addr addr, unsigned flags, 2346019Shines@cs.fsu.edu uint64_t *res); 2356019Shines@cs.fsu.edu 2366019Shines@cs.fsu.edu Fault prefetch(Addr addr, unsigned flags) 2376019Shines@cs.fsu.edu { 2386019Shines@cs.fsu.edu // need to do this... 2396019Shines@cs.fsu.edu return No_Fault; 2406019Shines@cs.fsu.edu } 2416019Shines@cs.fsu.edu 2426019Shines@cs.fsu.edu void writeHint(Addr addr, int size) 2436019Shines@cs.fsu.edu { 2446019Shines@cs.fsu.edu // need to do this... 2456019Shines@cs.fsu.edu } 2466019Shines@cs.fsu.edu}; 2476019Shines@cs.fsu.edu 2486019Shines@cs.fsu.edu#endif // __SIMPLE_CPU_HH__ 2496019Shines@cs.fsu.edu