base.hh revision 3735
12SN/A/*
21762SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan
32SN/A * All rights reserved.
42SN/A *
52SN/A * Redistribution and use in source and binary forms, with or without
62SN/A * modification, are permitted provided that the following conditions are
72SN/A * met: redistributions of source code must retain the above copyright
82SN/A * notice, this list of conditions and the following disclaimer;
92SN/A * redistributions in binary form must reproduce the above copyright
102SN/A * notice, this list of conditions and the following disclaimer in the
112SN/A * documentation and/or other materials provided with the distribution;
122SN/A * neither the name of the copyright holders nor the names of its
132SN/A * contributors may be used to endorse or promote products derived from
142SN/A * this software without specific prior written permission.
152SN/A *
162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
272665Ssaidi@eecs.umich.edu *
282665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt
292665Ssaidi@eecs.umich.edu *          Dave Greene
302665Ssaidi@eecs.umich.edu *          Nathan Binkert
312SN/A */
322SN/A
332623SN/A#ifndef __CPU_SIMPLE_BASE_HH__
342623SN/A#define __CPU_SIMPLE_BASE_HH__
352SN/A
361354SN/A#include "base/statistics.hh"
371858SN/A#include "config/full_system.hh"
381717SN/A#include "cpu/base.hh"
392683Sktlim@umich.edu#include "cpu/simple_thread.hh"
401354SN/A#include "cpu/pc_event.hh"
411354SN/A#include "cpu/static_inst.hh"
422387SN/A#include "mem/packet.hh"
432387SN/A#include "mem/port.hh"
442387SN/A#include "mem/request.hh"
4556SN/A#include "sim/eventq.hh"
462SN/A
472SN/A// forward declarations
481858SN/A#if FULL_SYSTEM
492SN/Aclass Processor;
503453Sgblack@eecs.umich.edunamespace TheISA
513453Sgblack@eecs.umich.edu{
523453Sgblack@eecs.umich.edu    class ITB;
533453Sgblack@eecs.umich.edu    class DTB;
543453Sgblack@eecs.umich.edu}
552462SN/Aclass MemObject;
562SN/A
572SN/Aclass RemoteGDB;
582SN/Aclass GDBListener;
59715SN/A
60715SN/A#else
61715SN/A
62715SN/Aclass Process;
63715SN/A
642SN/A#endif // FULL_SYSTEM
652SN/A
662680Sktlim@umich.educlass ThreadContext;
67237SN/Aclass Checkpoint;
682SN/A
692SN/Anamespace Trace {
702SN/A    class InstRecord;
712SN/A}
722SN/A
732420SN/A
742623SN/Aclass BaseSimpleCPU : public BaseCPU
752SN/A{
762107SN/A  protected:
772107SN/A    typedef TheISA::MachInst MachInst;
782159SN/A    typedef TheISA::MiscReg MiscReg;
792455SN/A    typedef TheISA::FloatReg FloatReg;
802455SN/A    typedef TheISA::FloatRegBits FloatRegBits;
812386SN/A
822623SN/A  protected:
832SN/A    Trace::InstRecord *traceData;
841371SN/A
852SN/A  public:
862SN/A    void post_interrupt(int int_num, int index);
872SN/A
882SN/A    void zero_fill_64(Addr addr) {
892SN/A      static int warned = 0;
902SN/A      if (!warned) {
912SN/A        warn ("WH64 is not implemented");
922SN/A        warned = 1;
932SN/A      }
942SN/A    };
952SN/A
961400SN/A  public:
971400SN/A    struct Params : public BaseCPU::Params
981400SN/A    {
991858SN/A#if FULL_SYSTEM
1003453Sgblack@eecs.umich.edu        TheISA::ITB *itb;
1013453Sgblack@eecs.umich.edu        TheISA::DTB *dtb;
1022SN/A#else
1031400SN/A        Process *process;
1042SN/A#endif
1051400SN/A    };
1062623SN/A    BaseSimpleCPU(Params *params);
1072623SN/A    virtual ~BaseSimpleCPU();
1082SN/A
1091400SN/A  public:
1102683Sktlim@umich.edu    /** SimpleThread object, provides all the architectural state. */
1112683Sktlim@umich.edu    SimpleThread *thread;
1122190SN/A
1132683Sktlim@umich.edu    /** ThreadContext object, provides an interface for external
1142683Sktlim@umich.edu     * objects to modify this thread's state.
1152683Sktlim@umich.edu     */
1162680Sktlim@umich.edu    ThreadContext *tc;
1172SN/A
1181858SN/A#if FULL_SYSTEM
1192SN/A    Addr dbg_vtophys(Addr addr);
1202SN/A
1212SN/A    bool interval_stats;
1222SN/A#endif
1232SN/A
1242SN/A    // current instruction
1252SN/A    MachInst inst;
1262SN/A
1272566SN/A    // Static data storage
1282566SN/A    TheISA::IntReg dataReg;
1292566SN/A
1302107SN/A    StaticInstPtr curStaticInst;
1313276Sgblack@eecs.umich.edu    StaticInstPtr curMacroStaticInst;
1321469SN/A
1332623SN/A    void checkForInterrupts();
1342662Sstever@eecs.umich.edu    Fault setupFetchRequest(Request *req);
1352623SN/A    void preExecute();
1362623SN/A    void postExecute();
1372623SN/A    void advancePC(Fault fault);
138180SN/A
139393SN/A    virtual void deallocateContext(int thread_num);
140393SN/A    virtual void haltContext(int thread_num);
1412SN/A
1422SN/A    // statistics
143334SN/A    virtual void regStats();
144334SN/A    virtual void resetStats();
1452SN/A
1462SN/A    // number of simulated instructions
1472SN/A    Counter numInst;
148334SN/A    Counter startNumInst;
149729SN/A    Stats::Scalar<> numInsts;
150707SN/A
151707SN/A    virtual Counter totalInstructions() const
152707SN/A    {
153707SN/A        return numInst - startNumInst;
154707SN/A    }
1552SN/A
1562SN/A    // number of simulated memory references
157729SN/A    Stats::Scalar<> numMemRefs;
1582SN/A
159124SN/A    // number of simulated loads
160124SN/A    Counter numLoad;
161334SN/A    Counter startNumLoad;
162124SN/A
1632SN/A    // number of idle cycles
164729SN/A    Stats::Average<> notIdleFraction;
165729SN/A    Stats::Formula idleFraction;
1662SN/A
1672390SN/A    // number of cycles stalled for I-cache responses
168729SN/A    Stats::Scalar<> icacheStallCycles;
1692SN/A    Counter lastIcacheStall;
1702SN/A
1712390SN/A    // number of cycles stalled for I-cache retries
1722390SN/A    Stats::Scalar<> icacheRetryCycles;
1732390SN/A    Counter lastIcacheRetry;
1742390SN/A
1752390SN/A    // number of cycles stalled for D-cache responses
176729SN/A    Stats::Scalar<> dcacheStallCycles;
1772SN/A    Counter lastDcacheStall;
1782SN/A
1792390SN/A    // number of cycles stalled for D-cache retries
1802390SN/A    Stats::Scalar<> dcacheRetryCycles;
1812390SN/A    Counter lastDcacheRetry;
1822390SN/A
183217SN/A    virtual void serialize(std::ostream &os);
184237SN/A    virtual void unserialize(Checkpoint *cp, const std::string &section);
1852SN/A
1861371SN/A    // These functions are only used in CPU models that split
1871371SN/A    // effective address computation from the actual memory access.
1882623SN/A    void setEA(Addr EA) { panic("BaseSimpleCPU::setEA() not implemented\n"); }
1892623SN/A    Addr getEA() 	{ panic("BaseSimpleCPU::getEA() not implemented\n"); }
1901371SN/A
191581SN/A    void prefetch(Addr addr, unsigned flags)
1922SN/A    {
1932SN/A        // need to do this...
1942SN/A    }
1952SN/A
196753SN/A    void writeHint(Addr addr, int size, unsigned flags)
1972SN/A    {
1982SN/A        // need to do this...
1992SN/A    }
200594SN/A
201595SN/A    Fault copySrcTranslate(Addr src);
202594SN/A
203595SN/A    Fault copy(Addr dest);
204705SN/A
205726SN/A    // The register accessor methods provide the index of the
206726SN/A    // instruction's operand (e.g., 0 or 1), not the architectural
207726SN/A    // register index, to simplify the implementation of register
208726SN/A    // renaming.  We find the architectural register index by indexing
209726SN/A    // into the instruction's own operand index table.  Note that a
210726SN/A    // raw pointer to the StaticInst is provided instead of a
211726SN/A    // ref-counted StaticInstPtr to redice overhead.  This is fine as
212726SN/A    // long as these methods don't copy the pointer into any long-term
213726SN/A    // storage (which is pretty hard to imagine they would have reason
214726SN/A    // to do).
215705SN/A
2163735Sstever@eecs.umich.edu    uint64_t readIntRegOperand(const StaticInst *si, int idx)
217726SN/A    {
2182683Sktlim@umich.edu        return thread->readIntReg(si->srcRegIdx(idx));
219726SN/A    }
220705SN/A
2213735Sstever@eecs.umich.edu    FloatReg readFloatRegOperand(const StaticInst *si, int idx, int width)
222726SN/A    {
223726SN/A        int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
2242683Sktlim@umich.edu        return thread->readFloatReg(reg_idx, width);
225726SN/A    }
226705SN/A
2273735Sstever@eecs.umich.edu    FloatReg readFloatRegOperand(const StaticInst *si, int idx)
228726SN/A    {
229726SN/A        int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
2302683Sktlim@umich.edu        return thread->readFloatReg(reg_idx);
231726SN/A    }
232705SN/A
2333735Sstever@eecs.umich.edu    FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx,
2343735Sstever@eecs.umich.edu                                         int width)
235726SN/A    {
236726SN/A        int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
2372683Sktlim@umich.edu        return thread->readFloatRegBits(reg_idx, width);
2382455SN/A    }
2392455SN/A
2403735Sstever@eecs.umich.edu    FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx)
2412455SN/A    {
2422455SN/A        int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
2432683Sktlim@umich.edu        return thread->readFloatRegBits(reg_idx);
244726SN/A    }
245705SN/A
2463735Sstever@eecs.umich.edu    void setIntRegOperand(const StaticInst *si, int idx, uint64_t val)
247726SN/A    {
2482683Sktlim@umich.edu        thread->setIntReg(si->destRegIdx(idx), val);
249726SN/A    }
250705SN/A
2513735Sstever@eecs.umich.edu    void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val,
2523735Sstever@eecs.umich.edu                            int width)
253726SN/A    {
254726SN/A        int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
2552683Sktlim@umich.edu        thread->setFloatReg(reg_idx, val, width);
256726SN/A    }
257705SN/A
2583735Sstever@eecs.umich.edu    void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
259726SN/A    {
260726SN/A        int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
2612683Sktlim@umich.edu        thread->setFloatReg(reg_idx, val);
262726SN/A    }
263726SN/A
2643735Sstever@eecs.umich.edu    void setFloatRegOperandBits(const StaticInst *si, int idx,
2653735Sstever@eecs.umich.edu                                FloatRegBits val, int width)
266726SN/A    {
267726SN/A        int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
2682683Sktlim@umich.edu        thread->setFloatRegBits(reg_idx, val, width);
2692455SN/A    }
2702455SN/A
2713735Sstever@eecs.umich.edu    void setFloatRegOperandBits(const StaticInst *si, int idx,
2723735Sstever@eecs.umich.edu                                FloatRegBits val)
2732455SN/A    {
2742455SN/A        int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
2752683Sktlim@umich.edu        thread->setFloatRegBits(reg_idx, val);
276726SN/A    }
277705SN/A
2782683Sktlim@umich.edu    uint64_t readPC() { return thread->readPC(); }
2792683Sktlim@umich.edu    uint64_t readNextPC() { return thread->readNextPC(); }
2802683Sktlim@umich.edu    uint64_t readNextNPC() { return thread->readNextNPC(); }
2812447SN/A
2822683Sktlim@umich.edu    void setPC(uint64_t val) { thread->setPC(val); }
2832683Sktlim@umich.edu    void setNextPC(uint64_t val) { thread->setNextPC(val); }
2842683Sktlim@umich.edu    void setNextNPC(uint64_t val) { thread->setNextNPC(val); }
285705SN/A
2862159SN/A    MiscReg readMiscReg(int misc_reg)
2872159SN/A    {
2882683Sktlim@umich.edu        return thread->readMiscReg(misc_reg);
2892159SN/A    }
290705SN/A
2913468Sgblack@eecs.umich.edu    MiscReg readMiscRegWithEffect(int misc_reg)
2922159SN/A    {
2933468Sgblack@eecs.umich.edu        return thread->readMiscRegWithEffect(misc_reg);
2942159SN/A    }
2952159SN/A
2963468Sgblack@eecs.umich.edu    void setMiscReg(int misc_reg, const MiscReg &val)
2972159SN/A    {
2982683Sktlim@umich.edu        return thread->setMiscReg(misc_reg, val);
2992159SN/A    }
3002159SN/A
3013468Sgblack@eecs.umich.edu    void setMiscRegWithEffect(int misc_reg, const MiscReg &val)
3022159SN/A    {
3032683Sktlim@umich.edu        return thread->setMiscRegWithEffect(misc_reg, val);
3042159SN/A    }
305705SN/A
3061858SN/A#if FULL_SYSTEM
3072683Sktlim@umich.edu    Fault hwrei() { return thread->hwrei(); }
3082680Sktlim@umich.edu    void ev5_trap(Fault fault) { fault->invoke(tc); }
3092683Sktlim@umich.edu    bool simPalCheck(int palFunc) { return thread->simPalCheck(palFunc); }
310705SN/A#else
3112683Sktlim@umich.edu    void syscall(int64_t callnum) { thread->syscall(callnum); }
312705SN/A#endif
313705SN/A
3142683Sktlim@umich.edu    bool misspeculating() { return thread->misspeculating(); }
3152680Sktlim@umich.edu    ThreadContext *tcBase() { return tc; }
3162SN/A};
3172SN/A
3182623SN/A#endif // __CPU_SIMPLE_BASE_HH__
319