base.hh revision 3468
12SN/A/*
21762SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan
32SN/A * All rights reserved.
42SN/A *
52SN/A * Redistribution and use in source and binary forms, with or without
62SN/A * modification, are permitted provided that the following conditions are
72SN/A * met: redistributions of source code must retain the above copyright
82SN/A * notice, this list of conditions and the following disclaimer;
92SN/A * redistributions in binary form must reproduce the above copyright
102SN/A * notice, this list of conditions and the following disclaimer in the
112SN/A * documentation and/or other materials provided with the distribution;
122SN/A * neither the name of the copyright holders nor the names of its
132SN/A * contributors may be used to endorse or promote products derived from
142SN/A * this software without specific prior written permission.
152SN/A *
162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
272665Ssaidi@eecs.umich.edu *
282665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt
292665Ssaidi@eecs.umich.edu *          Dave Greene
302665Ssaidi@eecs.umich.edu *          Nathan Binkert
312SN/A */
322SN/A
332623SN/A#ifndef __CPU_SIMPLE_BASE_HH__
342623SN/A#define __CPU_SIMPLE_BASE_HH__
352SN/A
361354SN/A#include "base/statistics.hh"
371858SN/A#include "config/full_system.hh"
381717SN/A#include "cpu/base.hh"
392683Sktlim@umich.edu#include "cpu/simple_thread.hh"
401354SN/A#include "cpu/pc_event.hh"
411354SN/A#include "cpu/static_inst.hh"
422387SN/A#include "mem/packet.hh"
432387SN/A#include "mem/port.hh"
442387SN/A#include "mem/request.hh"
4556SN/A#include "sim/eventq.hh"
462SN/A
472SN/A// forward declarations
481858SN/A#if FULL_SYSTEM
492SN/Aclass Processor;
503453Sgblack@eecs.umich.edunamespace TheISA
513453Sgblack@eecs.umich.edu{
523453Sgblack@eecs.umich.edu    class ITB;
533453Sgblack@eecs.umich.edu    class DTB;
543453Sgblack@eecs.umich.edu}
552462SN/Aclass MemObject;
562SN/A
572SN/Aclass RemoteGDB;
582SN/Aclass GDBListener;
59715SN/A
60715SN/A#else
61715SN/A
62715SN/Aclass Process;
63715SN/A
642SN/A#endif // FULL_SYSTEM
652SN/A
662680Sktlim@umich.educlass ThreadContext;
67237SN/Aclass Checkpoint;
682SN/A
692SN/Anamespace Trace {
702SN/A    class InstRecord;
712SN/A}
722SN/A
732420SN/A
742623SN/Aclass BaseSimpleCPU : public BaseCPU
752SN/A{
762107SN/A  protected:
772107SN/A    typedef TheISA::MachInst MachInst;
782159SN/A    typedef TheISA::MiscReg MiscReg;
792455SN/A    typedef TheISA::FloatReg FloatReg;
802455SN/A    typedef TheISA::FloatRegBits FloatRegBits;
812386SN/A
822499SN/A    MemObject *mem;
832386SN/A
842623SN/A  protected:
852SN/A    Trace::InstRecord *traceData;
861371SN/A
872SN/A  public:
882SN/A    void post_interrupt(int int_num, int index);
892SN/A
902SN/A    void zero_fill_64(Addr addr) {
912SN/A      static int warned = 0;
922SN/A      if (!warned) {
932SN/A        warn ("WH64 is not implemented");
942SN/A        warned = 1;
952SN/A      }
962SN/A    };
972SN/A
981400SN/A  public:
991400SN/A    struct Params : public BaseCPU::Params
1001400SN/A    {
1012542SN/A        MemObject *mem;
1021858SN/A#if FULL_SYSTEM
1033453Sgblack@eecs.umich.edu        TheISA::ITB *itb;
1043453Sgblack@eecs.umich.edu        TheISA::DTB *dtb;
1052SN/A#else
1061400SN/A        Process *process;
1072SN/A#endif
1081400SN/A    };
1092623SN/A    BaseSimpleCPU(Params *params);
1102623SN/A    virtual ~BaseSimpleCPU();
1112SN/A
1121400SN/A  public:
1132683Sktlim@umich.edu    /** SimpleThread object, provides all the architectural state. */
1142683Sktlim@umich.edu    SimpleThread *thread;
1152190SN/A
1162683Sktlim@umich.edu    /** ThreadContext object, provides an interface for external
1172683Sktlim@umich.edu     * objects to modify this thread's state.
1182683Sktlim@umich.edu     */
1192680Sktlim@umich.edu    ThreadContext *tc;
1202SN/A
1211858SN/A#if FULL_SYSTEM
1222SN/A    Addr dbg_vtophys(Addr addr);
1232SN/A
1242SN/A    bool interval_stats;
1252SN/A#endif
1262SN/A
1272SN/A    // current instruction
1282SN/A    MachInst inst;
1292SN/A
1302566SN/A    // Static data storage
1312566SN/A    TheISA::IntReg dataReg;
1322566SN/A
1332107SN/A    StaticInstPtr curStaticInst;
1343276Sgblack@eecs.umich.edu    StaticInstPtr curMacroStaticInst;
1351469SN/A
1362623SN/A    void checkForInterrupts();
1372662Sstever@eecs.umich.edu    Fault setupFetchRequest(Request *req);
1382623SN/A    void preExecute();
1392623SN/A    void postExecute();
1402623SN/A    void advancePC(Fault fault);
141180SN/A
142393SN/A    virtual void deallocateContext(int thread_num);
143393SN/A    virtual void haltContext(int thread_num);
1442SN/A
1452SN/A    // statistics
146334SN/A    virtual void regStats();
147334SN/A    virtual void resetStats();
1482SN/A
1492SN/A    // number of simulated instructions
1502SN/A    Counter numInst;
151334SN/A    Counter startNumInst;
152729SN/A    Stats::Scalar<> numInsts;
153707SN/A
154707SN/A    virtual Counter totalInstructions() const
155707SN/A    {
156707SN/A        return numInst - startNumInst;
157707SN/A    }
1582SN/A
1592SN/A    // number of simulated memory references
160729SN/A    Stats::Scalar<> numMemRefs;
1612SN/A
162124SN/A    // number of simulated loads
163124SN/A    Counter numLoad;
164334SN/A    Counter startNumLoad;
165124SN/A
1662SN/A    // number of idle cycles
167729SN/A    Stats::Average<> notIdleFraction;
168729SN/A    Stats::Formula idleFraction;
1692SN/A
1702390SN/A    // number of cycles stalled for I-cache responses
171729SN/A    Stats::Scalar<> icacheStallCycles;
1722SN/A    Counter lastIcacheStall;
1732SN/A
1742390SN/A    // number of cycles stalled for I-cache retries
1752390SN/A    Stats::Scalar<> icacheRetryCycles;
1762390SN/A    Counter lastIcacheRetry;
1772390SN/A
1782390SN/A    // number of cycles stalled for D-cache responses
179729SN/A    Stats::Scalar<> dcacheStallCycles;
1802SN/A    Counter lastDcacheStall;
1812SN/A
1822390SN/A    // number of cycles stalled for D-cache retries
1832390SN/A    Stats::Scalar<> dcacheRetryCycles;
1842390SN/A    Counter lastDcacheRetry;
1852390SN/A
186217SN/A    virtual void serialize(std::ostream &os);
187237SN/A    virtual void unserialize(Checkpoint *cp, const std::string &section);
1882SN/A
1891371SN/A    // These functions are only used in CPU models that split
1901371SN/A    // effective address computation from the actual memory access.
1912623SN/A    void setEA(Addr EA) { panic("BaseSimpleCPU::setEA() not implemented\n"); }
1922623SN/A    Addr getEA() 	{ panic("BaseSimpleCPU::getEA() not implemented\n"); }
1931371SN/A
194581SN/A    void prefetch(Addr addr, unsigned flags)
1952SN/A    {
1962SN/A        // need to do this...
1972SN/A    }
1982SN/A
199753SN/A    void writeHint(Addr addr, int size, unsigned flags)
2002SN/A    {
2012SN/A        // need to do this...
2022SN/A    }
203594SN/A
204595SN/A    Fault copySrcTranslate(Addr src);
205594SN/A
206595SN/A    Fault copy(Addr dest);
207705SN/A
208726SN/A    // The register accessor methods provide the index of the
209726SN/A    // instruction's operand (e.g., 0 or 1), not the architectural
210726SN/A    // register index, to simplify the implementation of register
211726SN/A    // renaming.  We find the architectural register index by indexing
212726SN/A    // into the instruction's own operand index table.  Note that a
213726SN/A    // raw pointer to the StaticInst is provided instead of a
214726SN/A    // ref-counted StaticInstPtr to redice overhead.  This is fine as
215726SN/A    // long as these methods don't copy the pointer into any long-term
216726SN/A    // storage (which is pretty hard to imagine they would have reason
217726SN/A    // to do).
218705SN/A
2192107SN/A    uint64_t readIntReg(const StaticInst *si, int idx)
220726SN/A    {
2212683Sktlim@umich.edu        return thread->readIntReg(si->srcRegIdx(idx));
222726SN/A    }
223705SN/A
2242455SN/A    FloatReg readFloatReg(const StaticInst *si, int idx, int width)
225726SN/A    {
226726SN/A        int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
2272683Sktlim@umich.edu        return thread->readFloatReg(reg_idx, width);
228726SN/A    }
229705SN/A
2302455SN/A    FloatReg readFloatReg(const StaticInst *si, int idx)
231726SN/A    {
232726SN/A        int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
2332683Sktlim@umich.edu        return thread->readFloatReg(reg_idx);
234726SN/A    }
235705SN/A
2362455SN/A    FloatRegBits readFloatRegBits(const StaticInst *si, int idx, int width)
237726SN/A    {
238726SN/A        int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
2392683Sktlim@umich.edu        return thread->readFloatRegBits(reg_idx, width);
2402455SN/A    }
2412455SN/A
2422455SN/A    FloatRegBits readFloatRegBits(const StaticInst *si, int idx)
2432455SN/A    {
2442455SN/A        int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
2452683Sktlim@umich.edu        return thread->readFloatRegBits(reg_idx);
246726SN/A    }
247705SN/A
2482107SN/A    void setIntReg(const StaticInst *si, int idx, uint64_t val)
249726SN/A    {
2502683Sktlim@umich.edu        thread->setIntReg(si->destRegIdx(idx), val);
251726SN/A    }
252705SN/A
2532455SN/A    void setFloatReg(const StaticInst *si, int idx, FloatReg val, int width)
254726SN/A    {
255726SN/A        int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
2562683Sktlim@umich.edu        thread->setFloatReg(reg_idx, val, width);
257726SN/A    }
258705SN/A
2592455SN/A    void setFloatReg(const StaticInst *si, int idx, FloatReg val)
260726SN/A    {
261726SN/A        int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
2622683Sktlim@umich.edu        thread->setFloatReg(reg_idx, val);
263726SN/A    }
264726SN/A
2652455SN/A    void setFloatRegBits(const StaticInst *si, int idx,
2662577SN/A                         FloatRegBits val, int width)
267726SN/A    {
268726SN/A        int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
2692683Sktlim@umich.edu        thread->setFloatRegBits(reg_idx, val, width);
2702455SN/A    }
2712455SN/A
2722455SN/A    void setFloatRegBits(const StaticInst *si, int idx, FloatRegBits val)
2732455SN/A    {
2742455SN/A        int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
2752683Sktlim@umich.edu        thread->setFloatRegBits(reg_idx, val);
276726SN/A    }
277705SN/A
2782683Sktlim@umich.edu    uint64_t readPC() { return thread->readPC(); }
2792683Sktlim@umich.edu    uint64_t readNextPC() { return thread->readNextPC(); }
2802683Sktlim@umich.edu    uint64_t readNextNPC() { return thread->readNextNPC(); }
2812447SN/A
2822683Sktlim@umich.edu    void setPC(uint64_t val) { thread->setPC(val); }
2832683Sktlim@umich.edu    void setNextPC(uint64_t val) { thread->setNextPC(val); }
2842683Sktlim@umich.edu    void setNextNPC(uint64_t val) { thread->setNextNPC(val); }
285705SN/A
2862159SN/A    MiscReg readMiscReg(int misc_reg)
2872159SN/A    {
2882683Sktlim@umich.edu        return thread->readMiscReg(misc_reg);
2892159SN/A    }
290705SN/A
2913468Sgblack@eecs.umich.edu    MiscReg readMiscRegWithEffect(int misc_reg)
2922159SN/A    {
2933468Sgblack@eecs.umich.edu        return thread->readMiscRegWithEffect(misc_reg);
2942159SN/A    }
2952159SN/A
2963468Sgblack@eecs.umich.edu    void setMiscReg(int misc_reg, const MiscReg &val)
2972159SN/A    {
2982683Sktlim@umich.edu        return thread->setMiscReg(misc_reg, val);
2992159SN/A    }
3002159SN/A
3013468Sgblack@eecs.umich.edu    void setMiscRegWithEffect(int misc_reg, const MiscReg &val)
3022159SN/A    {
3032683Sktlim@umich.edu        return thread->setMiscRegWithEffect(misc_reg, val);
3042159SN/A    }
305705SN/A
3061858SN/A#if FULL_SYSTEM
3072683Sktlim@umich.edu    Fault hwrei() { return thread->hwrei(); }
3082683Sktlim@umich.edu    bool inPalMode() { return thread->inPalMode(); }
3092680Sktlim@umich.edu    void ev5_trap(Fault fault) { fault->invoke(tc); }
3102683Sktlim@umich.edu    bool simPalCheck(int palFunc) { return thread->simPalCheck(palFunc); }
311705SN/A#else
3122683Sktlim@umich.edu    void syscall(int64_t callnum) { thread->syscall(callnum); }
313705SN/A#endif
314705SN/A
3152683Sktlim@umich.edu    bool misspeculating() { return thread->misspeculating(); }
3162680Sktlim@umich.edu    ThreadContext *tcBase() { return tc; }
3172SN/A};
3182SN/A
3192623SN/A#endif // __CPU_SIMPLE_BASE_HH__
320